2 ## Compute the location and size of where this firmware image
3 ## (coreboot plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FAILOVER_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
10 default ROM_SECTION_SIZE = FALLBACK_SIZE
11 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
13 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
14 default ROM_SECTION_OFFSET = 0
19 ## Compute the start location and size size of
20 ## The coreboot bootloader.
22 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
23 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
26 ## Compute where this copy of coreboot will start in the boot rom
28 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
31 ## Compute a range of ROM that can cached to speed up coreboot,
34 ## XIP_ROM_SIZE must be a power of 2.
35 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
37 default XIP_ROM_SIZE=65536
40 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
43 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
45 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
52 ## Build the objects we have code for in this directory.
59 #needed by irq_tables and mptable and acpi_tables
71 # object acpi_tables.o
73 # if SB_HT_CHAIN_ON_BUS0
80 # if SB_HT_CHAIN_ON_BUS0
92 depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
93 action "iasl -p $(PWD)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
94 action "mv dsdt_lb.hex dsdt.c"
98 #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
102 depends "$(MAINBOARD)/dx/pci2.asl"
103 action "iasl -p $(PWD)/pci2 -tc $(MAINBOARD)/dx/pci2.asl"
104 action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
105 action "mv pci2.hex ssdt2.c"
109 depends "$(MAINBOARD)/dx/pci3.asl"
110 action "iasl -p $(PWD)/pci3 -tc $(MAINBOARD)/dx/pci3.asl"
111 action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
112 action "mv pci3.hex ssdt3.c"
116 depends "$(MAINBOARD)/dx/pci4.asl"
117 action "iasl -p $(PWD)/pci4 -tc $(MAINBOARD)/dx/pci4.asl"
118 action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
119 action "mv pci4.hex ssdt4.c"
123 depends "$(MAINBOARD)/dx/pci5.asl"
124 action "iasl -p $(PWD)/pci5 -tc $(MAINBOARD)/dx/pci5.asl"
125 action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
126 action "mv pci5.hex ssdt5.c"
135 # compile cache_as_ram.c to auto.o
136 makerule ./cache_as_ram_auto.o
137 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
138 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
142 #compile cache_as_ram.c to auto.inc
143 makerule ./cache_as_ram_auto.inc
144 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
145 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
146 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
147 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
153 if USE_FAILOVER_IMAGE
155 if CONFIG_AP_CODE_IN_CAR
156 makerule ./apc_auto.o
157 depends "$(MAINBOARD)/apc_auto.c option_table.h"
158 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
160 ldscript /arch/i386/init/ldscript_apc.lb
165 ## Build our 16 bit and 32 bit coreboot entry code
168 if HAVE_FAILOVER_BOOT
169 if USE_FAILOVER_IMAGE
170 mainboardinit cpu/x86/16bit/entry16.inc
171 ldscript /cpu/x86/16bit/entry16.lds
174 if USE_FALLBACK_IMAGE
175 mainboardinit cpu/x86/16bit/entry16.inc
176 ldscript /cpu/x86/16bit/entry16.lds
180 mainboardinit cpu/x86/32bit/entry32.inc
183 ldscript /cpu/x86/32bit/entry32.lds
187 ldscript /cpu/amd/car/cache_as_ram.lds
192 ## Build our reset vector (This is where coreboot is entered)
194 if HAVE_FAILOVER_BOOT
195 if USE_FAILOVER_IMAGE
196 mainboardinit cpu/x86/16bit/reset16.inc
197 ldscript /cpu/x86/16bit/reset16.lds
199 mainboardinit cpu/x86/32bit/reset32.inc
200 ldscript /cpu/x86/32bit/reset32.lds
203 if USE_FALLBACK_IMAGE
204 mainboardinit cpu/x86/16bit/reset16.inc
205 ldscript /cpu/x86/16bit/reset16.lds
207 mainboardinit cpu/x86/32bit/reset32.inc
208 ldscript /cpu/x86/32bit/reset32.lds
213 ## Include an id string (For safe flashing)
215 mainboardinit arch/i386/lib/id.inc
216 ldscript /arch/i386/lib/id.lds
220 ## Setup Cache-As-Ram
222 mainboardinit cpu/amd/car/cache_as_ram.inc
226 ### This is the early phase of coreboot startup
227 ### Things are delicate and we test to see if we should
228 ### failover to another image.
230 if HAVE_FAILOVER_BOOT
231 if USE_FAILOVER_IMAGE
233 ldscript /arch/i386/lib/failover_failover.lds
237 if USE_FALLBACK_IMAGE
239 ldscript /arch/i386/lib/failover.lds
245 ### O.k. We aren't just an intermediary anymore!
254 initobject cache_as_ram_auto.o
256 mainboardinit ./cache_as_ram_auto.inc
262 ## Include the secondary Configuration files
266 dir /southbridge/amd/amd8132
268 chip northbridge/amd/amdk8/root_complex
269 device apic_cluster 0 on
270 chip cpu/amd/socket_940
274 device pci_domain 0 on
275 chip northbridge/amd/amdk8
276 device pci 18.0 on end
277 device pci 18.0 on end
278 device pci 18.0 on # northbridge
279 chip southbridge/amd/amd8131
280 # the on/off keyword is mandatory
281 device pci 0.0 on end
282 device pci 0.1 on end
283 device pci 1.0 on end
284 device pci 1.1 on end
286 chip southbridge/amd/amd8111
287 # this "device pci 0.0" is the parent the next one
290 device pci 0.0 on end
291 device pci 0.1 on end
292 device pci 0.2 off end
293 device pci 1.0 off end
294 #chip drivers/pci/onboard
295 # device pci 6.0 on end
296 # register "rom_address" = "0xfff80000"
300 chip superio/winbond/w83627hf
301 device pnp 2e.0 off # Floppy
306 device pnp 2e.1 off # Parallel Port
310 device pnp 2e.2 on # Com1
314 device pnp 2e.3 off # Com2
318 device pnp 2e.5 on # Keyboard
324 device pnp 2e.6 off # CIR
327 device pnp 2e.7 off # GAME_MIDI_GIPO1
332 device pnp 2e.8 on # GPIO2
338 device pnp 2e.9 off end # GPIO3
339 device pnp 2e.a off end # ACPI
340 device pnp 2e.b on # HW Monitor
346 device pci 1.1 on end
347 device pci 1.2 on end
349 chip drivers/generic/generic #dimm 0-0-0
352 chip drivers/generic/generic #dimm 0-0-1
355 chip drivers/generic/generic #dimm 0-1-0
358 chip drivers/generic/generic #dimm 0-1-1
361 chip drivers/generic/generic #dimm 1-0-0
364 chip drivers/generic/generic #dimm 1-0-1
367 chip drivers/generic/generic #dimm 1-1-0
370 chip drivers/generic/generic #dimm 1-1-1
374 device pci 1.5 off end
375 device pci 1.6 off end
376 register "ide0_enable" = "1"
377 register "ide1_enable" = "1"
379 end # device pci 18.0
381 device pci 18.1 on end
382 device pci 18.2 on end
383 device pci 18.3 on end
387 # chip drivers/generic/debug
388 # device pnp 0.0 off end # chip name
389 # device pnp 0.1 on end # pci_regs_all
390 # device pnp 0.2 off end # mem
391 # device pnp 0.3 off end # cpuid
392 # device pnp 0.4 off end # smbus_regs_all
393 # device pnp 0.5 off end # dual core msr
394 # device pnp 0.6 off end # cache size
395 # device pnp 0.7 off end # tsc