src/mainboard/intel/jarrell/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <stdlib.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "ram/ramtest.c"
  14 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
  15 #include "northbridge/intel/e7520/raminit.h"
  16 #include "superio/nsc/pc87427/pc87427.h"
  17 #include "cpu/x86/lapic/boot_cpu.c"
  18 #include "cpu/x86/mtrr/earlymtrr.c"
  19 #include "watchdog.c"
  20 #include "reset.c"
  21 #include "power_reset_check.c"
  22 #include "jarrell_fixups.c"
  23 #include "superio/nsc/pc87427/pc87427_early_init.c"
  24 #include "northbridge/intel/e7520/memory_initialized.c"
  25 #include "cpu/x86/bist.h"
  26
  27 #define SIO_GPIO_BASE 0x680
  28 #define SIO_XBUS_BASE 0x4880
  29
  30 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2)
  31 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, PC87427_SP1)
  32
  33 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0)
  34 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  35
  36 /* Beta values:         0x00090800 */
  37 /* Silver values:       0x000a0900 */
  38 #define RECVENA_CONFIG  0x000a090a
  39 #define RECVENB_CONFIG  0x000a090a
  40 #define DIMM_MAP_LOGICAL 0x0124
  41
  42 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  43 {
  44         /* nothing to do */
  45 }
  46 static inline int spd_read_byte(unsigned device, unsigned address)
  47 {
  48         return smbus_read_byte(device, address);
  49 }
  50
  51 #include "northbridge/intel/e7520/raminit.c"
  52 #include "sdram/generic_sdram.c"
  53 #include "debug.c"
  54
  55
  56 static void main(unsigned long bist)
  57 {
  58         /*
  59          *
  60          *
  61          */
  62         static const struct mem_controller mch[] = {
  63                 {
  64                         .node_id = 0,
  65                         .f0 = PCI_DEV(0, 0x00, 0),
  66                         .f1 = PCI_DEV(0, 0x00, 1),
  67                         .f2 = PCI_DEV(0, 0x00, 2),
  68                         .f3 = PCI_DEV(0, 0x00, 3),
  69                         .channel0 = { (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, 0 },
  70                         .channel1 = { (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, 0 },
  71                 }
  72         };
  73
  74         if (bist == 0) {
  75                 /* Skip this if there was a built in self test failure */
  76                 early_mtrr_init();
  77                 if (memory_initialized()) {
  78                         asm volatile ("jmp __cpu_reset");
  79                 }
  80         }
  81         /* Setup the console */
  82         pc87427_disable_dev(CONSOLE_SERIAL_DEV);
  83         pc87427_disable_dev(HIDDEN_SERIAL_DEV);
  84         pc87427_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE);
  85         /* Enable Serial 2 lines instead of GPIO */
  86         outb(0x2c, 0x2e);
  87         outb((inb(0x2f) & (~1<<1)), 0x2f);
  88         uart_init();
  89         console_init();
  90
  91         /* Halt if there was a built in self test failure */
  92         report_bist_failure(bist);
  93
  94         pc87427_enable_dev(PC87427_GPIO_DEV, SIO_GPIO_BASE);
  95
  96         pc87427_enable_dev(PC87427_XBUS_DEV, SIO_XBUS_BASE);
  97         xbus_cfg(PC87427_XBUS_DEV);
  98
  99         /* MOVE ME TO A BETTER LOCATION !!! */
 100         /* config LPC decode for flash memory access */
 101         device_t dev;
 102         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
 103         if (dev == PCI_DEV_INVALID) {
 104                 die("Missing ich5?");
 105         }
 106         pci_write_config32(dev, 0xe8, 0x00000000);
 107         pci_write_config8(dev, 0xf0, 0x00);
 108
 109 #if 0
 110         print_pci_devices();
 111 #endif
 112         enable_smbus();
 113 #if 0
 114 //      dump_spd_registers(&cpu[0]);
 115         int i;
 116         for(i = 0; i < 1; i++) {
 117                 dump_spd_registers();
 118         }
 119 #endif
 120         disable_watchdogs();
 121         power_down_reset_check();
 122 //      dump_ipmi_registers();
 123         mainboard_set_e7520_leds();
 124         sdram_initialize(ARRAY_SIZE(mch), mch);
 125         ich5_watchdog_on();
 126 #if 0
 127         dump_pci_devices();
 128 #endif
 129 #if 0
 130         dump_pci_device(PCI_DEV(0, 0x00, 0));
 131         dump_bar14(PCI_DEV(0, 0x00, 0));
 132 #endif
 133
 134 #if 0 // temporarily disabled
 135         /* Check the first 1M */
 136 //      ram_check(0x00000000, 0x000100000);
 137 //      ram_check(0x00000000, 0x000a0000);
 138         ram_check(0x00100000, 0x01000000);
 139         /* check the first 1M in the 3rd Gig */
 140         ram_check(0x30100000, 0x31000000);
 141 #if 0
 142         ram_check(0x00000000, 0x02000000);
 143 #endif
 144
 145 #endif
 146 #if 0
 147         while(1) {
 148                 hlt();
 149         }
 150 #endif
 151 }