preliminary Intel D945GCLF Atom+i945 support.
[coreboot.git] / src / mainboard / intel / d945gclf / devicetree.cb
1 ##
2 ## This file is part of the coreboot project.
3 ## 
4 ## Copyright (C) 2007-2008 coresystems GmbH
5 ##
6 ## This program is free software; you can redistribute it and/or
7 ## modify it under the terms of the GNU General Public License as
8 ## published by the Free Software Foundation; version 2 of
9 ## the License.
10 ##
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 ## GNU General Public License for more details.
15 ##
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
19 ## MA 02110-1301 USA
20 ##
21
22 chip northbridge/intel/i945
23
24         device apic_cluster 0 on
25                 chip cpu/intel/socket_441
26                         device apic 0 on end
27                 end
28         end
29
30         device pci_domain 0 on 
31                 device pci 00.0 on end # host bridge
32                 device pci 01.0 off end # i945 PCIe root port
33                 chip drivers/pci/onboard
34                         device pci 02.0 on end # vga controller
35                         # register "rom_address" = "0xfffc0000" # 256 KB image
36                         # register "rom_address" = "0xfff80000" # 512 KB image
37                         # register "rom_address" = "0xfff00000" # 1 MB image
38                 end
39                 device pci 02.1 on end # display controller
40
41                 chip southbridge/intel/i82801gx
42                         register "pirqa_routing" = "0x05"
43                         register "pirqb_routing" = "0x07"
44                         register "pirqc_routing" = "0x05"
45                         register "pirqd_routing" = "0x07"
46                         register "pirqe_routing" = "0x80"
47                         register "pirqf_routing" = "0x80"
48                         register "pirqg_routing" = "0x80"
49                         register "pirqh_routing" = "0x06"
50
51                         # GPI routing
52                         #  0 No effect (default)
53                         #  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
54                         #  2 SCI (if corresponding GPIO_EN bit is also set)
55                         register "gpi13_routing" = "1"
56                         register "gpe0_en" = "0x20000601"
57
58                         register "ide_legacy_combined" = "0x1"
59                         register "ide_enable_primary" = "0x1"
60                         register "ide_enable_secondary" = "0x0"
61                         register "sata_ahci" = "0x0"
62
63                         device pci 1b.0 on end # High Definition Audio
64                         device pci 1c.0 on end # PCIe
65                         device pci 1c.1 on end # PCIe
66                         device pci 1c.2 on end # PCIe
67                         #device pci 1c.3 off end # PCIe port 4
68                         #device pci 1c.4 off end # PCIe port 5
69                         #device pci 1c.5 off end # PCIe port 6
70                         device pci 1d.0 on end # USB UHCI
71                         device pci 1d.1 on end # USB UHCI
72                         device pci 1d.2 on end # USB UHCI
73                         device pci 1d.3 on end # USB UHCI
74                         device pci 1d.7 on end # USB2 EHCI
75                         device pci 1e.0 on end # PCI bridge
76                         #device pci 1e.2 off end # AC'97 Audio 
77                         #device pci 1e.3 off end # AC'97 Modem
78                         device pci 1f.0 on # LPC bridge
79                                 chip superio/smsc/lpc47m15x
80                                         device pnp 2e.0 off             # Floppy
81                                         end
82                                         device pnp 2e.3 off             # Parport
83                                         end
84                                         device pnp 2e.4 on
85                                                  io 0x60 = 0x3f8
86                                                 irq 0x70 = 4
87                                         end
88                                         device pnp 2e.5 on
89                                                  io 0x60 = 0x2f8
90                                                 irq 0x70 = 3
91                                                 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
92                                         end
93                                         device pnp 2e.7 on              # Keyboard+Mouse
94                                                  io 0x60 = 0x60
95                                                  io 0x62 = 0x64
96                                                 irq 0x70 = 1
97                                                 irq 0x72 = 12
98                                                 irq 0xf0 = 0x82         # HW accel A20.
99                                         end
100                                         device pnp 2e.8 on              # GAME
101                                                 # all default
102                                         end
103                                         device pnp 2e.a on              # PME
104                                         end
105                                         device pnp 2e.b on              # MPU
106                                         end
107                                 end
108                         end
109                         #device pci 1f.1 off end # IDE
110                         device pci 1f.2 on end  # SATA
111                         device pci 1f.3 on end  # SMBus
112                         #device pci 1f.4 off end # Realtek ID Codec
113                 end
114         end
115 end