2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <device/pci_def.h>
26 #include <device/pnp_def.h>
28 #include "pc80/serial.c"
29 #include "arch/i386/lib/console.c"
30 #include "ram/ramtest.c"
31 #include "cpu/x86/bist.h"
32 #include "cpu/x86/msr.h"
33 #include <cpu/amd/lxdef.h>
34 #include <cpu/amd/geode_post_code.h>
35 #include "southbridge/amd/cs5536/cs5536.h"
37 #define POST_CODE(x) outb(x, 0x80)
38 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
40 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
41 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
42 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
44 static inline int spd_read_byte(unsigned int device, unsigned int address)
46 return smbus_read_byte(device, address);
49 #define ManualConf 1 /* Do automatic strapped PLL config */
50 //#define PLLMSRhi 0x0000059C /* CPU and GLIU mult/div 500/400*/
51 //#define PLLMSRhi 0x0000049C /* CPU and GLIU mult/div 500/333*/
52 #define PLLMSRhi 0x0000039C /* CPU and GLIU mult/div 500/266*/
53 //0x0000059C 0000 0000 0000 0000 0000 |0101 1|0|01 110|0
54 /* Hold Count - how long we will sit in reset */
55 #define PLLMSRlo 0x00DE6000
60 #include "northbridge/amd/lx/raminit.h"
61 #include "northbridge/amd/lx/pll_reset.c"
62 #include "northbridge/amd/lx/raminit.c"
63 #include "sdram/generic_sdram.c"
64 #include "cpu/amd/model_lx/cpureginit.c"
65 #include "cpu/amd/model_lx/syspreinit.c"
67 static void msr_init(void)
71 /* Setup access to the cache for under 1MB. */
73 msr.lo = 0x1000A000; /* 0-A0000 write back */
74 wrmsr(CPU_RCONF_DEFAULT, msr);
76 msr.hi = 0x0; /* Write back */
78 wrmsr(CPU_RCONF_A0_BF, msr);
79 wrmsr(CPU_RCONF_C0_DF, msr);
80 wrmsr(CPU_RCONF_E0_FF, msr);
82 /* Setup access to the cache for under 640K. Note MC not setup yet. */
85 wrmsr(MSR_GLIU0 + 0x20, msr);
89 wrmsr(MSR_GLIU0 + 0x21, msr);
93 wrmsr(MSR_GLIU1 + 0x20, msr);
97 wrmsr(MSR_GLIU1 + 0x21, msr);
100 static void mb_gpio_init(void)
102 /* Early mainboard specific GPIO setup. */
105 void cache_as_ram_main(void)
109 static const struct mem_controller memctrl[] = {
110 {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
116 cs5536_early_setup();
118 /* Note: must do this AFTER the early_setup! It is counting on some
119 * early MSR setup for CS5536.
121 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
126 pll_reset(ManualConf);
130 sdram_initialize(1, memctrl);
132 /* ram_check(0, 640 * 1024); */
134 /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */