src/mainboard/ibm/e326/Config.lb

   1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
   2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
   3 include /config/nofailovercalculation.lb
   4
   5 ##
   6 ## Set all of the defaults for an x86 architecture
   7 ##
   8
   9 arch i386 end
  10
  11 ##
  12 ## Build the objects we have code for in this directory.
  13 ##
  14
  15 driver mainboard.o
  16 if CONFIG_HAVE_MP_TABLE object mptable.o end
  17 if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
  18 #object reset.o
  19
  20 if CONFIG_USE_INIT
  21
  22 makerule ./auto.o
  23         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  24         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  25 end
  26
  27 else
  28
  29 makerule ./auto.inc
  30         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  31         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  32         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  33         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  34 end
  35
  36 end
  37
  38 ##
  39 ## Build our 16 bit and 32 bit coreboot entry code
  40 ##
  41 if CONFIG_USE_FALLBACK_IMAGE
  42         mainboardinit cpu/x86/16bit/entry16.inc
  43         ldscript /cpu/x86/16bit/entry16.lds
  44 end
  45
  46 mainboardinit cpu/x86/32bit/entry32.inc
  47
  48         if CONFIG_USE_INIT
  49                 ldscript /cpu/x86/32bit/entry32.lds
  50         end
  51
  52         if CONFIG_USE_INIT
  53                 ldscript      /cpu/amd/car/cache_as_ram.lds
  54         end
  55
  56 ##
  57 ## Build our reset vector (This is where coreboot is entered)
  58 ##
  59 if CONFIG_USE_FALLBACK_IMAGE
  60         mainboardinit cpu/x86/16bit/reset16.inc
  61         ldscript /cpu/x86/16bit/reset16.lds
  62 else
  63         mainboardinit cpu/x86/32bit/reset32.inc
  64         ldscript /cpu/x86/32bit/reset32.lds
  65 end
  66
  67 ##
  68 ## Include an id string (For safe flashing)
  69 ##
  70 mainboardinit arch/i386/lib/id.inc
  71 ldscript /arch/i386/lib/id.lds
  72
  73 ##
  74 ## Setup Cache-As-Ram
  75 ##
  76 mainboardinit cpu/amd/car/cache_as_ram.inc
  77
  78 ###
  79 ### This is the early phase of coreboot startup
  80 ### Things are delicate and we test to see if we should
  81 ### failover to another image.
  82 ###
  83 if CONFIG_USE_FALLBACK_IMAGE
  84        ldscript /arch/i386/lib/failover.lds
  85 end
  86
  87 ###
  88 ### O.k. We aren't just an intermediary anymore!
  89 ###
  90
  91 ##
  92 ## Setup RAM
  93 ##
  94 if CONFIG_USE_INIT
  95 initobject auto.o
  96 else
  97 mainboardinit ./auto.inc
  98 end
  99
 100 ##
 101 ## Include the secondary Configuration files
 102 ##
 103 config chip.h
 104
 105
 106 chip northbridge/amd/amdk8/root_complex
 107         device apic_cluster 0 on
 108                 chip cpu/amd/socket_940
 109                         device apic 0 on end
 110                 end
 111         end
 112
 113         device pci_domain 0 on
 114                 chip northbridge/amd/amdk8
 115                         device pci 18.0 on end # LDT 0
 116                         device pci 18.0 on     # LDT 1
 117                                 chip southbridge/amd/amd8131
 118                                         device pci 0.0 on end
 119                                         device pci 0.1 on end
 120                                         device pci 1.0 on end
 121                                         device pci 1.1 on end
 122                                 end
 123                                 chip southbridge/amd/amd8111
 124                                         device pci 0.0 on
 125                                                 device pci 0.0 on end
 126                                                 device pci 0.1 on end
 127                                                 device pci 0.2 on end
 128                                                 device pci 1.0 off end
 129                                                 chip drivers/pci/onboard
 130                                                         device pci 5.0 on end # ATI Rage XL
 131                                                         register "rom_address" = "0xfff80000"
 132                                                 end
 133                                         end
 134                                         device pci 1.0 on
 135                                                 chip superio/nsc/pc87366
 136                                                         device  pnp 2e.0 off  # Floppy
 137                                                                  io 0x60 = 0x3f0
 138                                                                 irq 0x70 = 6
 139                                                                 drq 0x74 = 2
 140                                                         end
 141                                                         device pnp 2e.1 off  # Parallel Port
 142                                                                  io 0x60 = 0x378
 143                                                                 irq 0x70 = 7
 144                                                         end
 145                                                         device pnp 2e.2 off # Com 2
 146                                                                  io 0x60 = 0x2f8
 147                                                                 irq 0x70 = 3
 148                                                         end
 149                                                         device pnp 2e.3 on  # Com 1
 150                                                                  io 0x60 = 0x3f8
 151                                                                 irq 0x70 = 4
 152                                                         end
 153                                                         device pnp 2e.4 off end # SWC
 154                                                         device pnp 2e.5 off end # Mouse
 155                                                         device pnp 2e.6 on  # Keyboard
 156                                                                  io 0x60 = 0x60
 157                                                                  io 0x62 = 0x64
 158                                                                 irq 0x70 = 1
 159                                                         end
 160                                                         device pnp 2e.7 off end # GPIO
 161                                                         device pnp 2e.8 off end # ACB
 162                                                         device pnp 2e.9 off end # FSCM
 163                                                         device pnp 2e.a off end # WDT
 164                                                 end
 165                                         end
 166                                         device pci 1.1 on end
 167                                         device pci 1.2 on end
 168                                         device pci 1.3 on end
 169                                         device pci 1.5 off end
 170                                         device pci 1.6 off end
 171                                         register "ide0_enable" = "1"
 172                                         register "ide1_enable" = "1"
 173                                 end
 174                         end #  device pci 18.0
 175                         device pci 18.0 on end # LDT2
 176                         device pci 18.1 on end
 177                         device pci 18.2 on end
 178                         device pci 18.3 on end
 179                 end
 180         end
 181 end
 182