src/mainboard/ibm/e325/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include <stdlib.h>
  11 #include "option_table.h"
  12 #include "pc80/mc146818rtc_early.c"
  13 #include "pc80/serial.c"
  14 #include "arch/i386/lib/console.c"
  15 #include "ram/ramtest.c"
  16
  17 #include <cpu/amd/model_fxx_rev.h>
  18 #include "northbridge/amd/amdk8/incoherent_ht.c"
  19 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  20 #include "northbridge/amd/amdk8/raminit.h"
  21 #include "cpu/amd/model_fxx/apic_timer.c"
  22 #include "lib/delay.c"
  23
  24 #if CONFIG_USE_INIT == 0
  25 #include "lib/memcpy.c"
  26 #endif
  27
  28 #include "cpu/x86/lapic/boot_cpu.c"
  29 #include "northbridge/amd/amdk8/reset_test.c"
  30 #include "northbridge/amd/amdk8/debug.c"
  31 #include "superio/nsc/pc87366/pc87366_early_serial.c"
  32
  33 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  34 #include "cpu/x86/bist.h"
  35
  36 #include "northbridge/amd/amdk8/setup_resource_map.c"
  37
  38 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
  39
  40 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  41
  42 static void memreset_setup(void)
  43 {
  44         if (is_cpu_pre_c0()) {
  45                 /* Set the memreset low */
  46                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  47                 /* Ensure the BIOS has control of the memory lines */
  48                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  49         } else {
  50                 /* Ensure the CPU has controll of the memory lines */
  51                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  52         }
  53 }
  54
  55 static void memreset(int controllers, const struct mem_controller *ctrl)
  56 {
  57         if (is_cpu_pre_c0()) {
  58                 udelay(800);
  59                 /* Set memreset_high */
  60                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  61                 udelay(90);
  62         }
  63 }
  64
  65
  66 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  67 {
  68         /* nothing to do */
  69 }
  70
  71 static inline int spd_read_byte(unsigned device, unsigned address)
  72 {
  73         return smbus_read_byte(device, address);
  74 }
  75
  76 #define QRANK_DIMM_SUPPORT 1
  77
  78 #include "northbridge/amd/amdk8/raminit.c"
  79 #include "resourcemap.c"
  80 #include "northbridge/amd/amdk8/coherent_ht.c"
  81 #include "sdram/generic_sdram.c"
  82
  83 #if CONFIG_LOGICAL_CPUS==1
  84 #define SET_NB_CFG_54 1
  85 #endif
  86 #include "cpu/amd/dualcore/dualcore.c"
  87
  88 #define FIRST_CPU  1
  89 #define SECOND_CPU 1
  90 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  91
  92 #include "cpu/amd/car/copy_and_run.c"
  93
  94 #include "cpu/amd/car/post_cache_as_ram.c"
  95
  96 #include "cpu/amd/model_fxx/init_cpus.c"
  97
  98
  99 #if USE_FALLBACK_IMAGE == 1
 100
 101 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 102 #include "northbridge/amd/amdk8/early_ht.c"
 103
 104 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 105 {
 106         unsigned last_boot_normal_x = last_boot_normal();
 107
 108         /* Is this a cpu only reset? or Is this a secondary cpu? */
 109         if ((cpu_init_detectedx) || (!boot_cpu())) {
 110                 if (last_boot_normal_x) {
 111                         goto normal_image;
 112                 } else {
 113                         goto fallback_image;
 114                 }
 115         }
 116
 117         /* Nothing special needs to be done to find bus 0 */
 118         /* Allow the HT devices to be found */
 119
 120         enumerate_ht_chain();
 121
 122         amd8111_enable_rom();
 123
 124         /* Is this a deliberate reset by the bios */
 125         if (bios_reset_detected() && last_boot_normal_x) {
 126                 goto normal_image;
 127         }
 128         /* This is the primary cpu how should I boot? */
 129         else if (do_normal_boot()) {
 130                 goto normal_image;
 131         }
 132         else {
 133                 goto fallback_image;
 134         }
 135  normal_image:
 136         __asm__ volatile ("jmp __normal_image"
 137                 : /* outputs */
 138                 : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */
 139                 );
 140
 141  fallback_image:
 142         ;
 143 }
 144 #endif
 145
 146 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 147
 148 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 149 {
 150
 151 #if USE_FALLBACK_IMAGE == 1
 152         failover_process(bist, cpu_init_detectedx);
 153 #endif
 154         real_main(bist, cpu_init_detectedx);
 155
 156 }
 157
 158 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 159 {
 160         static const struct mem_controller cpu[] = {
 161                 {
 162                         .node_id = 0,
 163                         .f0 = PCI_DEV(0, 0x18, 0),
 164                         .f1 = PCI_DEV(0, 0x18, 1),
 165                         .f2 = PCI_DEV(0, 0x18, 2),
 166                         .f3 = PCI_DEV(0, 0x18, 3),
 167                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 168                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 169                 },
 170 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 171                 {
 172                         .node_id = 1,
 173                         .f0 = PCI_DEV(0, 0x19, 0),
 174                         .f1 = PCI_DEV(0, 0x19, 1),
 175                         .f2 = PCI_DEV(0, 0x19, 2),
 176                         .f3 = PCI_DEV(0, 0x19, 3),
 177                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 178                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 179                 },
 180 #endif
 181         };
 182
 183         int needs_reset;
 184
 185         if (bist == 0) {
 186                 init_cpus(cpu_init_detectedx);
 187         }
 188
 189         pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);
 190         uart_init();
 191         console_init();
 192
 193         /* Halt if there was a built in self test failure */
 194         report_bist_failure(bist);
 195
 196         setup_ibm_e325_resource_map();
 197
 198         needs_reset = setup_coherent_ht_domain();
 199
 200 #if CONFIG_LOGICAL_CPUS==1
 201         // It is said that we should start core1 after all core0 launched
 202         start_other_cores();
 203 #endif
 204         // automatically set that for you, but you might meet tight space
 205         needs_reset |= ht_setup_chains_x();
 206
 207         if (needs_reset) {
 208                 print_info("ht reset -\r\n");
 209                 soft_reset();
 210         }
 211
 212         enable_smbus();
 213
 214         memreset_setup();
 215         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 216
 217         post_cache_as_ram();
 218
 219 }