1 uses CONFIG_HAVE_MP_TABLE
3 uses CONFIG_HAVE_PIRQ_TABLE
4 uses CONFIG_USE_FALLBACK_IMAGE
5 uses CONFIG_HAVE_FALLBACK_BOOT
6 uses CONFIG_HAVE_HARD_RESET
7 uses CONFIG_IRQ_SLOT_COUNT
8 uses CONFIG_HAVE_OPTION_TABLE
10 uses CONFIG_MAX_PHYSICAL_CPUS
13 uses CONFIG_FALLBACK_SIZE
15 uses CONFIG_ROM_SECTION_SIZE
16 uses CONFIG_ROM_IMAGE_SIZE
17 uses CONFIG_ROM_SECTION_SIZE
18 uses CONFIG_ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_ROM_PAYLOAD_START
21 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
22 uses CONFIG_PRECOMPRESSED_PAYLOAD
23 uses CONFIG_PAYLOAD_SIZE
25 uses CONFIG_XIP_ROM_SIZE
26 uses CONFIG_XIP_ROM_BASE
27 uses CONFIG_STACK_SIZE
29 uses CONFIG_USE_OPTION_TABLE
30 uses CONFIG_LB_CKS_RANGE_START
31 uses CONFIG_LB_CKS_RANGE_END
32 uses CONFIG_LB_CKS_LOC
33 uses CONFIG_MAINBOARD_PART_NUMBER
34 uses CONFIG_MAINBOARD_VENDOR
36 uses COREBOOT_EXTRA_VERSION
38 uses CONFIG_TTYS0_BAUD
39 uses CONFIG_TTYS0_BASE
41 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
42 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
43 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
44 uses CONFIG_CONSOLE_SERIAL8250
45 uses CONFIG_CROSS_COMPILE
49 uses CONFIG_USE_DCACHE_RAM
50 uses CONFIG_DCACHE_RAM_BASE
51 uses CONFIG_DCACHE_RAM_SIZE
53 uses CONFIG_USE_PRINTK_IN_CAR
61 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
63 default CONFIG_ROM_SIZE=524288
66 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
68 default CONFIG_FALLBACK_SIZE=0x40000
71 ## Build code for the fallback boot
73 default CONFIG_HAVE_FALLBACK_BOOT=1
76 ## Build code to reset the motherboard from coreboot
78 default CONFIG_HAVE_HARD_RESET=1
81 ## Build code to export a programmable irq routing table
83 default CONFIG_HAVE_PIRQ_TABLE=1
84 default CONFIG_IRQ_SLOT_COUNT=9
87 ## Build code to export an x86 MP table
88 ## Useful for specifying IRQ routing values
90 default CONFIG_HAVE_MP_TABLE=1
93 ## Build code to export a CMOS option table
95 default CONFIG_HAVE_OPTION_TABLE=1
98 ## Move the default coreboot cmos range off of AMD RTC registers
100 default CONFIG_LB_CKS_RANGE_START=49
101 default CONFIG_LB_CKS_RANGE_END=122
102 default CONFIG_LB_CKS_LOC=123
105 ## Build code for SMP support
106 ## Only worry about 2 micro processors
109 default CONFIG_MAX_CPUS=1
110 default CONFIG_MAX_PHYSICAL_CPUS=1
113 ## Build code to setup a generic IOAPIC
115 default CONFIG_IOAPIC=1
118 ## enable CACHE_AS_RAM specifics
120 default CONFIG_USE_DCACHE_RAM=1
121 default CONFIG_DCACHE_RAM_BASE=0xcf000
122 default CONFIG_DCACHE_RAM_SIZE=0x1000
123 default CONFIG_USE_INIT=0
126 ## Clean up the motherboard id strings
128 default CONFIG_MAINBOARD_PART_NUMBER="E325"
129 default CONFIG_MAINBOARD_VENDOR="IBM"
130 #default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
131 #default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
134 ### coreboot layout values
137 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
138 default CONFIG_ROM_IMAGE_SIZE = 65536
141 ## Use a small 8K stack
143 default CONFIG_STACK_SIZE=0x2000
146 ## Use a small 16K heap
148 default CONFIG_HEAP_SIZE=0x8000
151 ## Only use the option table in a normal image
153 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
156 ## Coreboot C code runs at this location in RAM
158 default CONFIG_RAMBASE=0x00004000
161 ## Load the payload from the ROM
163 default CONFIG_ROM_PAYLOAD = 1
166 ### Defaults of options that you may want to override in the target config file
170 ## The default compiler
172 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
173 default CONFIG_HOSTCC="gcc"
175 default CONFIG_USE_PRINTK_IN_CAR=1
178 ## The Serial Console
181 # To Enable the Serial Console
182 default CONFIG_CONSOLE_SERIAL8250=1
184 ## Select the serial console baud rate
185 default CONFIG_TTYS0_BAUD=115200
186 #default CONFIG_TTYS0_BAUD=57600
187 #default CONFIG_TTYS0_BAUD=38400
188 #default CONFIG_TTYS0_BAUD=19200
189 #default CONFIG_TTYS0_BAUD=9600
190 #default CONFIG_TTYS0_BAUD=4800
191 #default CONFIG_TTYS0_BAUD=2400
192 #default CONFIG_TTYS0_BAUD=1200
194 # Select the serial console base port
195 default CONFIG_TTYS0_BASE=0x3f8
197 # Select the serial protocol
198 # This defaults to 8 data bits, 1 stop bit, and no parity
199 default CONFIG_TTYS0_LCS=0x3
202 ### Select the coreboot loglevel
204 ## EMERG 1 system is unusable
205 ## ALERT 2 action must be taken immediately
206 ## CRIT 3 critical conditions
207 ## ERR 4 error conditions
208 ## WARNING 5 warning conditions
209 ## NOTICE 6 normal but significant condition
210 ## INFO 7 informational
211 ## CONFIG_DEBUG 8 debug-level messages
212 ## SPEW 9 Way too many details
214 ## Request this level of debugging output
215 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
216 ## At a maximum only compile in this level of debugging
217 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
220 ## Select power on after power fail setting
221 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
228 default CONFIG_CBFS=0