3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_MAX_PHYSICAL_CPUS
17 uses ROM_SECTION_OFFSET
18 uses CONFIG_ROM_PAYLOAD
19 uses CONFIG_ROM_PAYLOAD_START
20 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
21 uses CONFIG_PRECOMPRESSED_PAYLOAD
29 uses LB_CKS_RANGE_START
32 uses MAINBOARD_PART_NUMBER
35 uses COREBOOT_EXTRA_VERSION
40 uses DEFAULT_CONSOLE_LOGLEVEL
41 uses MAXIMUM_CONSOLE_LOGLEVEL
42 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
43 uses CONFIG_CONSOLE_SERIAL8250
59 ## ROM_SIZE is the size of boot ROM that this board will use.
61 default ROM_SIZE=524288
64 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
66 default FALLBACK_SIZE=0x40000
69 ## Build code for the fallback boot
71 default HAVE_FALLBACK_BOOT=1
74 ## Build code to reset the motherboard from coreboot
76 default HAVE_HARD_RESET=1
79 ## Build code to export a programmable irq routing table
81 default HAVE_PIRQ_TABLE=1
82 default IRQ_SLOT_COUNT=9
85 ## Build code to export an x86 MP table
86 ## Useful for specifying IRQ routing values
88 default HAVE_MP_TABLE=1
91 ## Build code to export a CMOS option table
93 default HAVE_OPTION_TABLE=1
96 ## Move the default coreboot cmos range off of AMD RTC registers
98 default LB_CKS_RANGE_START=49
99 default LB_CKS_RANGE_END=122
100 default LB_CKS_LOC=123
103 ## Build code for SMP support
104 ## Only worry about 2 micro processors
107 default CONFIG_MAX_CPUS=1
108 default CONFIG_MAX_PHYSICAL_CPUS=1
111 ## Build code to setup a generic IOAPIC
113 default CONFIG_IOAPIC=1
116 ## enable CACHE_AS_RAM specifics
118 default USE_DCACHE_RAM=1
119 default DCACHE_RAM_BASE=0xcf000
120 default DCACHE_RAM_SIZE=0x1000
121 default CONFIG_USE_INIT=0
124 ## Clean up the motherboard id strings
126 default MAINBOARD_PART_NUMBER="E325"
127 default MAINBOARD_VENDOR="IBM"
128 #default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
129 #default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
132 ### coreboot layout values
135 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
136 default ROM_IMAGE_SIZE = 65536
139 ## Use a small 8K stack
141 default STACK_SIZE=0x2000
144 ## Use a small 16K heap
146 default HEAP_SIZE=0x8000
149 ## Only use the option table in a normal image
151 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
154 ## Coreboot C code runs at this location in RAM
156 default _RAMBASE=0x00004000
159 ## Load the payload from the ROM
161 default CONFIG_ROM_PAYLOAD = 1
164 ### Defaults of options that you may want to override in the target config file
168 ## The default compiler
170 default CC="$(CROSS_COMPILE)gcc -m32"
174 ## The Serial Console
177 # To Enable the Serial Console
178 default CONFIG_CONSOLE_SERIAL8250=1
180 ## Select the serial console baud rate
181 default TTYS0_BAUD=115200
182 #default TTYS0_BAUD=57600
183 #default TTYS0_BAUD=38400
184 #default TTYS0_BAUD=19200
185 #default TTYS0_BAUD=9600
186 #default TTYS0_BAUD=4800
187 #default TTYS0_BAUD=2400
188 #default TTYS0_BAUD=1200
190 # Select the serial console base port
191 default TTYS0_BASE=0x3f8
193 # Select the serial protocol
194 # This defaults to 8 data bits, 1 stop bit, and no parity
195 default TTYS0_LCS=0x3
198 ### Select the coreboot loglevel
200 ## EMERG 1 system is unusable
201 ## ALERT 2 action must be taken immediately
202 ## CRIT 3 critical conditions
203 ## ERR 4 error conditions
204 ## WARNING 5 warning conditions
205 ## NOTICE 6 normal but significant condition
206 ## INFO 7 informational
207 ## DEBUG 8 debug-level messages
208 ## SPEW 9 Way too many details
210 ## Request this level of debugging output
211 default DEFAULT_CONSOLE_LOGLEVEL=8
212 ## At a maximum only compile in this level of debugging
213 default MAXIMUM_CONSOLE_LOGLEVEL=8
216 ## Select power on after power fail setting
217 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"