src/mainboard/ibm/e325/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (coreboot plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The coreboot bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of coreboot will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up coreboot,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 ##
  36 ## Set all of the defaults for an x86 architecture
  37 ##
  38
  39 arch i386 end
  40
  41 ##
  42 ## Build the objects we have code for in this directory.
  43 ##
  44
  45 driver mainboard.o
  46 if HAVE_MP_TABLE object mptable.o end
  47 if HAVE_PIRQ_TABLE object irq_tables.o end
  48 #object reset.o
  49
  50 if USE_DCACHE_RAM
  51
  52 if CONFIG_USE_INIT
  53
  54 makerule ./auto.o
  55         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  56         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
  57 end
  58
  59 else
  60
  61 makerule ./auto.inc
  62         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  63         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
  64         action "perl -e 's/.rodata/.rom.data/g' -pi $@"
  65         action "perl -e 's/.text/.section .rom.text/g' -pi $@"
  66 end
  67
  68 end
  69 else
  70 ##
  71 ## Romcc output
  72 ##
  73 makerule ./failover.E
  74         depends "$(MAINBOARD)/failover.c ./romcc"
  75         action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  76 end
  77
  78 makerule ./failover.inc
  79         depends "$(MAINBOARD)/failover.c ./romcc"
  80         action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  81 end
  82
  83 makerule ./auto.E
  84         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  85         action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  86 end
  87 makerule ./auto.inc
  88         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  89         action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  90 end
  91
  92 end
  93
  94 ##
  95 ## Build our 16 bit and 32 bit coreboot entry code
  96 ##
  97 if USE_FALLBACK_IMAGE
  98         mainboardinit cpu/x86/16bit/entry16.inc
  99         ldscript /cpu/x86/16bit/entry16.lds
 100 end
 101
 102 mainboardinit cpu/x86/32bit/entry32.inc
 103
 104 if USE_DCACHE_RAM
 105         if CONFIG_USE_INIT
 106                 ldscript /cpu/x86/32bit/entry32.lds
 107         end
 108
 109         if CONFIG_USE_INIT
 110                 ldscript      /cpu/amd/car/cache_as_ram.lds
 111         end
 112 end
 113
 114 ##
 115 ## Build our reset vector (This is where coreboot is entered)
 116 ##
 117 if USE_FALLBACK_IMAGE
 118         mainboardinit cpu/x86/16bit/reset16.inc
 119         ldscript /cpu/x86/16bit/reset16.lds
 120 else
 121         mainboardinit cpu/x86/32bit/reset32.inc
 122         ldscript /cpu/x86/32bit/reset32.lds
 123 end
 124
 125 if USE_DCACHE_RAM
 126 else
 127 ### Should this be in the northbridge code?
 128 mainboardinit arch/i386/lib/cpu_reset.inc
 129 end
 130
 131 ##
 132 ## Include an id string (For safe flashing)
 133 ##
 134 mainboardinit arch/i386/lib/id.inc
 135 ldscript /arch/i386/lib/id.lds
 136
 137 if USE_DCACHE_RAM
 138 ##
 139 ## Setup Cache-As-Ram
 140 ##
 141 mainboardinit cpu/amd/car/cache_as_ram.inc
 142 end
 143
 144 ###
 145 ### This is the early phase of coreboot startup
 146 ### Things are delicate and we test to see if we should
 147 ### failover to another image.
 148 ###
 149 if USE_FALLBACK_IMAGE
 150 if USE_DCACHE_RAM
 151        ldscript /arch/i386/lib/failover.lds
 152 else
 153        ldscript /arch/i386/lib/failover.lds
 154         mainboardinit ./failover.inc
 155 end
 156 end
 157
 158 ###
 159 ### O.k. We aren't just an intermediary anymore!
 160 ###
 161
 162 ##
 163 ## Setup RAM
 164 ##
 165 if USE_DCACHE_RAM
 166
 167 if CONFIG_USE_INIT
 168 initobject auto.o
 169 else
 170 mainboardinit ./auto.inc
 171 end
 172
 173 else
 174
 175 ##
 176 ## Setup RAM
 177 ##
 178 mainboardinit cpu/x86/fpu/enable_fpu.inc
 179 mainboardinit cpu/x86/mmx/enable_mmx.inc
 180 mainboardinit cpu/x86/sse/enable_sse.inc
 181 mainboardinit ./auto.inc
 182 mainboardinit cpu/x86/sse/disable_sse.inc
 183 mainboardinit cpu/x86/mmx/disable_mmx.inc
 184 end
 185
 186 ##
 187 ## Include the secondary Configuration files
 188 ##
 189 config chip.h
 190
 191
 192 chip northbridge/amd/amdk8/root_complex
 193         device pci_domain 0 on
 194                 chip northbridge/amd/amdk8
 195                         device pci 18.0 on end # LDT 0
 196                         device pci 18.0 on     # LDT 1
 197                                 chip southbridge/amd/amd8131
 198                                         device pci 0.0 on end
 199                                         device pci 0.1 on end
 200                                         device pci 1.0 on end
 201                                         device pci 1.1 on end
 202                                 end
 203                                 chip southbridge/amd/amd8111
 204                                         device pci 0.0 on
 205                                                 device pci 0.0 on end
 206                                                 device pci 0.1 on end
 207                                                 device pci 0.2 on end
 208                                                 device pci 1.0 off end
 209                                         end
 210                                         device pci 1.0 on
 211                                                 chip superio/nsc/pc87366
 212                                                         device  pnp 2e.0 off  # Floppy
 213                                                                  io 0x60 = 0x3f0
 214                                                                 irq 0x70 = 6
 215                                                                 drq 0x74 = 2
 216                                                         end
 217                                                         device pnp 2e.1 off  # Parallel Port
 218                                                                  io 0x60 = 0x378
 219                                                                 irq 0x70 = 7
 220                                                         end
 221                                                         device pnp 2e.2 off # Com 2
 222                                                                  io 0x60 = 0x2f8
 223                                                                 irq 0x70 = 3
 224                                                         end
 225                                                         device pnp 2e.3 on  # Com 1
 226                                                                  io 0x60 = 0x3f8
 227                                                                 irq 0x70 = 4
 228                                                         end
 229                                                         device pnp 2e.4 off end # SWC
 230                                                         device pnp 2e.5 off end # Mouse
 231                                                         device pnp 2e.6 on  # Keyboard
 232                                                                  io 0x60 = 0x60
 233                                                                  io 0x62 = 0x64
 234                                                                 irq 0x70 = 1
 235                                                         end
 236                                                         device pnp 2e.7 off end # GPIO
 237                                                         device pnp 2e.8 off end # ACB
 238                                                         device pnp 2e.9 off end # FSCM
 239                                                         device pnp 2e.a off end # WDT
 240                                                 end
 241                                         end
 242                                         device pci 1.1 on end
 243                                         device pci 1.2 on end
 244                                         device pci 1.3 on end
 245                                         device pci 1.5 off end
 246                                         device pci 1.6 off end
 247                                 end
 248                         end #  device pci 18.0
 249                         device pci 18.0 on end # LDT2
 250                         device pci 18.1 on end
 251                         device pci 18.2 on end
 252                         device pci 18.3 on end
 253                 end
 254                 chip northbridge/amd/amdk8
 255                         device pci 19.0 on end
 256                         device pci 19.0 on end
 257                         device pci 19.0 on end
 258                         device pci 19.1 on end
 259                         device pci 19.2 on end
 260                         device pci 19.3 on end
 261                 end
 262         end
 263         device apic_cluster 0 on
 264                 chip cpu/amd/socket_940
 265                         device apic 0 on end
 266                 end
 267                 chip cpu/amd/socket_940
 268                         device apic 1 on end
 269                 end
 270         end
 271 end
 272