2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 ## Compute the location and size of where this firmware image
24 ## (coreboot plus bootloader) will live in the boot rom chip.
27 default ROM_SECTION_SIZE = FAILOVER_SIZE
28 default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
31 default ROM_SECTION_SIZE = FALLBACK_SIZE
32 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
34 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
35 default ROM_SECTION_OFFSET = 0
40 ## Compute the start location and size size of
41 ## The coreboot bootloader.
43 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
44 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
47 ## Compute where this copy of coreboot will start in the boot rom
49 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
52 ## Compute a range of ROM that can cached to speed up coreboot,
55 ## XIP_ROM_SIZE must be a power of 2.
56 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
58 default XIP_ROM_SIZE=65536
61 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
64 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
66 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
73 ## Build the objects we have code for in this directory.
77 #needed by irq_tables and mptable and acpi_tables
80 if HAVE_MP_TABLE object mptable.o end
81 if HAVE_PIRQ_TABLE object irq_tables.o end
86 makerule ./cache_as_ram_auto.o
87 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
88 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
91 makerule ./cache_as_ram_auto.inc
92 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
93 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
94 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
95 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
101 if USE_FAILOVER_IMAGE
103 if CONFIG_AP_CODE_IN_CAR
104 makerule ./apc_auto.o
105 depends "$(MAINBOARD)/apc_auto.c option_table.h"
106 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
108 ldscript /arch/i386/init/ldscript_apc.lb
114 ## Build our 16 bit and 32 bit coreboot entry code
116 if HAVE_FAILOVER_BOOT
117 if USE_FAILOVER_IMAGE
118 mainboardinit cpu/x86/16bit/entry16.inc
119 ldscript /cpu/x86/16bit/entry16.lds
122 if USE_FALLBACK_IMAGE
123 mainboardinit cpu/x86/16bit/entry16.inc
124 ldscript /cpu/x86/16bit/entry16.lds
128 mainboardinit cpu/x86/32bit/entry32.inc
132 ldscript /cpu/x86/32bit/entry32.lds
136 ldscript /cpu/amd/car/cache_as_ram.lds
142 ## Build our reset vector (This is where coreboot is entered)
144 if HAVE_FAILOVER_BOOT
145 if USE_FAILOVER_IMAGE
146 mainboardinit cpu/x86/16bit/reset16.inc
147 ldscript /cpu/x86/16bit/reset16.lds
149 mainboardinit cpu/x86/32bit/reset32.inc
150 ldscript /cpu/x86/32bit/reset32.lds
153 if USE_FALLBACK_IMAGE
154 mainboardinit cpu/x86/16bit/reset16.inc
155 ldscript /cpu/x86/16bit/reset16.lds
157 mainboardinit cpu/x86/32bit/reset32.inc
158 ldscript /cpu/x86/32bit/reset32.lds
163 ## Include an id string (For safe flashing)
165 mainboardinit southbridge/nvidia/mcp55/id.inc
166 ldscript /southbridge/nvidia/mcp55/id.lds
169 ## ROMSTRAP table for MCP55
171 if HAVE_FAILOVER_BOOT
172 if USE_FAILOVER_IMAGE
173 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
174 ldscript /southbridge/nvidia/mcp55/romstrap.lds
177 if USE_FALLBACK_IMAGE
178 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
179 ldscript /southbridge/nvidia/mcp55/romstrap.lds
185 ## Setup Cache-As-Ram
187 mainboardinit cpu/amd/car/cache_as_ram.inc
191 ### This is the early phase of coreboot startup
192 ### Things are delicate and we test to see if we should
193 ### failover to another image.
195 if HAVE_FAILOVER_BOOT
196 if USE_FAILOVER_IMAGE
198 ldscript /arch/i386/lib/failover_failover.lds
202 if USE_FALLBACK_IMAGE
204 ldscript /arch/i386/lib/failover.lds
219 initobject cache_as_ram_auto.o
221 mainboardinit ./cache_as_ram_auto.inc
226 ## Include the secondary Configuration files
230 chip northbridge/amd/amdk8/root_complex
231 device apic_cluster 0 on
232 chip cpu/amd/socket_AM2
236 device pci_domain 0 on
237 chip northbridge/amd/amdk8 #mc0
239 # devices on link 0, link 0 == LDT 0
240 chip southbridge/nvidia/mcp55
241 device pci 0.0 on end # HT
242 device pci 1.0 on # LPC
243 chip superio/ite/it8716f
246 # Watchdog from CLKIN, CLKIN = 24 MHz
248 # Serial Flash (SPI only)
254 device pnp 2e.1 on # Com1
258 device pnp 2e.2 off # Com2
262 device pnp 2e.3 off # Parallel Port
266 device pnp 2e.4 on # EC
271 device pnp 2e.5 on # Keyboard
276 device pnp 2e.6 on # Mouse
279 device pnp 2e.7 on # GPIO, SPI flash
282 # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
288 # pin 6,3,128,127,126 is GP63,64,65,66,67
290 # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
294 # Serial Flash I/O (SPI only)
296 # watch dog force timeout (parallel flash only)
300 # GPIO pin set 1 disable internal pullup
302 # GPIO pin set 5 enable internal pullup
304 # SIO pin set 1 alternate function
306 # SIO pin set 2 mixed function
308 # SIO pin set 3 mixed function
310 # SIO pin set 4 alternate function
312 # SIO pin set 1 input mode
314 # SIO pin set 2 input mode
316 # SIO pin set 4 input mode
318 # Generate SMI# on EC IRQ
322 # HWMON alert beep pin location
325 device pnp 2e.8 off # MIDI
329 device pnp 2e.9 off # GAME
332 device pnp 2e.a off end # CIR
335 device pci 1.1 on # SM 0
336 chip drivers/generic/generic #dimm 0-0-0
339 chip drivers/generic/generic #dimm 0-0-1
342 chip drivers/generic/generic #dimm 0-1-0
345 chip drivers/generic/generic #dimm 0-1-1
348 chip drivers/generic/generic #dimm 1-0-0
351 chip drivers/generic/generic #dimm 1-0-1
354 chip drivers/generic/generic #dimm 1-1-0
357 chip drivers/generic/generic #dimm 1-1-1
361 #WTF?!? We already have device pci 1.1 in the section above
362 device pci 1.1 on # SM 1
363 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
364 # chip drivers/generic/generic #PCIXA Slot1
365 # device i2c 50 on end
367 # chip drivers/generic/generic #PCIXB Slot1
368 # device i2c 51 on end
370 # chip drivers/generic/generic #PCIXB Slot2
371 # device i2c 52 on end
373 # chip drivers/generic/generic #PCI Slot1
374 # device i2c 53 on end
376 # chip drivers/generic/generic #Master MCP55 PCI-E
377 # device i2c 54 on end
379 # chip drivers/generic/generic #Slave MCP55 PCI-E
380 # device i2c 55 on end
382 chip drivers/generic/generic #MAC EEPROM
387 device pci 2.0 on end # USB 1.1
388 device pci 2.1 on end # USB 2
389 device pci 4.0 on end # IDE
390 device pci 5.0 on end # SATA 0
391 device pci 5.1 on end # SATA 1
392 device pci 5.2 on end # SATA 2
393 device pci 6.0 on end # PCI
394 device pci 6.1 on end # AZA
395 device pci 8.0 on end # NIC
396 device pci 9.0 off end # NIC
397 device pci a.0 on end # PCI E 5
398 device pci b.0 on end # PCI E 4
399 device pci c.0 on end # PCI E 3
400 device pci d.0 on end # PCI E 2
401 device pci e.0 on end # PCI E 1
402 device pci f.0 on end # PCI E 0
403 register "ide0_enable" = "1"
404 register "sata0_enable" = "1"
405 register "sata1_enable" = "1"
406 register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
407 register "mac_eeprom_addr" = "0x51"
409 end # device pci 18.0
410 device pci 18.0 on end # Link 1
411 device pci 18.0 on end
412 device pci 18.1 on end
413 device pci 18.2 on end
414 device pci 18.3 on end
419 # chip drivers/generic/debug
420 # device pnp 0.0 off end # chip name
421 # device pnp 0.1 on end # pci_regs_all
422 # device pnp 0.2 on end # mem
423 # device pnp 0.3 off end # cpuid
424 # device pnp 0.4 on end # smbus_regs_all
425 # device pnp 0.5 off end # dual core msr
426 # device pnp 0.6 off end # cache size
427 # device pnp 0.7 off end # tsc
428 # device pnp 0.8 off end # io
429 # device pnp 0.9 off end # io