2 #include <device/pci_def.h>
4 #include <device/pnp_def.h>
5 #include <arch/romcc_io.h>
7 #include "pc80/serial.c"
8 #include "console/console.c"
9 #include "lib/ramtest.c"
10 #include "cpu/x86/bist.h"
11 #include "cpu/x86/msr.h"
12 #include <cpu/amd/lxdef.h>
13 #include <cpu/amd/geode_post_code.h>
14 #include "southbridge/amd/cs5536/cs5536.h"
16 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
18 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
19 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
20 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
22 static inline int spd_read_byte(unsigned device, unsigned address)
24 return smbus_read_byte(device, address);
27 #define ManualConf 0 /* Do automatic strapped PLL config */
28 #define PLLMSRhi 0x00001490 /* manual settings for the PLL */
29 #define PLLMSRlo 0x02000030
32 #include "northbridge/amd/lx/raminit.h"
33 #include "northbridge/amd/lx/pll_reset.c"
34 #include "northbridge/amd/lx/raminit.c"
35 #include "lib/generic_sdram.c"
36 #include "cpu/amd/model_lx/cpureginit.c"
37 #include "cpu/amd/model_lx/syspreinit.c"
39 static void msr_init(void)
42 /* Setup access to the MC for under 1MB. Note MC not setup yet. */
45 wrmsr(CPU_RCONF_DEFAULT, msr);
49 wrmsr(MSR_GLIU0 + 0x20, msr);
53 wrmsr(MSR_GLIU1 + 0x20, msr);
56 static void mb_gpio_init(void)
58 /* Early mainboard specific GPIO setup */
61 void cache_as_ram_main(void)
65 static const struct mem_controller memctrl [] = {
66 {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
74 /* NOTE: must do this AFTER the early_setup!
75 * it is counting on some early MSR setup
78 cs5536_disable_internal_uart();
79 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
84 pll_reset(ManualConf);
88 sdram_initialize(1, memctrl);
90 /* Check all of memory */
91 ram_check(0x00000000, 640*1024);
93 /* Switch from Cache as RAM to real RAM */
94 /* There are two ways we could think about this.
95 1. If we are using the romstage.inc ROMCC way, the stack is going to be re-setup in the code following this code.
96 Just wbinvd the stack to clear the cache tags. We don't care where the stack used to be.
97 2. This file is built as a normal .c -> .o and linked in etc. The stack might be used to return etc.
98 That means we care about what is in the stack. If we are smart we set the CAR stack to the same location
99 as the rest of coreboot. If that is the case we can just do a wbinvd. The stack will be written into real
100 RAM that is now setup and we continue like nothing happened. If the stack is located somewhere other than
101 where LB would like it, you need to write some code to do a copy from cache to RAM
103 We use method 1 on Norwich.
106 print_err("POST 02\n");
108 print_err("Past wbinvd\n");
109 /* we are finding the return does not work on this board. Explicitly call the label that is
110 * after the call to us. This is gross, but sometimes at this level it is the only way out
112 void done_cache_as_ram_main(void);
113 done_cache_as_ram_main();