src/mainboard/digitallogic/adl855pc/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #if 0
   7 #include <arch/smp/lapic.h>
   8 #endif
   9 #include <arch/hlt.h>
  10 //#include "option_table.h"
  11 #include <stdlib.h>
  12 #include "pc80/mc146818rtc_early.c"
  13 #include "pc80/serial.c"
  14 #include "console/console.c"
  15 #include "lib/ramtest.c"
  16 #include "southbridge/intel/i82801dx/i82801dx.h"
  17 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
  18 #include "northbridge/intel/i855/raminit.h"
  19
  20 #if 0
  21 #include "cpu/p6/apic_timer.c"
  22 #include "lib/delay.c"
  23 #endif
  24
  25 #include "cpu/x86/lapic/boot_cpu.c"
  26 #include "northbridge/intel/i855/debug.c"
  27 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  28 #include "cpu/x86/mtrr/earlymtrr.c"
  29 #include "cpu/x86/bist.h"
  30
  31 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  32
  33 static void hard_reset(void)
  34 {
  35         outb(0x0e, 0x0cf9);
  36 }
  37
  38 static void memreset_setup(void)
  39 {
  40 }
  41
  42 static void memreset(int controllers, const struct mem_controller *ctrl)
  43 {
  44 }
  45
  46 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  47 {
  48         /* nothing to do */
  49 }
  50
  51 static inline int spd_read_byte(unsigned device, unsigned address)
  52 {
  53         return smbus_read_byte(device, address);
  54 }
  55
  56 #include "northbridge/intel/i855/raminit.c"
  57 #include "northbridge/intel/i855/reset_test.c"
  58 #include "lib/generic_sdram.c"
  59
  60 static void main(unsigned long bist)
  61 {
  62         static const struct mem_controller memctrl[] = {
  63                 {
  64                         .d0 = PCI_DEV(0, 0, 1),
  65                         .channel0 = { (0xa<<3)|0, 0 },
  66                 },
  67         };
  68
  69         if (bist == 0) {
  70                 early_mtrr_init();
  71 #if 0
  72                 enable_lapic();
  73                 init_timer();
  74 #endif
  75         }
  76
  77         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  78         uart_init();
  79         console_init();
  80
  81         /* Halt if there was a built in self test failure */
  82         report_bist_failure(bist);
  83
  84
  85 #if 0
  86         print_pci_devices();
  87 #endif
  88
  89         if(!bios_reset_detected()) {
  90                 enable_smbus();
  91 #if 0
  92         dump_spd_registers(&memctrl[0]);
  93         //              dump_smbus_registers();
  94 #endif
  95
  96                 memreset_setup();
  97
  98                 sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
  99
 100         }
 101 #if 0
 102         else {
 103                         /* clear memory 1meg */
 104         __asm__ volatile(
 105                 "1: \n\t"
 106                 "movl %0, %%fs:(%1)\n\t"
 107                 "addl $4,%1\n\t"
 108                 "subl $4,%2\n\t"
 109                 "jnz 1b\n\t"
 110                 :
 111                 : "a" (0), "D" (0), "c" (1024*1024)
 112                 );
 113
 114         }
 115 #endif
 116
 117 #if 0
 118         dump_pci_devices();
 119 #endif
 120 #if 0
 121         dump_pci_device(PCI_DEV(0, 0, 0));
 122 #endif
 123
 124 /*
 125 #if  0
 126         ram_check(0x00000000, msr.lo+(msr.hi<<32));
 127 #else
 128 #if 0
 129         // Check 16MB of memory @ 0
 130         ram_check(0x00000000, 0x01000000);
 131 #else
 132         // Check 16MB of memory @ 2GB
 133         ram_check(0x80000000, 0x81000000);
 134 #endif
 135 #endif
 136 */
 137 }
 138