src/mainboard/broadcom/blast/romstage.c

   1 #define QRANK_DIMM_SUPPORT 1
   2
   3 #if CONFIG_LOGICAL_CPUS==1
   4 #define SET_NB_CFG_54 1
   5 #endif
   6
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <device/pci_def.h>
  10 #include <arch/io.h>
  11 #include <device/pnp_def.h>
  12 #include <arch/romcc_io.h>
  13 #include <cpu/x86/lapic.h>
  14 #include "option_table.h"
  15 #include "pc80/mc146818rtc_early.c"
  16 #include "pc80/serial.c"
  17 #include "console/console.c"
  18 #include "lib/ramtest.c"
  19
  20 #if 0
  21 static void post_code(uint8_t value) {
  22 #if 0
  23         int i;
  24         for(i=0;i<0x80000;i++) {
  25                 outb(value, 0x80);
  26         }
  27 #endif
  28 }
  29 #endif
  30
  31 #include <cpu/amd/model_fxx_rev.h>
  32 #include "northbridge/amd/amdk8/incoherent_ht.c"
  33 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
  34 #include "northbridge/amd/amdk8/raminit.h"
  35 #include "cpu/amd/model_fxx/apic_timer.c"
  36 #include "lib/delay.c"
  37
  38 #include "cpu/x86/lapic/boot_cpu.c"
  39 #include "northbridge/amd/amdk8/reset_test.c"
  40 #include "northbridge/amd/amdk8/debug.c"
  41 #include "superio/nsc/pc87417/pc87417_early_serial.c"
  42
  43 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  44 #include "cpu/x86/bist.h"
  45
  46 #include "northbridge/amd/amdk8/setup_resource_map.c"
  47
  48 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
  49 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
  50
  51 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
  52
  53 static void memreset_setup(void)
  54 {
  55 }
  56
  57 static void memreset(int controllers, const struct mem_controller *ctrl)
  58 {
  59 }
  60
  61 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  62 {
  63 #define SMBUS_HUB 0x71
  64         int ret,i;
  65         unsigned device=(ctrl->channel0[0])>>8;
  66         smbus_send_byte(SMBUS_HUB, device);
  67 }
  68 #if 0
  69 static inline void change_i2c_mux(unsigned device)
  70 {
  71 #define SMBUS_HUB 0x71
  72         int ret;
  73         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  74         ret = smbus_send_byte(SMBUS_HUB, device);
  75         print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
  76 }
  77 #endif
  78
  79 static inline int spd_read_byte(unsigned device, unsigned address)
  80 {
  81         return smbus_read_byte(device, address);
  82 }
  83
  84 #include "northbridge/amd/amdk8/raminit.c"
  85 #include "northbridge/amd/amdk8/coherent_ht.c"
  86 #include "lib/generic_sdram.c"
  87
  88  /* tyan does not want the default */
  89 #include "resourcemap.c"
  90
  91 #include "cpu/amd/dualcore/dualcore.c"
  92
  93 #define RC0 (6<<8)
  94 #define RC1 (7<<8)
  95
  96 #define DIMM0 0x50
  97 #define DIMM1 0x51
  98 #define DIMM2 0x52
  99 #define DIMM3 0x53
 100
 101 #include "cpu/amd/car/copy_and_run.c"
 102 #include "cpu/amd/car/post_cache_as_ram.c"
 103
 104 #include "cpu/amd/model_fxx/init_cpus.c"
 105
 106 #include "northbridge/amd/amdk8/early_ht.c"
 107
 108 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 109 {
 110         static const uint16_t spd_addr[] = {
 111                 RC0|DIMM0, RC0|DIMM2, 0, 0,
 112                 RC0|DIMM1, RC0|DIMM3, 0, 0,
 113 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 114                 RC1|DIMM0, RC1|DIMM2, 0, 0,
 115                 RC1|DIMM1, RC1|DIMM3, 0, 0,
 116 #endif
 117         };
 118
 119         int needs_reset;
 120         unsigned bsp_apicid = 0;
 121
 122         struct mem_controller ctrl[8];
 123         unsigned nodes;
 124
 125         if (!cpu_init_detectedx && boot_cpu()) {
 126                 /* Nothing special needs to be done to find bus 0 */
 127                 /* Allow the HT devices to be found */
 128
 129                 enumerate_ht_chain();
 130
 131                 bcm5785_enable_rom();
 132
 133                 bcm5785_enable_lpc();
 134
 135                 //enable RTC
 136                 pc87417_enable_dev(RTC_DEV);
 137         }
 138
 139         if (bist == 0) {
 140                 bsp_apicid = init_cpus(cpu_init_detectedx);
 141         }
 142 //      post_code(0x32);
 143
 144         pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 145 //      post_code(0x33);
 146
 147         uart_init();
 148 //      post_code(0x34);
 149
 150         console_init();
 151
 152         /* Halt if there was a built in self test failure */
 153         report_bist_failure(bist);
 154
 155         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 156
 157         setup_blast_resource_map();
 158
 159 #if 0
 160         dump_pci_device(PCI_DEV(0, 0x18, 0));
 161         dump_pci_device(PCI_DEV(0, 0x19, 0));
 162 #endif
 163
 164         needs_reset = setup_coherent_ht_domain();
 165
 166 #if CONFIG_LOGICAL_CPUS==1
 167         // It is said that we should start core1 after all core0 launched
 168         wait_all_core0_started();
 169         start_other_cores();
 170 #endif
 171         wait_all_aps_started(bsp_apicid);
 172
 173         needs_reset |= ht_setup_chains_x();
 174
 175         bcm5785_early_setup();
 176
 177         if (needs_reset) {
 178                 print_info("ht reset -\n");
 179                 soft_reset();
 180         }
 181
 182         allow_all_aps_stop(bsp_apicid);
 183
 184         nodes = get_nodes();
 185         //It's the time to set ctrl now;
 186         fill_mem_ctrl(nodes, ctrl, spd_addr);
 187
 188         enable_smbus();
 189
 190 #if 0
 191         int i;
 192         for(i=4;i<8;i++) {
 193                 change_i2c_mux(i);
 194                 dump_smbus_registers();
 195         }
 196 #endif
 197
 198         memreset_setup();
 199
 200 //      init_timer();
 201
 202         sdram_initialize(nodes, ctrl);
 203
 204 #if 0
 205         print_pci_devices();
 206 #endif
 207
 208 #if 0
 209         dump_pci_devices();
 210 #endif
 211
 212         post_cache_as_ram();
 213
 214 }
 215