src/mainboard/broadcom/blast/romstage.c

   1 #define QRANK_DIMM_SUPPORT 1
   2
   3 #if CONFIG_LOGICAL_CPUS==1
   4 #define SET_NB_CFG_54 1
   5 #endif
   6
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <device/pci_def.h>
  10 #include <arch/io.h>
  11 #include <device/pnp_def.h>
  12 #include <arch/romcc_io.h>
  13 #include <cpu/x86/lapic.h>
  14 #include "option_table.h"
  15 #include "pc80/mc146818rtc_early.c"
  16 #include "pc80/serial.c"
  17 #include "console/console.c"
  18 #include "lib/ramtest.c"
  19
  20 #include <cpu/amd/model_fxx_rev.h>
  21 #include "northbridge/amd/amdk8/incoherent_ht.c"
  22 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
  23 #include "northbridge/amd/amdk8/raminit.h"
  24 #include "cpu/amd/model_fxx/apic_timer.c"
  25 #include "lib/delay.c"
  26
  27 #include "cpu/x86/lapic/boot_cpu.c"
  28 #include "northbridge/amd/amdk8/reset_test.c"
  29 #include "northbridge/amd/amdk8/debug.c"
  30 #include "superio/nsc/pc87417/pc87417_early_serial.c"
  31
  32 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  33 #include "cpu/x86/bist.h"
  34
  35 #include "northbridge/amd/amdk8/setup_resource_map.c"
  36
  37 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
  38 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
  39
  40 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
  41
  42 static void memreset_setup(void)
  43 {
  44 }
  45
  46 static void memreset(int controllers, const struct mem_controller *ctrl)
  47 {
  48 }
  49
  50 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  51 {
  52 #define SMBUS_HUB 0x71
  53         int ret,i;
  54         unsigned device=(ctrl->channel0[0])>>8;
  55         smbus_send_byte(SMBUS_HUB, device);
  56 }
  57 #if 0
  58 static inline void change_i2c_mux(unsigned device)
  59 {
  60 #define SMBUS_HUB 0x71
  61         int ret;
  62         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  63         ret = smbus_send_byte(SMBUS_HUB, device);
  64         print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
  65 }
  66 #endif
  67
  68 static inline int spd_read_byte(unsigned device, unsigned address)
  69 {
  70         return smbus_read_byte(device, address);
  71 }
  72
  73 #include "northbridge/amd/amdk8/raminit.c"
  74 #include "northbridge/amd/amdk8/coherent_ht.c"
  75 #include "lib/generic_sdram.c"
  76
  77  /* tyan does not want the default */
  78 #include "resourcemap.c"
  79
  80 #include "cpu/amd/dualcore/dualcore.c"
  81
  82 #define RC0 (6<<8)
  83 #define RC1 (7<<8)
  84
  85 #define DIMM0 0x50
  86 #define DIMM1 0x51
  87 #define DIMM2 0x52
  88 #define DIMM3 0x53
  89
  90 #include "cpu/amd/car/copy_and_run.c"
  91 #include "cpu/amd/car/post_cache_as_ram.c"
  92
  93 #include "cpu/amd/model_fxx/init_cpus.c"
  94
  95 #include "northbridge/amd/amdk8/early_ht.c"
  96
  97 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  98 {
  99         static const uint16_t spd_addr[] = {
 100                 RC0|DIMM0, RC0|DIMM2, 0, 0,
 101                 RC0|DIMM1, RC0|DIMM3, 0, 0,
 102 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 103                 RC1|DIMM0, RC1|DIMM2, 0, 0,
 104                 RC1|DIMM1, RC1|DIMM3, 0, 0,
 105 #endif
 106         };
 107
 108         int needs_reset;
 109         unsigned bsp_apicid = 0;
 110
 111         struct mem_controller ctrl[8];
 112         unsigned nodes;
 113
 114         if (!cpu_init_detectedx && boot_cpu()) {
 115                 /* Nothing special needs to be done to find bus 0 */
 116                 /* Allow the HT devices to be found */
 117
 118                 enumerate_ht_chain();
 119
 120                 bcm5785_enable_rom();
 121
 122                 bcm5785_enable_lpc();
 123
 124                 //enable RTC
 125                 pc87417_enable_dev(RTC_DEV);
 126         }
 127
 128         if (bist == 0) {
 129                 bsp_apicid = init_cpus(cpu_init_detectedx);
 130         }
 131 //      post_code(0x32);
 132
 133         pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 134 //      post_code(0x33);
 135
 136         uart_init();
 137 //      post_code(0x34);
 138
 139         console_init();
 140
 141         /* Halt if there was a built in self test failure */
 142         report_bist_failure(bist);
 143
 144         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 145
 146         setup_blast_resource_map();
 147
 148 #if 0
 149         dump_pci_device(PCI_DEV(0, 0x18, 0));
 150         dump_pci_device(PCI_DEV(0, 0x19, 0));
 151 #endif
 152
 153         needs_reset = setup_coherent_ht_domain();
 154
 155 #if CONFIG_LOGICAL_CPUS==1
 156         // It is said that we should start core1 after all core0 launched
 157         wait_all_core0_started();
 158         start_other_cores();
 159 #endif
 160         wait_all_aps_started(bsp_apicid);
 161
 162         needs_reset |= ht_setup_chains_x();
 163
 164         bcm5785_early_setup();
 165
 166         if (needs_reset) {
 167                 print_info("ht reset -\n");
 168                 soft_reset();
 169         }
 170
 171         allow_all_aps_stop(bsp_apicid);
 172
 173         nodes = get_nodes();
 174         //It's the time to set ctrl now;
 175         fill_mem_ctrl(nodes, ctrl, spd_addr);
 176
 177         enable_smbus();
 178
 179 #if 0
 180         int i;
 181         for(i=4;i<8;i++) {
 182                 change_i2c_mux(i);
 183                 dump_smbus_registers();
 184         }
 185 #endif
 186
 187         memreset_setup();
 188
 189 //      init_timer();
 190
 191         sdram_initialize(nodes, ctrl);
 192
 193 #if 0
 194         print_pci_devices();
 195 #endif
 196
 197 #if 0
 198         dump_pci_devices();
 199 #endif
 200
 201         post_cache_as_ram();
 202
 203 }
 204