5 uses USE_FALLBACK_IMAGE
6 uses HAVE_FALLBACK_BOOT
11 uses CONFIG_MAX_PHYSICAL_CPUS
12 uses CONFIG_LOGICAL_CPUS
20 uses ROM_SECTION_OFFSET
21 uses CONFIG_ROM_PAYLOAD
22 uses CONFIG_ROM_PAYLOAD_START
23 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
24 uses CONFIG_PRECOMPRESSED_PAYLOAD
32 uses LB_CKS_RANGE_START
35 uses MAINBOARD_PART_NUMBER
38 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
39 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
40 uses COREBOOT_EXTRA_VERSION
45 uses DEFAULT_CONSOLE_LOGLEVEL
46 uses MAXIMUM_CONSOLE_LOGLEVEL
47 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
48 uses CONFIG_CONSOLE_SERIAL8250
56 uses CONFIG_CONSOLE_VGA
57 uses CONFIG_PCI_ROM_RUN
58 uses HW_MEM_HOLE_SIZEK
59 uses HT_CHAIN_UNITID_BASE
60 uses HT_CHAIN_END_UNITID_BASE
61 uses SB_HT_CHAIN_ON_BUS0
67 uses CONFIG_USE_PRINTK_IN_CAR
69 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
76 ## ROM_SIZE is the size of boot ROM that this board will use.
78 default ROM_SIZE=524288
81 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
83 #default FALLBACK_SIZE=131072
85 default FALLBACK_SIZE=0x40000
88 ## Build code for the fallback boot
90 default HAVE_FALLBACK_BOOT=1
93 ## Build code to reset the motherboard from coreboot
95 default HAVE_HARD_RESET=1
98 ## Build code to export a programmable irq routing table
100 default HAVE_PIRQ_TABLE=1
101 default IRQ_SLOT_COUNT=11
104 ## Build code to export an x86 MP table
105 ## Useful for specifying IRQ routing values
107 default HAVE_MP_TABLE=1
110 ## Build code to export a CMOS option table
112 default HAVE_OPTION_TABLE=1
115 ## Move the default coreboot cmos range off of AMD RTC registers
117 default LB_CKS_RANGE_START=49
118 default LB_CKS_RANGE_END=122
119 default LB_CKS_LOC=123
122 ## Build code for SMP support
123 ## Only worry about 2 micro processors
126 default CONFIG_MAX_CPUS=4
127 default CONFIG_MAX_PHYSICAL_CPUS=2
128 default CONFIG_LOGICAL_CPUS=1
131 default HW_MEM_HOLE_SIZEK=0x100000
134 #default CONFIG_CONSOLE_VGA=1
135 #default CONFIG_PCI_ROM_RUN=1
138 default HT_CHAIN_UNITID_BASE=0x6
141 default HT_CHAIN_END_UNITID_BASE=0x1
143 #make the SB HT chain on bus 0
144 default SB_HT_CHAIN_ON_BUS0=1
147 ## enable CACHE_AS_RAM specifics
149 default USE_DCACHE_RAM=1
150 default DCACHE_RAM_BASE=0xcf000
151 default DCACHE_RAM_SIZE=0x1000
152 default CONFIG_USE_INIT=0
155 ## Build code to setup a generic IOAPIC
157 default CONFIG_IOAPIC=1
160 ## Clean up the motherboard id strings
162 default MAINBOARD_PART_NUMBER="blast"
163 default MAINBOARD_VENDOR="Broadcom"
164 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
165 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
169 ### coreboot layout values
172 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
173 default ROM_IMAGE_SIZE = 65536
176 ## Use a small 8K stack
178 default STACK_SIZE=0x2000
181 ## Use a small 16K heap
183 default HEAP_SIZE=0x4000
186 ## Only use the option table in a normal image
188 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
191 ## Coreboot C code runs at this location in RAM
193 default _RAMBASE=0x00004000
196 ## Load the payload from the ROM
198 default CONFIG_ROM_PAYLOAD = 1
201 ### Defaults of options that you may want to override in the target config file
205 ## The default compiler
207 default CC="$(CROSS_COMPILE)gcc -m32"
211 ## Disable the gdb stub by default
213 default CONFIG_GDB_STUB=0
215 default CONFIG_USE_PRINTK_IN_CAR=1
218 ## The Serial Console
221 # To Enable the Serial Console
222 default CONFIG_CONSOLE_SERIAL8250=1
224 ## Select the serial console baud rate
225 default TTYS0_BAUD=115200
226 #default TTYS0_BAUD=57600
227 #default TTYS0_BAUD=38400
228 #default TTYS0_BAUD=19200
229 #default TTYS0_BAUD=9600
230 #default TTYS0_BAUD=4800
231 #default TTYS0_BAUD=2400
232 #default TTYS0_BAUD=1200
234 # Select the serial console base port
235 default TTYS0_BASE=0x3f8
237 # Select the serial protocol
238 # This defaults to 8 data bits, 1 stop bit, and no parity
239 default TTYS0_LCS=0x3
242 ### Select the coreboot loglevel
244 ## EMERG 1 system is unusable
245 ## ALERT 2 action must be taken immediately
246 ## CRIT 3 critical conditions
247 ## ERR 4 error conditions
248 ## WARNING 5 warning conditions
249 ## NOTICE 6 normal but significant condition
250 ## INFO 7 informational
251 ## DEBUG 8 debug-level messages
252 ## SPEW 9 Way too many details
254 ## Request this level of debugging output
255 default DEFAULT_CONSOLE_LOGLEVEL=8
256 ## At a maximum only compile in this level of debugging
257 default MAXIMUM_CONSOLE_LOGLEVEL=8
260 ## Select power on after power fail setting
261 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
268 default CONFIG_ROMFS=0