2 * This file is part of the coreboot project.
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <arch/smp/mpspec.h>
23 #include <arch/ioapic.h>
24 #include <device/pci.h>
28 static void *smp_write_config_table(void *v)
30 static const char sig[4] = "PCMP";
31 static const char oem[8] = "COREBOOT";
32 static const char productid[12] = "ASUS P2B-D ";
33 struct mp_config_table *mc;
35 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
36 memset(mc, 0, sizeof(*mc));
38 memcpy(mc->mpc_signature, sig, sizeof(sig));
39 mc->mpc_length = sizeof(*mc); /* initially just the header */
41 mc->mpc_checksum = 0; /* not yet computed */
42 memcpy(mc->mpc_oem, oem, sizeof(oem));
43 memcpy(mc->mpc_productid, productid, sizeof(productid));
46 mc->mpc_entry_count = 0; /* No entries yet... */
47 mc->mpc_lapic = LAPIC_ADDR;
52 smp_write_processors(mc);
54 /* Bus: Bus ID Type */
55 smp_write_bus(mc, 0, "PCI ");
56 smp_write_bus(mc, 1, "PCI ");
57 smp_write_bus(mc, 2, "ISA ");
59 /* I/O APICs: APIC ID Version State Address */
60 smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
64 dev = dev_find_slot(1, PCI_DEVFN(0x1e, 0));
66 res = find_resource(dev, PCI_BASE_ADDRESS_0);
68 smp_write_ioapic(mc, 3, 0x20, res->base);
70 dev = dev_find_slot(1, PCI_DEVFN(0x1c, 0));
72 res = find_resource(dev, PCI_BASE_ADDRESS_0);
74 smp_write_ioapic(mc, 4, 0x20, res->base);
76 dev = dev_find_slot(4, PCI_DEVFN(0x1e, 0));
78 res = find_resource(dev, PCI_BASE_ADDRESS_0);
80 smp_write_ioapic(mc, 5, 0x20, res->base);
82 dev = dev_find_slot(4, PCI_DEVFN(0x1c, 0));
84 res = find_resource(dev, PCI_BASE_ADDRESS_0);
86 smp_write_ioapic(mc, 8, 0x20, res->base);
90 mptable_add_isa_interrupts(mc, 0x2, 0x2, 0);
92 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
94 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
97 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
98 smp_write_intsrc(mc, mp_ExtINT,
99 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x2, 0x0,
101 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
102 0x2, 0x0, MP_APIC_ALL, 0x1);
104 /* There is no extension information... */
106 /* Compute the checksums */
108 smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
109 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
110 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
111 mc, smp_next_mpe_entry(mc));
112 return smp_next_mpe_entry(mc);
115 unsigned long write_smp_table(unsigned long addr)
118 v = smp_write_floating_table(addr);
119 return (unsigned long)smp_write_config_table(v);