2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <device/pci_def.h>
26 #include <device/pnp_def.h>
27 #include <arch/romcc_io.h>
30 #include "pc80/serial.c"
31 #include "arch/i386/lib/console.c"
32 #include "ram/ramtest.c"
33 #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
34 #include "northbridge/intel/i82810/raminit.h"
35 #include "cpu/x86/mtrr/earlymtrr.c"
36 #include "cpu/x86/bist.h"
38 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
40 #include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
42 /* TODO: Not needed? */
43 void udelay(int usecs)
46 for (i = 0; i < usecs; i++)
51 #include "lib/delay.c"
53 #include "northbridge/intel/i82810/raminit.c"
54 #include "northbridge/intel/i82810/debug.c"
55 #include "sdram/generic_sdram.c"
57 static void main(unsigned long bist)
59 static const struct mem_controller memctrl[] = {
61 .d0 = PCI_DEV(0, 0, 0),
62 .channel0 = {0x50, 0x51},
71 lpc47b272_enable_serial(SERIAL_DEV, TTYS0_BASE);
75 /* Halt if there was a built in self test failure. */
76 report_bist_failure(bist);
78 /* dump_spd_registers(&memctrl[0]); */
80 /* sdram_initialize() runs out of registers. */
81 /* sdram_initialize(ARRAY_SIZE(memctrl), memctrl); */
83 sdram_set_registers(memctrl);
84 sdram_set_spd_registers(memctrl);
85 sdram_enable(0, memctrl);
88 /* ram_check(0, 640 * 1024); */