4 uses USE_FALLBACK_IMAGE
5 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_ROM_PAYLOAD
13 uses MAINBOARD_PART_NUMBER
14 uses COREBOOT_EXTRA_VERSION
23 uses ROM_SECTION_OFFSET
24 uses CONFIG_ROM_PAYLOAD_START
25 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
26 uses CONFIG_PRECOMPRESSED_PAYLOAD
37 uses DEFAULT_CONSOLE_LOGLEVEL
38 uses MAXIMUM_CONSOLE_LOGLEVEL
39 uses CONFIG_CONSOLE_SERIAL8250
43 uses CONFIG_UDELAY_TSC
46 ## ROM_SIZE is the size of boot ROM that this board will use.
47 default ROM_SIZE = 512*1024
54 ## Build code for the fallback boot
56 default HAVE_FALLBACK_BOOT = 1
61 default HAVE_MP_TABLE = 0
64 ## Build code to reset the motherboard from coreboot
66 default HAVE_HARD_RESET = 0
69 ## Build code to export a programmable irq routing table
71 default HAVE_PIRQ_TABLE = 1
72 default IRQ_SLOT_COUNT = 11
75 ## Build code to export a CMOS option table
77 default HAVE_OPTION_TABLE = 0
80 default CONFIG_IDE = 1
83 ### coreboot layout values
86 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
87 default ROM_IMAGE_SIZE = 65536
88 default FALLBACK_SIZE = 131072
91 ## Use a small 8K stack
93 default STACK_SIZE=0x2000
96 ## Use a small 16K heap
98 default HEAP_SIZE=0x4000
101 ## Only use the option table in a normal image
103 #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
104 default USE_OPTION_TABLE = 0
106 default _RAMBASE = 0x00004000
108 default CONFIG_ROM_PAYLOAD = 1
111 ## The default compiler
113 default CROSS_COMPILE=""
114 default CC="$(CROSS_COMPILE)gcc -m32"
118 ## The Serial Console
121 # To Enable the Serial Console
122 default CONFIG_CONSOLE_SERIAL8250=1
124 ## Select the serial console baud rate
125 default TTYS0_BAUD=115200
126 #default TTYS0_BAUD=57600
127 #default TTYS0_BAUD=38400
128 #default TTYS0_BAUD=19200
129 #default TTYS0_BAUD=9600
130 #default TTYS0_BAUD=4800
131 #default TTYS0_BAUD=2400
132 #default TTYS0_BAUD=1200
134 # Select the serial console base port
135 default TTYS0_BASE=0x3f8
137 # Select the serial protocol
138 # This defaults to 8 data bits, 1 stop bit, and no parity
139 default TTYS0_LCS=0x3
142 ### Select the coreboot loglevel
144 ## EMERG 1 system is unusable
145 ## ALERT 2 action must be taken immediately
146 ## CRIT 3 critical conditions
147 ## ERR 4 error conditions
148 ## WARNING 5 warning conditions
149 ## NOTICE 6 normal but significant condition
150 ## INFO 7 informational
151 ## DEBUG 8 debug-level messages
152 ## SPEW 9 Way too many details
154 ## Request this level of debugging output
155 default DEFAULT_CONSOLE_LOGLEVEL=9
156 ## At a maximum only compile in this level of debugging
157 default MAXIMUM_CONSOLE_LOGLEVEL=9
159 default CONFIG_UDELAY_TSC=1
165 default CONFIG_CBFS=0