2 * This file is part of the coreboot project.
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include "NbPlatform.h"
25 #define RD890_IOAPIC_ADDR 0xC8000000
26 /* platform dependent configuration default value */
30 * [0..7] - Node (0..8)
31 * [8..11] - Link (0..3)
32 * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
34 #ifndef DEFAULT_HT_PATH
35 #if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1
36 #define DEFAULT_HT_PATH {0x0, 0x3}
38 #if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1
39 #define DEFAULT_HT_PATH {0x0, 0x1}
44 * Bitmap of enabled ports on NB #0/1/2/3
47 * Bit[2] - Enable PCIe port 2
48 * Bit[3] - Enable PCIe port 3
49 * Bit[4] - Enable PCIe port 4
50 * Bit[5] - Enable PCIe port 5
51 * Bit[6] - Enable PCIe port 2
52 * Bit[7] - Enable PCIe port 7
54 * Bit[9] - Enable PCIe port 9
55 * Bit[10]- Enable PCIe port 10
56 * Bit[11]- Enable PCIe port 11
57 * Bit[12]- Enable PCIe port 12
58 * Bit[13]- Enable PCIe port 13
61 * Port 2 and 4 enabled for training/initialization
63 #ifndef DEFAULT_PORT_ENABLE_MAP
64 #define DEFAULT_PORT_ENABLE_MAP 0x0014
68 * Bitmap of ports that have slot or onboard device connected.
69 * Example force PCIe Gen1 supporton port 2 and 4 (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4)
70 * #define DEFAULT_PORT_FORCE_GEN1 0x604
72 #ifndef DEFAULT_PORT_FORCE_GEN1
73 #define DEFAULT_PORT_FORCE_GEN1 0x0
77 * Bitmap of ports that have server hotplug support
79 #ifndef DEFAULT_HOTPLUG_SUPPORT
80 #define DEFAULT_HOTPLUG_SUPPORT 0x0
83 #ifndef DEFAULT_HOTPLUG_DESCRIPTOR
84 #define DEFAULT_HOTPLUG_DESCRIPTOR {0, 0, 0, 0, 0, 0, 0, 0}
87 #ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS
88 #define DEFAULT_TEMPMMIO_BASE_ADDRESS 0xD0000000
92 * Default GPP1 core configuraton on NB #0/1/2/3.
93 * 2 x8 slot, GFX_CONFIG_AABB
94 * 1 x16 slot, GFX_CONFIG_AAAA
96 #ifndef DEFAULT_GPP1_CONFIG
97 #define DEFAULT_GPP1_CONFIG GFX_CONFIG_AABB
101 * Default GPP2 core configuraton on NB #0/1/2/3.
102 * 2 x8 slot, GFX_CONFIG_AABB
103 * 1 x16 slot, GFX_CONFIG_AAAA
105 #ifndef DEFAULT_GPP2_CONFIG
106 #define DEFAULT_GPP2_CONFIG GFX_CONFIG_AABB
110 * Default GPP3a core configuraton on NB #0/1/2/3.
111 * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1
112 * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2
113 * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3
114 * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4
115 * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5
116 * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6
118 #ifndef DEFAULT_GPP3A_CONFIG
119 #define DEFAULT_GPP3A_CONFIG GPP_CONFIG_GPP111111
124 * Default HT Transmitter de-emphasis setting
126 #ifndef DEFAULT_HT_DEEMPASIES
127 #define DEFAULT_HT_DEEMPASIES 0x3
131 * Default APIC nterrupt base for IOAPIC
133 #ifndef DEFAULT_APIC_INTERRUPT_BASE
134 #define DEFAULT_APIC_INTERRUPT_BASE 24
138 #define DEFAULT_PLATFORM_CONFIG(name) \
139 NB_PLATFORM_CONFIG name = { \
140 DEFAULT_PORT_ENABLE_MAP, \
141 DEFAULT_PORT_FORCE_GEN1, \
142 DEFAULT_HOTPLUG_SUPPORT, \
143 DEFAULT_HOTPLUG_DESCRIPTOR, \
144 DEFAULT_TEMPMMIO_BASE_ADDRESS, \
145 DEFAULT_GPP1_CONFIG, \
146 DEFAULT_GPP2_CONFIG, \
147 DEFAULT_GPP3A_CONFIG, \
148 DEFAULT_HT_DEEMPASIES, \
149 /*DEFAULT_HT_PATH,*/ \
150 DEFAULT_APIC_INTERRUPT_BASE, \
154 * Platform configuration
157 UINT16 PortEnableMap; ///< Bitmap of enabled ports
158 UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2
159 UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug
160 UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors
161 UINT32 TemporaryMmio; ///< Temporary MMIO
162 UINT32 Gpp1Config; ///< Default PCIe GFX core configuration
163 UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration
164 UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration
165 UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level
166 // HT_PATH NbHtPath; ///< HT path to NB
167 UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC.
168 } NB_PLATFORM_CONFIG;
171 * Bridge CIMx configuration
173 void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig);
175 #endif //_RD890_CFG_H_