2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #ifndef _M5A99X_EVO_CFG_H_
22 #define _M5A99X_EVO_CFG_H_
30 #define BIOS_SIZE_1M 0
31 #define BIOS_SIZE_2M 1
32 #define BIOS_SIZE_4M 3
33 #define BIOS_SIZE_8M 7
35 /* In SB800, default ROM size is 1M Bytes, if your platform ROM
36 * bigger than 1M you have to set the ROM size outside CIMx module and
37 * before AGESA module get call.
39 #if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
40 #define BIOS_SIZE BIOS_SIZE_1M
41 #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
42 #define BIOS_SIZE BIOS_SIZE_2M
43 #elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
44 #define BIOS_SIZE BIOS_SIZE_4M
45 #elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
46 #define BIOS_SIZE BIOS_SIZE_8M
50 * @def SPREAD_SPECTRUM
52 * 0 - Disable Spread Spectrum function
53 * 1 - Enable Spread Spectrum function
55 #define SPREAD_SPECTRUM 0
67 * @brief bit[0-6] used to control USB
70 * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
71 * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
72 * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
73 * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
74 * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
75 * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
76 * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
78 #define USB_CONFIG 0x7F
82 * @breif bit[0-4] used for PCI Slots Clock Control,
85 * PCI SLOT 0 define at BIT0
86 * PCI SLOT 1 define at BIT1
87 * PCI SLOT 2 define at BIT2
88 * PCI SLOT 3 define at BIT3
89 * PCI SLOT 4 define at BIT4
91 #define PCI_CLOCK_CTRL 0x1F
95 * @def SATA_CONTROLLER
96 * @breif INCHIP Sata Controller
98 #define SATA_CONTROLLER CIMX_OPTION_ENABLED
103 * @breif INCHIP Sata Controller Mode
104 * NOTE: DO NOT ALLOW SATA & IDE use same mode
106 #define SATA_MODE NATIVE_IDE_MODE
109 * @breif INCHIP Sata IDE Controller Mode
111 #define IDE_LEGACY_MODE 0
112 #define IDE_NATIVE_MODE 1
116 * @breif INCHIP Sata IDE Controller Mode
117 * NOTE: DO NOT ALLOW SATA & IDE use same mode
119 #define SATA_IDE_MODE IDE_LEGACY_MODE
122 * @def EXTERNAL_CLOCK
123 * @brief 00/10: Reference clock from crystal oscillator via
124 * PAD_XTALI and PAD_XTALO
126 * @def INTERNAL_CLOCK
127 * @brief 01/11: Reference clock from internal clock through
128 * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
130 #define EXTERNAL_CLOCK 0x00
131 #define INTERNAL_CLOCK 0x01
133 /* NOTE: inagua have to using internal clock,
134 * otherwise can not detect sata drive
136 #define SATA_CLOCK_SOURCE INTERNAL_CLOCK
139 * @def SATA_PORT_MULT_CAP_RESERVED
142 #define SATA_PORT_MULT_CAP_RESERVED 1
147 * @brief Detect Azalia controller automatically.
149 * @def AZALIA_DISABLE
150 * @brief Disable Azalia controller.
153 * @brief Enable Azalia controller.
155 #define AZALIA_AUTO 0
156 #define AZALIA_DISABLE 1
157 #define AZALIA_ENABLE 2
160 * @breif INCHIP HDA controller
162 #define AZALIA_CONTROLLER AZALIA_AUTO
166 * @def AZALIA_PIN_CONFIG
171 #define AZALIA_PIN_CONFIG 1
175 * @def AZALIA_SDIN_PIN
177 * SDIN0 is define at BIT0 & BIT1
180 * 10 - As a Azalia SDIN pin
181 * SDIN1 is define at BIT2 & BIT3
182 * SDIN2 is define at BIT4 & BIT5
183 * SDIN3 is define at BIT6 & BIT7
185 //#define AZALIA_SDIN_PIN 0xAA
186 #define AZALIA_SDIN_PIN 0x2A
189 * @def GPP_CONTROLLER
191 #define GPP_CONTROLLER CIMX_OPTION_ENABLED
195 * @brief GPP Link Configuration
196 * four possible configuration:
202 #define GPP_CFGMODE GPP_CFGMODE_X1111
209 #define NB_SB_GEN2 TRUE
216 #define SB_GPP_GEN2 TRUE
219 * @def SB_GPP_UNHIDE_PORTS
220 * TRUE - ports visable always, even port empty
221 * FALSE - ports invisable if port empty
223 #define SB_GPP_UNHIDE_PORTS FALSE
233 * @def SIO_HWM_BASE_ADDRESS Super IO HWM base address
235 #define SIO_HWM_BASE_ADDRESS 0x290
239 * @section SBCIMx_LEGACY_FREE SBCIMx_LEGACY_FREE
240 * @li <b>1</b> - Legacy free enable
241 * @li <b>0</b> - Legacy free disable
243 #ifndef SBCIMx_LEGACY_FREE
244 #define SBCIMx_LEGACY_FREE 0
249 * @li <b>0</b> - Disable
250 * @li <b>1</b> - Enable
252 #ifndef SBCIMX_SPI_SPEED
253 #define SBCIMX_SPI_SPEED 0
257 * @section SpiFastSpeed
258 * @li <b>0</b> - Disable
259 * @li <b>1</b> - Enable
261 #ifndef SBCIMX_SPI_FASTSPEED
262 #define SBCIMX_SPI_FASTSPEED 0
267 * @li <b>0</b> - Disable
268 * @li <b>1</b> - Enable
270 #ifndef SBCIMX_SPI_MODE
271 #define SBCIMX_SPI_MODE 0
275 * @section SpiBurstWrite
276 * @li <b>0</b> - Disable
277 * @li <b>1</b> - Enable
279 #ifndef SBCIMX_SPI_BURST_WRITE
280 #define SBCIMX_SPI_BURST_WRITE 0
284 * @section INCHIP_EC_KBD INCHIP_EC_KBD
285 * @li <b>0</b> - Use SIO PS/2 function.
286 * @li <b>1</b> - Use EC PS/2 function.
288 #ifndef INCHIP_EC_KBD
289 #define INCHIP_EC_KBD 0
293 * @section INCHIP_EC_CHANNEL10 INCHIP_EC_CHANNEL10
294 * @li <b>0</b> - EC controller NOT support Channel10
295 * @li <b>1</b> - EC controller support Channel10.
297 #ifndef INCHIP_EC_CHANNEL10
298 #define INCHIP_EC_CHANNEL10 1
302 * @section Smbus0BaseAddress
304 // #ifndef SMBUS0_BASE_ADDRESS
305 // #define SMBUS0_BASE_ADDRESS 0xB00
309 * @section Smbus1BaseAddress
311 // #ifndef SMBUS1_BASE_ADDRESS
312 // #define SMBUS1_BASE_ADDRESS 0xB21
316 * @section SioPmeBaseAddress
318 // #ifndef SIO_PME_BASE_ADDRESS
319 // #define SIO_PME_BASE_ADDRESS 0xE00
323 * @section WatchDogTimerBase
325 // #ifndef WATCHDOG_TIMER_BASE_ADDRESS
326 // #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000
330 * @section GecShadowRomBase
332 #ifndef GEC_ROM_SHADOW_ADDRESS
333 #define GEC_ROM_SHADOW_ADDRESS 0xFED61000
337 * @section SpiRomBaseAddress
339 // #ifndef SPI_BASE_ADDRESS
340 // #define SPI_BASE_ADDRESS 0xFEC10000
344 * @section AcpiPm1EvtBlkAddr
346 // #ifndef PM1_EVT_BLK_ADDRESS
347 // #define PM1_EVT_BLK_ADDRESS 0x400
351 * @section AcpiPm1CntBlkAddr
353 // #ifndef PM1_CNT_BLK_ADDRESS
354 // #define PM1_CNT_BLK_ADDRESS 0x404
358 * @section AcpiPmTmrBlkAddr
360 // #ifndef PM1_TMR_BLK_ADDRESS
361 // #define PM1_TMR_BLK_ADDRESS 0x408
365 * @section CpuControlBlkAddr
367 // #ifndef CPU_CNT_BLK_ADDRESS
368 // #define CPU_CNT_BLK_ADDRESS 0x410
372 * @section AcpiGpe0BlkAddr
374 // #ifndef GPE0_BLK_ADDRESS
375 // #define GPE0_BLK_ADDRESS 0x420
379 * @section SmiCmdPortAddr
381 // #ifndef SMI_CMD_PORT
382 // #define SMI_CMD_PORT 0xB0
386 * @section AcpiPmaCntBlkAddr
388 // #ifndef ACPI_PMA_CNT_BLK_ADDRESS
389 // #define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
393 * @section SataController
394 * @li <b>0</b> - Disable
395 * @li <b>1</b> - Enable
397 #ifndef INCHIP_SATA_CONTROLLER
398 #define INCHIP_SATA_CONTROLLER 1
402 * @section SataIdeCombMdPriSecOpt
403 * @li <b>0</b> - Primary
404 * @li <b>1</b> - Secondary<TD></TD>
405 * Sata Controller set as primary or
406 * secondary while Combined Mode is enabled
408 #ifndef SATA_COMBINE_MODE_CHANNEL
409 #define SATA_COMBINE_MODE_CHANNEL 0
413 * @section SataSetMaxGen2
414 * @li <b>0</b> - Disable
415 * @li <b>1</b> - Enable
416 * SataController Set to Max Gen2 mode
418 #ifndef SATA_MAX_GEN2_MODE
419 #define SATA_MAX_GEN2_MODE 0
423 * @section SataIdeCombinedMode
424 * @li <b>0</b> - Disable
425 * @li <b>1</b> - Enable
426 * Sata IDE Controller set to Combined Mode
428 #ifndef SATA_COMBINE_MODE
429 #define SATA_COMBINE_MODE 0
432 #define SATA_CLK_RESERVED 9
436 * @li <b>0</b> - Disable
437 * @li <b>1</b> - Enable
444 * @section SataInternal100Spread
445 * @li <b>0</b> - Disable
446 * @li <b>1</b> - Enable
448 #ifndef INCHIP_SATA_INTERNAL_100_SPREAD
449 #define INCHIP_SATA_INTERNAL_100_SPREAD 0
454 * @li <b>0</b> - Disable
455 * @li <b>1</b> - Enable
457 #ifndef INCHIP_CG2_PLL
458 #define INCHIP_CG2_PLL 0
465 * @section SpreadSpectrum
466 * @li <b>0</b> - Disable
467 * @li <b>1</b> - Enable
468 * Spread Spectrum function
470 #define INCHIP_SPREAD_SPECTRUM 1
473 * @section INCHIP_USB_CINFIG INCHIP_USB_CINFIG
475 * - Usb Ohci1 Contoller is define at BIT0
477 * (Bus 0 Dev 18 Func0)
478 * - Usb Ehci1 Contoller is define at BIT1
480 * (Bus 0 Dev 18 Func2)
481 * - Usb Ohci2 Contoller is define at BIT2
483 * (Bus 0 Dev 19 Func0)
484 * - Usb Ehci2 Contoller is define at BIT3
486 * (Bus 0 Dev 19 Func2)
487 * - Usb Ohci3 Contoller is define at BIT4
489 * (Bus 0 Dev 22 Func0)
490 * - Usb Ehci3 Contoller is define at BIT5
492 * (Bus 0 Dev 22 Func2)
493 * - Usb Ohci4 Contoller is define at BIT6
495 * (Bus 0 Dev 20 Func5)
497 #define INCHIP_USB_CINFIG 0x7F
498 #define INCHIP_USB_OHCI1_CINFIG 0x01
499 #define INCHIP_USB_OHCI2_CINFIG 0x01
500 #if CONFIG_ONBOARD_USB30 == 1
501 #define INCHIP_USB_OHCI3_CINFIG 0x00
503 #define INCHIP_USB_OHCI3_CINFIG 0x01
505 #define INCHIP_USB_OHCI4_CINFIG 0x01
506 #define INCHIP_USB_EHCI1_CINFIG 0x01
507 #define INCHIP_USB_EHCI2_CINFIG 0x01
508 #define INCHIP_USB_EHCI3_CINFIG 0x01
511 * @section INCHIP_SATA_MODE INCHIP_SATA_MODE
512 * @li <b>000</b> - Native IDE mode
513 * @li <b>001</b> - RAID mode
514 * @li <b>010</b> - AHCI mode
515 * @li <b>011</b> - Legacy IDE mode
516 * @li <b>100</b> - IDE->AHCI mode
517 * @li <b>101</b> - AHCI mode as 7804 ID (AMD driver)
518 * @li <b>110</b> - IDE->AHCI mode as 7804 ID (AMD driver)
520 #define INCHIP_SATA_MODE 0
523 * @section INCHIP_IDE_MODE INCHIP_IDE_MODE
524 * @li <b>0</b> - Legacy IDE mode
525 * @li <b>1</b> - Native IDE mode<TD></TD>
526 * ** DO NOT ALLOW SATA & IDE use same mode **
528 #define INCHIP_IDE_MODE 1
530 #define SATA_PORT_MULT_CAP_RESERVED 1
533 * @section INCHIP_AZALIA_CONTROLLER INCHIP_AZALIA_CONTROLLER
534 * @li <b>0</b> - Auto : Detect Azalia controller automatically.
535 * @li <b>1</b> - Diable : Disable Azalia controller.
536 * @li <b>2</b> - Enable : Enable Azalia controller.
538 #define INCHIP_AZALIA_CONTROLLER 2
539 #define AZALIA_AUTO 0
540 #define AZALIA_DISABLE 1
541 #define AZALIA_ENABLE 2
544 * @section INCHIP_AZALIA_PIN_CONFIG INCHIP_AZALIA_PIN_CONFIG
545 * @li <b>0</b> - disable
546 * @li <b>1</b> - enable
548 #define INCHIP_AZALIA_PIN_CONFIG 1
551 * @section AZALIA_PIN_CONFIG AZALIA_PIN_CONFIG
553 * SDIN0 is define at BIT0 & BIT1
556 * - 10: As a Azalia SDIN pin<TD></TD>
557 * SDIN1 is define at BIT2 & BIT3
560 * - 10: As a Azalia SDIN pin<TD></TD>
561 * SDIN2 is define at BIT4 & BIT5
564 * - 10: As a Azalia SDIN pin<TD></TD>
565 * SDIN3 is define at BIT6 & BIT7
568 * - 10: As a Azalia SDIN pin
570 #define AZALIA_PIN_CONFIG 0x2A
573 * @section AzaliaSnoop
574 * @li <b>0</b> - disable
575 * @li <b>1</b> - enable *
577 #define INCHIP_AZALIA_SNOOP 0x01
580 * @section NCHIP_GEC_CONTROLLER
581 * @li <b>0</b> - Enable *
582 * @li <b>1</b> - Disable
584 #define INCHIP_GEC_CONTROLLER 0x00
587 * @section SB_HPET_TIMER SB_HPET_TIMER
588 * @li <b>0</b> - Disable
589 * @li <b>1</b> - Enable
591 #define SB_HPET_TIMER 1
594 * @section SB_GPP_CONTROLLER SB_GPP_CONTROLLER
595 * @li <b>0</b> - Disable
596 * @li <b>1</b> - Enable
598 #define SB_GPP_CONTROLLER 1
601 * @section GPP_LINK_CONFIG GPP_LINK_CONFIG
602 * @li <b>0000</b> - Port ABCD -> 4:0:0:0
603 * @li <b>0001</b> - N/A
604 * @li <b>0010</b> - Port ABCD -> 2:2:0:0
605 * @li <b>0011</b> - Port ABCD -> 2:1:1:0
606 * @li <b>0100</b> - Port ABCD -> 1:1:1:1
608 #define GPP_LINK_CONFIG 4
611 * @section SB_GPP_PORT0 SB_GPP_PORT0
612 * @li <b>0</b> - Disable
613 * @li <b>1</b> - Enable
615 #define SB_GPP_PORT0 1
618 * @section SB_GPP_PORT1 SB_GPP_PORT1
619 * @li <b>0</b> - Disable
620 * @li <b>1</b> - Enable
622 #define SB_GPP_PORT1 1
625 * @section SB_GPP_PORT2 SB_GPP_PORT2
626 * @li <b>0</b> - Disable
627 * @li <b>1</b> - Enable
629 #define SB_GPP_PORT2 1
632 * @section SB_GPP_PORT3 SB_GPP_PORT3
633 * @li <b>0</b> - Disable
634 * @li <b>1</b> - Enable
636 #define SB_GPP_PORT3 1
639 * @section SB_IR_CONTROLLER
640 * @li <b>00 </b> - disable
641 * @li <b>01 </b> - Rx and Tx0
642 * @li <b>10 </b> - Rx and Tx1
643 * @li <b>11 </b> - Rx and both Tx0,Tx1
645 #define SB_IR_CONTROLLER 3
648 * @section INCHIP_USB_PHY_POWER_DOWN
649 * @li <b>0</b> - Disable
650 * @li <b>1</b> - Enable
652 #define INCHIP_USB_PHY_POWER_DOWN 0
655 * @section INCHIP_NATIVE_PCIE_SUPPOORT
656 * @li <b>0</b> - Disable
657 * @li <b>1</b> - Enable
659 #define INCHIP_NATIVE_PCIE_SUPPOORT 1
662 * @section INCHIP_NB_SB_GEN2
663 * @li <b>0</b> - Disable
664 * @li <b>1</b> - Enable
666 #define INCHIP_NB_SB_GEN2 1
669 * @section INCHIP_GPP_GEN2
670 * @li <b>0</b> - Disable
671 * @li <b>1</b> - Enable
673 #define INCHIP_GPP_GEN2 1
676 * @section INCHIP_GPP_MEMORY_WRITE_IMPROVE
677 * @li <b>0</b> - Disable
678 * @li <b>1</b> - Enable
680 #define INCHIP_GPP_MEMORY_WRITE_IMPROVE 1
683 * @section INCHIP_GEC_PHY_STATUS
684 * @li <b>0</b> - Gb PHY Mode *
685 * @li <b>1</b> - 100/10 PHY Mode
687 #define INCHIP_GEC_PHY_STATUS 0
690 * @section INCHIP_GEC_POWER_POLICY
691 * @li <b>0</b> - S3/S5
694 * @li <b>3</b> - Never power down *
696 #define INCHIP_GEC_POWER_POLICY 3
699 * @section INCHIP_GEC_DEBUGBUS
700 * @li <b>0</b> - Disable *
701 * @li <b>1</b> - Enable
703 #define INCHIP_GEC_DEBUGBUS 0
706 * @section SATA_MAX_GEN2_MODE SATA_MAX_GEN2_MODE
707 * @li <b>0</b> - Disable *
708 * @li <b>1</b> - Enable
709 * SataController Set to Max Gen2 mode
711 #define SATA_MAX_GEN2_MODE 0
714 * @section INCHIP_SATA_AGGR_LINK_PM_CAP
715 * @li <b>0</b> - Disable
716 * @li <b>1</b> - Enable *
717 * SataController Set to aggressive link PM capability
719 #define INCHIP_SATA_AGGR_LINK_PM_CAP 0
722 * @section INCHIP_SATA_PORT_MULT_CAP
723 * @li <b>0</b> - Disable
724 * @li <b>1</b> - Enable *
725 * SataController Set to Port Multiple capability
727 #define INCHIP_SATA_PORT_MULT_CAP 1
730 * @section INCHIP_SATA_PSC_CAP
731 * @li <b>0</b> - Disable
732 * @li <b>1</b> - Enable *
734 #define INCHIP_SATA_PSC_CAP 0
737 * @section INCHIP_SATA_SSC_CAP
738 * @li <b>0</b> - Disable
739 * @li <b>1</b> - Enable *
741 #define INCHIP_SATA_SSC_CAP 0
744 * @section INCHIP_SATA_CLK_AUTO_OFF
745 * @li <b>0</b> - Disable
746 * @li <b>1</b> - Enable *
748 #define INCHIP_SATA_CLK_AUTO_OFF 1
751 * @section INCHIP_SATA_FIS_BASE_SW
752 * @li <b>0</b> - Disable
753 * @li <b>1</b> - Enable *
755 #define INCHIP_SATA_FIS_BASE_SW 1
758 * @section INCHIP_SATA_CCC_SUPPORT
759 * @li <b>0</b> - Disable
760 * @li <b>1</b> - Enable *
762 #define INCHIP_SATA_CCC_SUPPORT 1
765 * @section INCHIP_SATA_MSI_CAP
766 * @li <b>0</b> - Disable
767 * @li <b>1</b> - Enable *
769 #define INCHIP_SATA_MSI_CAP 1
772 * @section CIMXSB_SATA_TARGET_8DEVICE_CAP
773 * @li <b>0</b> - Disable *
774 * @li <b>1</b> - Enable
776 #define CIMXSB_SATA_TARGET_8DEVICE_CAP 0
779 * @section SATA_DISABLE_GENERIC_MODE
780 * @li <b>0</b> - Disable *
781 * @li <b>1</b> - Enable
783 #define SATA_DISABLE_GENERIC_MODE_CAP 0
786 * @section SATA_AHCI_ENCLOSURE_CAP
787 * @li <b>0</b> - Disable *
788 * @li <b>1</b> - Enable
790 #define SATA_AHCI_ENCLOSURE_CAP 0
793 * @section SataForceRaid (RISD5 mode)
794 * @li <b>0</b> - Disable *
795 * @li <b>1</b> - Enable
797 #define INCHIP_SATA_FORCE_RAID5 0
800 * @section SATA_GPIO_0_CAP
801 * @li <b>0</b> - Disable *
802 * @li <b>1</b> - Enable
804 #define SATA_GPIO_0_CAP 0
807 * @section SATA_GPIO_1_CAP
808 * @li <b>0</b> - Disable *
809 * @li <b>1</b> - Enable
811 #define SATA_GPIO_1_CAP 0
814 * @section SataPhyPllShutDown
815 * @li <b>0</b> - Disable
816 * @li <b>1</b> - Enable *
818 #define SATA_PHY_PLL_SHUTDOWN 1
821 * @section ImcEnableOverWrite
822 * @li <b>0</b> - Disable
823 * @li <b>1</b> - Enable
825 #define IMC_ENABLE_OVER_WRITE 0
829 * @li <b>0</b> - Disable
830 * @li <b>1</b> - Enable
835 * @section HdAudioMsi
836 * @li <b>0</b> - Disable
837 * @li <b>1</b> - Enable
839 #define HDAUDIO_MSI 0
843 * @li <b>0</b> - Disable
844 * @li <b>1</b> - Enable
850 * @li <b>0</b> - Disable
851 * @li <b>1</b> - Enable
857 * @li <b>0</b> - Disable
858 * @li <b>1</b> - Enable
863 * @section GecShadowRomBase
864 * @li <b>0</b> - Disable
865 * @li <b>1</b> - Enable *
867 #define GEC_SHADOWROM_BASE 0xFED61000
870 * @section SataController
871 * @li <b>0</b> - Disable
872 * @li <b>1</b> - Enable *
874 #define SATA_CONTROLLER 1
877 * @section SataIdeCombMdPriSecOpt
878 * @li <b>0</b> - Disable
879 * @li <b>1</b> - Enable
881 #define SATA_IDE_COMBMD_PRISEC_OPT 0
884 * @section SataIdeCombinedMode
885 * @li <b>0</b> - Disable
886 * @li <b>1</b> - Enable
888 #define SATA_IDECOMBINED_MODE 0
892 * @li <b>0</b> - Disable
893 * @li <b>1</b> - Enable *
895 #define SB_SD_CONFIG 1
899 * @li <b>0</b> - Disable
900 * @li <b>1</b> - Enable *
902 #define SB_SD_SPEED 1
905 * @section sdBitwidth
906 * @li <b>0</b> - Disable
907 * @li <b>1</b> - Enable *
909 #define SB_SD_BITWIDTH 1
912 * @section SataDisUnusedIdePChannel
913 * @li <b>0</b> - Disable
914 * @li <b>1</b> - Enable
916 #define SATA_DISUNUSED_IDE_P_CHANNEL 0
919 * @section SataDisUnusedIdeSChannel
920 * @li <b>0</b> - Disable
921 * @li <b>1</b> - Enable
923 #define SATA_DISUNUSED_IDE_S_CHANNEL 0
926 * @section IdeDisUnusedIdePChannel
927 * @li <b>0</b> - Disable
928 * @li <b>1</b> - Enable
930 #define IDE_DISUNUSED_IDE_P_CHANNEL 0
933 * @section IdeDisUnusedIdeSChannel
934 * @li <b>0</b> - Disable
935 * @li <b>1</b> - Enable
937 #define IDE_DISUNUSED_IDE_S_CHANNEL 0
940 * @section IdeDisUnusedIdeSChannel
941 * @li <b>0</b> - Disable
942 * @li <b>1</b> - Enable
946 * @section SataEspPort0
947 * @li <b>0</b> - Disable
948 * @li <b>1</b> - Enable
950 #define SATA_ESP_PORT0 0
953 * @section SataEspPort1
954 * @li <b>0</b> - Disable
955 * @li <b>1</b> - Enable
957 #define SATA_ESP_PORT1 0
960 * @section SataEspPort2
961 * @li <b>0</b> - Disable
962 * @li <b>1</b> - Enable
964 #define SATA_ESP_PORT2 0
967 * @section SataEspPort3
968 * @li <b>0</b> - Disable
969 * @li <b>1</b> - Enable
971 #define SATA_ESP_PORT3 0
974 * @section SataEspPort4
975 * @li <b>0</b> - Disable
976 * @li <b>1</b> - Enable
978 #define SATA_ESP_PORT4 0
981 * @section SataEspPort5
982 * @li <b>0</b> - Disable
983 * @li <b>1</b> - Enable
985 #define SATA_ESP_PORT5 0
988 * @section SataEspPort6
989 * @li <b>0</b> - Disable
990 * @li <b>1</b> - Enable
992 #define SATA_ESP_PORT6 0
995 * @section SataEspPort7
996 * @li <b>0</b> - Disable
997 * @li <b>1</b> - Enable
999 #define SATA_ESP_PORT7 0
1002 * @section SataPortPower0
1003 * @li <b>0</b> - Disable
1004 * @li <b>1</b> - Enable
1006 #define SATA_PORT_POWER_PORT0 0
1009 * @section SataPortPower1
1010 * @li <b>0</b> - Disable
1011 * @li <b>1</b> - Enable
1013 #define SATA_PORT_POWER_PORT1 0
1016 * @section SataPortPower2
1017 * @li <b>0</b> - Disable
1018 * @li <b>1</b> - Enable
1020 #define SATA_PORT_POWER_PORT2 0
1023 * @section SataPortPower3
1024 * @li <b>0</b> - Disable
1025 * @li <b>1</b> - Enable
1027 #define SATA_PORT_POWER_PORT3 0
1030 * @section SataPortPower4
1031 * @li <b>0</b> - Disable
1032 * @li <b>1</b> - Enable
1034 #define SATA_PORT_POWER_PORT4 0
1037 * @section SataPortPower5
1038 * @li <b>0</b> - Disable
1039 * @li <b>1</b> - Enable
1041 #define SATA_PORT_POWER_PORT5 0
1044 * @section SataPortPower6
1045 * @li <b>0</b> - Disable
1046 * @li <b>1</b> - Enable
1048 #define SATA_PORT_POWER_PORT6 0
1051 * @section SataPortPower7
1052 * @li <b>0</b> - Disable
1053 * @li <b>1</b> - Enable
1055 #define SATA_PORT_POWER_PORT7 0
1058 * @section SataPortMd0
1059 * @li <b>0</b> - Disable
1060 * @li <b>1</b> - Enable
1062 #define SATA_PORTMODE_PORT0 3
1065 * @section SataPortMd1
1066 * @li <b>0</b> - Disable
1067 * @li <b>1</b> - Enable
1069 #define SATA_PORTMODE_PORT1 3
1072 * @section SataPortMd2
1073 * @li <b>0</b> - Disable
1074 * @li <b>1</b> - Enable
1076 #define SATA_PORTMODE_PORT2 3
1079 * @section SataPortMd3
1080 * @li <b>0</b> - Disable
1081 * @li <b>1</b> - Enable
1083 #define SATA_PORTMODE_PORT3 3
1086 * @section SataPortMd4
1087 * @li <b>0</b> - Disable
1088 * @li <b>1</b> - Enable
1090 #define SATA_PORTMODE_PORT4 0
1093 * @section SataPortMd5
1094 * @li <b>0</b> - Disable
1095 * @li <b>1</b> - Enable
1097 #define SATA_PORTMODE_PORT5 0
1100 * @section SataPortMd6
1101 * @li <b>0</b> - Disable
1102 * @li <b>1</b> - Enable
1104 #define SATA_PORTMODE_PORT6 0
1107 * @section SataPortMd7
1108 * @li <b>0</b> - Disable
1109 * @li <b>1</b> - Enable
1111 #define SATA_PORTMODE_PORT7 0
1114 * @section SataHotRemovelEnh0
1115 * @li <b>0</b> - Disable
1116 * @li <b>1</b> - Enable
1118 #define SATA_HOTREMOVEL_ENH_PORT0 0
1121 * @section SataHotRemovelEnh1
1122 * @li <b>0</b> - Disable
1123 * @li <b>1</b> - Enable
1125 #define SATA_HOTREMOVEL_ENH_PORT1 0
1128 * @section SataHotRemovelEnh2
1129 * @li <b>0</b> - Disable
1130 * @li <b>1</b> - Enable
1132 #define SATA_HOTREMOVEL_ENH_PORT2 0
1135 * @section SataHotRemovelEnh3
1136 * @li <b>0</b> - Disable
1137 * @li <b>1</b> - Enable
1139 #define SATA_HOTREMOVEL_ENH_PORT3 0
1142 * @section SataHotRemovelEnh4
1143 * @li <b>0</b> - Disable
1144 * @li <b>1</b> - Enable
1146 #define SATA_HOTREMOVEL_ENH_PORT4 0
1149 * @section SataHotRemovelEnh5
1150 * @li <b>0</b> - Disable
1151 * @li <b>1</b> - Enable
1153 #define SATA_HOTREMOVEL_ENH_PORT5 0
1156 * @section SataHotRemovelEnh6
1157 * @li <b>0</b> - Disable
1158 * @li <b>1</b> - Enable
1160 #define SATA_HOTREMOVEL_ENH_PORT6 0
1163 * @section SataHotRemovelEnh7
1164 * @li <b>0</b> - Disable
1165 * @li <b>1</b> - Enable
1167 #define SATA_HOTREMOVEL_ENH_PORT7 0
1170 * @section XhciSwitch
1171 * @li <b>0</b> - Disable
1172 * @li <b>1</b> - Enable
1174 #if CONFIG_ONBOARD_USB30 == 1
1175 #define SB_XHCI_SWITCH 0
1177 #define SB_XHCI_SWITCH 1
1181 * @section FrontPanelDetected
1182 * @li <b>0</b> - Disable
1183 * @li <b>1</b> - Enable
1185 #define INCHIP_FRONT_PANEL_DETECTED 0
1188 * @section AnyHT200MhzLink
1189 * @li <b>0</b> - Disable
1190 * @li <b>1</b> - Enable
1192 #define INCHIP_ANY_HT_200MHZ_LINK 0
1195 * @section PcibClkStopOverride
1196 * @li <b>0</b> - Disable
1197 * @li <b>1</b> - Enable
1199 #define INCHIP_PCIB_CLK_STOP_OVERRIDE 0
1202 * @section GppLinkConfig
1203 * @li <b>0000</b> - Port ABCD -> 4:0:0:0
1204 * @li <b>0001</b> - N/A
1205 * @li <b>0010</b> - Port ABCD -> 2:2:0:0
1206 * @li <b>0011</b> - Port ABCD -> 2:1:1:0
1207 * @li <b>0100</b> - Port ABCD -> 1:1:1:1
1209 #define INCHIP_GPP_LINK_CONFIG 4
1212 * @section GppUnhidePorts
1213 * @li <b>0</b> - Disable
1214 * @li <b>1</b> - Enable
1216 #define INCHIP_GPP_UNHIDE_PORTS 0
1219 * @section GppPortAspm
1220 * @li <b>01</b> - Disabled
1221 * @li <b>01</b> - L0s
1222 * @li <b>10</b> - L1
1223 * @li <b>11</b> - L0s + L1
1225 #define INCHIP_GPP_PORT_ASPM 3
1228 * @section GppLaneReversal
1229 * @li <b>0</b> - Disable
1230 * @li <b>1</b> - Enable
1232 #define INCHIP_GPP_LANEREVERSAL 0
1235 * @section AlinkPhyPllPowerDown
1236 * @li <b>0</b> - Disable
1237 * @li <b>1</b> - Enable
1239 #define INCHIP_ALINK_PHY_PLL_POWER_DOWN 1
1242 * @section GppPhyPllPowerDown
1243 * @li <b>0</b> - Disable
1244 * @li <b>1</b> - Enable
1246 #define INCHIP_GPP_PHY_PLL_POWER_DOWN 1
1249 * @section GppDynamicPowerSaving
1250 * @li <b>0</b> - Disable
1251 * @li <b>1</b> - Enable
1253 #define INCHIP_GPP_DYNAMIC_POWER_SAVING 1
1257 * @li <b>0</b> - Disable
1258 * @li <b>1</b> - Enable
1260 #define INCHIP_PCIE_AER 0
1264 * @li <b>0</b> - Disable
1265 * @li <b>1</b> - Enable
1267 #define INCHIP_PCIE_RAS 0
1270 * @section GppHardwareDowngrade
1271 * @li <b>0</b> - Disable
1272 * @li <b>1</b> - Enable
1274 #define INCHIP_GPP_HARDWARE_DOWNGRADE 0
1277 * @section GppToggleReset
1278 * @li <b>0</b> - Disable
1279 * @li <b>1</b> - Enable
1281 #define INCHIP_GPP_TOGGLE_RESET 0
1284 * @section SbPcieOrderRule
1285 * @li <b>00</b> - Disable
1286 * @li <b>01</b> - Rule 1
1287 * @li <b>10</b> - Rule 2
1289 #define INCHIP_SB_PCIE_ORDER_RULE 2
1293 * @li <b>0</b> - Disable
1294 * @li <b>1</b> - Enable
1296 #define INCHIP_ACDC_MSG 0
1299 * @section TimerTickTrack
1300 * @li <b>0</b> - Disable
1301 * @li <b>1</b> - Enable
1303 #define INCHIP_TIMER_TICK_TRACK 1
1306 * @section ClockInterruptTag
1307 * @li <b>0</b> - Disable
1308 * @li <b>1</b> - Enable
1310 #define INCHIP_CLOCK_INTERRUPT_TAG 1
1313 * @section OhciTrafficHanding
1314 * @li <b>0</b> - Disable
1315 * @li <b>1</b> - Enable
1317 #define INCHIP_OHCI_TRAFFIC_HANDING 0
1320 * @section EhciTrafficHanding
1321 * @li <b>0</b> - Disable
1322 * @li <b>1</b> - Enable
1324 #define INCHIP_EHCI_TRAFFIC_HANDING 0
1327 * @section FusionMsgCMultiCore
1328 * @li <b>0</b> - Disable
1329 * @li <b>1</b> - Enable
1331 #define INCHIP_FUSION_MSGC_MULTICORE 0
1334 * @section FusionMsgCStage
1335 * @li <b>0</b> - Disable
1336 * @li <b>1</b> - Enable
1338 #define INCHIP_FUSION_MSGC_STAGE 0
1341 * @section ALinkClkGateOff
1342 * @li <b>0</b> - Disable
1343 * @li <b>1</b> - Enable
1345 #define INCHIP_ALINK_CLK_GATE_OFF 0
1348 * @section BLinkClkGateOff
1349 * @li <b>0</b> - Disable
1350 * @li <b>1</b> - Enable
1352 #define INCHIP_BLINK_CLK_GATE_OFF 0
1355 * @section SlowSpeedABlinkClock
1356 * @li <b>0</b> - Disable
1357 * @li <b>1</b> - Enable
1359 #define INCHIP_SLOW_SPEED_ABLINK_CLOCK 0
1362 * @section AbClockGating
1363 * @li <b>0</b> - Disable
1364 * @li <b>1</b> - Enable
1366 #define INCHIP_AB_CLOCK_GATING 1
1369 * @section GppClockGating
1370 * @li <b>0</b> - Disable
1371 * @li <b>1</b> - Enable
1373 #define INCHIP_GPP_CLOCK_GATING 1
1376 * @section L1TimerOverwrite
1377 * @li <b>0</b> - Disable
1378 * @li <b>1</b> - Enable
1380 #define INCHIP_L1_TIMER_OVERWRITE 0
1383 * @section UmiDynamicSpeedChange
1384 * @li <b>0</b> - Disable
1385 * @li <b>1</b> - Enable
1387 #define INCHIP_UMI_DYNAMIC_SPEED_CHANGE 0
1390 * @section SbAlinkGppTxDriverStrength
1391 * @li <b>0</b> - Disable
1392 * @li <b>1</b> - Enable
1394 #define INCHIP_ALINK_GPP_TX_DRV_STRENGTH 0
1397 * @section StressResetMode
1398 * @li <b>0</b> - Disable
1399 * @li <b>1</b> - Enable
1401 #define INCHIP_STRESS_RESET_MODE 0
1403 #ifndef SB_PCI_CLOCK_RESERVED
1404 #define SB_PCI_CLOCK_RESERVED 0x0 //according to CIMx change 0x1F
1408 * @brief South Bridge CIMx configuration
1411 void sb900_cimx_config(AMDSBCFG *sb_cfg);
1412 void SbPowerOnInit_Config(AMDSBCFG *sb_cfg);
1415 * @brief Entry point of Southbridge CIMx callout
1417 * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
1419 * @param[in] func Southbridge CIMx Function ID.
1420 * @param[in] data Southbridge Input Data.
1421 * @param[in] sb_cfg Southbridge configuration structure pointer.
1424 u32 sb900_callout_entry(u32 func, u32 data, void* sb_cfg);