2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2006 MSI
7 * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
8 * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #define RAMINIT_SYSINFO 1
27 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
29 unsigned int get_sbdn(unsigned bus);
31 /* Used by raminit. */
32 #define QRANK_DIMM_SUPPORT 1
34 /* Used by init_cpus and fidvid */
35 #define K8_SET_FIDVID 1
37 /* If we want to wait for core1 done before DQS training, set it to 0. */
38 #define K8_SET_FIDVID_CORE0_ONLY 1
40 #if CONFIG_K8_REV_F_SUPPORT == 1
41 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
46 #include <device/pci_def.h>
48 #include <device/pnp_def.h>
49 #include <arch/romcc_io.h>
50 #include <cpu/amd/mtrr.h>
51 #include <cpu/x86/lapic.h>
52 #include "option_table.h"
53 #include "pc80/mc146818rtc_early.c"
54 #include "pc80/serial.c"
55 #include "console/console.c"
56 #include <cpu/amd/model_fxx_rev.h>
57 #include "northbridge/amd/amdk8/raminit.h"
58 #include "cpu/amd/model_fxx/apic_timer.c"
59 #include "lib/delay.c"
60 #include "cpu/x86/lapic/boot_cpu.c"
61 #include "northbridge/amd/amdk8/reset_test.c"
62 #include "northbridge/amd/amdk8/debug.c"
63 #include "northbridge/amd/amdk8/early_ht.c"
64 #include "superio/ite/it8712f/it8712f_early_serial.c"
65 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
66 #include "cpu/amd/mtrr/amd_earlymtrr.c"
67 #include "cpu/x86/bist.h"
68 #include "northbridge/amd/amdk8/setup_resource_map.c"
70 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
71 #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
73 static void memreset_setup(void)
77 static void memreset(int controllers, const struct mem_controller *ctrl)
81 static inline int spd_read_byte(unsigned device, unsigned address)
83 return smbus_read_byte(device, address);
86 void activate_spd_rom(const struct mem_controller *ctrl)
90 #define K8_4RANK_DIMM_SUPPORT 1
92 #include "southbridge/via/k8t890/k8t890_early_car.c"
93 #include "northbridge/amd/amdk8/amdk8.h"
94 #include "northbridge/amd/amdk8/raminit_f.c"
95 #include "northbridge/amd/amdk8/coherent_ht.c"
96 #include "northbridge/amd/amdk8/incoherent_ht.c"
97 #include "lib/generic_sdram.c"
98 #include "cpu/amd/dualcore/dualcore.c"
99 #include "cpu/amd/car/copy_and_run.c"
100 #include "cpu/amd/car/post_cache_as_ram.c"
101 #include "cpu/amd/model_fxx/init_cpus.c"
105 /* this function might fail on some K8 CPUs with errata #181 */
106 static void ldtstop_sb(void)
108 print_debug("toggle LDTSTP#\r\n");
109 u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c);
110 reg = reg ^ (1 << 0);
111 outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
112 reg = inb(VT8237R_ACPI_IO_BASE + 0x15);
113 print_debug("done\r\n");
116 #include "cpu/amd/model_fxx/fidvid.c"
117 #include "northbridge/amd/amdk8/resourcemap.c"
119 #warning No hard_reset implemented for this board!
120 void hard_reset(void)
122 print_info("NO HARD RESET. FIX ME!\n");
125 void soft_reset(void)
130 print_debug("soft reset \r\n");
133 tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
135 /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
136 pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
139 /* daisy daisy ... */
144 unsigned int get_sbdn(unsigned bus)
148 dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
149 PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
150 return (dev >> 15) & 0x1f;
158 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
160 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
162 real_main(bist, cpu_init_detectedx);
165 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
168 static const uint16_t spd_addr[] = {
169 (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
170 (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
171 #if CONFIG_MAX_PHYSICAL_CPUS > 1
172 (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
173 (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
176 unsigned bsp_apicid = 0;
178 struct sys_info *sysinfo =
179 (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
184 it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
185 it8712f_kill_watchdog();
186 it8712f_enable_3vsbsw();
191 print_info("now booting... real_main\r\n");
194 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
196 /* Halt if there was a built in self test failure. */
197 report_bist_failure(bist);
198 setup_default_resource_map();
199 setup_coherent_ht_domain();
200 wait_all_core0_started();
202 print_info("now booting... Core0 started\r\n");
204 #if CONFIG_LOGICAL_CPUS==1
205 /* It is said that we should start core1 after all core0 launched. */
207 wait_all_other_cores_started(bsp_apicid);
210 ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
212 needs_reset = optimize_link_coherent_ht();
213 print_debug_hex8(needs_reset);
214 needs_reset |= optimize_link_incoherent_ht(sysinfo);
215 print_debug_hex8(needs_reset);
216 needs_reset |= k8t890_early_setup_ht();
217 print_debug_hex8(needs_reset);
219 vt8237_early_network_init(NULL);
220 vt8237_early_spi_init();
223 print_debug_hex8(needs_reset);
225 print_debug("Xht reset -\r\n");
227 print_debug("NO reset\r\n");
231 /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
232 /* allow LDT STOP asserts */
233 vt8237_sb_enable_fid_vid();
236 print_debug("after enable_fid_change\r\n");
238 init_fidvid_bsp(bsp_apicid);
240 /* Stop the APs so we can start them later in init. */
241 allow_all_aps_stop(bsp_apicid);
243 /* It's the time to set ctrl now. */
244 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
247 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);