src/mainboard/arima/hdama/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include "lib/ramtest.c"
  11
  12 #include <cpu/amd/model_fxx_rev.h>
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18
  19 #include "cpu/x86/lapic/boot_cpu.c"
  20 #include "northbridge/amd/amdk8/reset_test.c"
  21 #include "northbridge/amd/amdk8/debug.c"
  22 #include "superio/nsc/pc87360/pc87360_early_serial.c"
  23
  24 #include "cpu/x86/mtrr/earlymtrr.c"
  25 #include "cpu/x86/bist.h"
  26
  27 #include "northbridge/amd/amdk8/setup_resource_map.c"
  28
  29 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
  30
  31 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  32
  33 /*
  34  * GPIO28 of 8111 will control H0_MEMRESET_L
  35  * GPIO29 of 8111 will control H1_MEMRESET_L
  36  */
  37 static void memreset_setup(void)
  38 {
  39         if (is_cpu_pre_c0()) {
  40                 /* Set the memreset low */
  41                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  42                 /* Ensure the BIOS has control of the memory lines */
  43                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  44         }
  45         else {
  46                 /* Ensure the CPU has controll of the memory lines */
  47                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  48         }
  49 }
  50
  51 static void memreset(int controllers, const struct mem_controller *ctrl)
  52 {
  53         if (is_cpu_pre_c0()) {
  54                 udelay(800);
  55                 /* Set memreset_high */
  56                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  57                 udelay(90);
  58         }
  59 }
  60
  61 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  62 {
  63         /* nothing to do */
  64 }
  65
  66 static inline int spd_read_byte(unsigned device, unsigned address)
  67 {
  68         return smbus_read_byte(device, address);
  69 }
  70
  71 #define QRANK_DIMM_SUPPORT 1
  72
  73 #include "northbridge/amd/amdk8/raminit.c"
  74 #include "northbridge/amd/amdk8/resourcemap.c"
  75 #include "northbridge/amd/amdk8/coherent_ht.c"
  76 #include "lib/generic_sdram.c"
  77
  78 #if CONFIG_LOGICAL_CPUS==1
  79 #define SET_NB_CFG_54 1
  80 #endif
  81 #include "cpu/amd/dualcore/dualcore.c"
  82
  83 #define FIRST_CPU  1
  84 #define SECOND_CPU 1
  85 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  86
  87
  88
  89 #include "cpu/amd/car/post_cache_as_ram.c"
  90
  91 #include "cpu/amd/model_fxx/init_cpus.c"
  92
  93 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  94 #include "northbridge/amd/amdk8/early_ht.c"
  95
  96 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  97 {
  98         static const uint16_t spd_addr [] = {
  99                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 100                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 101 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 102                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 103                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 104 #endif
 105         };
 106
 107         int needs_reset;
 108         unsigned bsp_apicid = 0;
 109         struct mem_controller ctrl[8];
 110         unsigned nodes;
 111
 112         if (!cpu_init_detectedx && boot_cpu()) {
 113                 /* Nothing special needs to be done to find bus 0 */
 114                 /* Allow the HT devices to be found */
 115
 116                 enumerate_ht_chain();
 117
 118                 amd8111_enable_rom();
 119         }
 120
 121         if (bist == 0) {
 122                 bsp_apicid = init_cpus(cpu_init_detectedx);
 123         }
 124
 125         pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 126         uart_init();
 127         console_init();
 128
 129         /* Halt if there was a built in self test failure */
 130         report_bist_failure(bist);
 131
 132         setup_default_resource_map();
 133
 134         needs_reset = setup_coherent_ht_domain();
 135
 136 #if CONFIG_LOGICAL_CPUS==1
 137         // It is said that we should start core1 after all core0 launched
 138         start_other_cores();
 139         wait_all_other_cores_started(bsp_apicid);
 140 #endif
 141         /* This is needed to be able to call udelay().  It could be moved to
 142          * memreset_setup, since udelay is called in memreset. */
 143         init_timer();
 144
 145         // automatically set that for you, but you might meet tight space
 146         needs_reset |= ht_setup_chains_x();
 147
 148         if (needs_reset) {
 149                 print_info("ht reset -\n");
 150                 soft_reset();
 151         }
 152
 153         allow_all_aps_stop(bsp_apicid);
 154
 155         nodes = get_nodes();
 156
 157         fill_mem_ctrl(nodes, ctrl, spd_addr);
 158
 159         enable_smbus();
 160
 161         memreset_setup();
 162
 163         sdram_initialize(nodes, ctrl);
 164
 165         post_cache_as_ram();
 166 }
 167