src/mainboard/arima/hdama/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include "option_table.h"
   9 #include "pc80/mc146818rtc_early.c"
  10 #include <console/console.h>
  11 #include "lib/ramtest.c"
  12
  13 #include <cpu/amd/model_fxx_rev.h>
  14 #include "northbridge/amd/amdk8/incoherent_ht.c"
  15 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/amd/model_fxx/apic_timer.c"
  18 #include "lib/delay.c"
  19
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include "superio/nsc/pc87360/pc87360_early_serial.c"
  24
  25 #include "cpu/x86/mtrr/earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #include "northbridge/amd/amdk8/setup_resource_map.c"
  29
  30 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
  31
  32 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  33
  34 /*
  35  * GPIO28 of 8111 will control H0_MEMRESET_L
  36  * GPIO29 of 8111 will control H1_MEMRESET_L
  37  */
  38 static void memreset_setup(void)
  39 {
  40         if (is_cpu_pre_c0()) {
  41                 /* Set the memreset low */
  42                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  43                 /* Ensure the BIOS has control of the memory lines */
  44                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  45         }
  46         else {
  47                 /* Ensure the CPU has controll of the memory lines */
  48                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  49         }
  50 }
  51
  52 static void memreset(int controllers, const struct mem_controller *ctrl)
  53 {
  54         if (is_cpu_pre_c0()) {
  55                 udelay(800);
  56                 /* Set memreset_high */
  57                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  58                 udelay(90);
  59         }
  60 }
  61
  62 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  63 {
  64         /* nothing to do */
  65 }
  66
  67 static inline int spd_read_byte(unsigned device, unsigned address)
  68 {
  69         return smbus_read_byte(device, address);
  70 }
  71
  72 #define QRANK_DIMM_SUPPORT 1
  73
  74 #include "northbridge/amd/amdk8/raminit.c"
  75 #include "northbridge/amd/amdk8/resourcemap.c"
  76 #include "northbridge/amd/amdk8/coherent_ht.c"
  77 #include "lib/generic_sdram.c"
  78
  79 #if CONFIG_LOGICAL_CPUS==1
  80 #define SET_NB_CFG_54 1
  81 #endif
  82 #include "cpu/amd/dualcore/dualcore.c"
  83
  84 #define FIRST_CPU  1
  85 #define SECOND_CPU 1
  86 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  87
  88
  89
  90 #include "cpu/amd/car/post_cache_as_ram.c"
  91
  92 #include "cpu/amd/model_fxx/init_cpus.c"
  93
  94 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  95 #include "northbridge/amd/amdk8/early_ht.c"
  96
  97 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  98 {
  99         static const uint16_t spd_addr [] = {
 100                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 101                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 102 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 103                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 104                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 105 #endif
 106         };
 107
 108         int needs_reset;
 109         unsigned bsp_apicid = 0;
 110         struct mem_controller ctrl[8];
 111         unsigned nodes;
 112
 113         if (!cpu_init_detectedx && boot_cpu()) {
 114                 /* Nothing special needs to be done to find bus 0 */
 115                 /* Allow the HT devices to be found */
 116
 117                 enumerate_ht_chain();
 118
 119                 amd8111_enable_rom();
 120         }
 121
 122         if (bist == 0) {
 123                 bsp_apicid = init_cpus(cpu_init_detectedx);
 124         }
 125
 126         pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 127         uart_init();
 128         console_init();
 129
 130         /* Halt if there was a built in self test failure */
 131         report_bist_failure(bist);
 132
 133         setup_default_resource_map();
 134
 135         needs_reset = setup_coherent_ht_domain();
 136
 137 #if CONFIG_LOGICAL_CPUS==1
 138         // It is said that we should start core1 after all core0 launched
 139         start_other_cores();
 140         wait_all_other_cores_started(bsp_apicid);
 141 #endif
 142         /* This is needed to be able to call udelay().  It could be moved to
 143          * memreset_setup, since udelay is called in memreset. */
 144         init_timer();
 145
 146         // automatically set that for you, but you might meet tight space
 147         needs_reset |= ht_setup_chains_x();
 148
 149         if (needs_reset) {
 150                 print_info("ht reset -\n");
 151                 soft_reset();
 152         }
 153
 154         allow_all_aps_stop(bsp_apicid);
 155
 156         nodes = get_nodes();
 157
 158         fill_mem_ctrl(nodes, ctrl, spd_addr);
 159
 160         enable_smbus();
 161
 162         memreset_setup();
 163
 164         sdram_initialize(nodes, ctrl);
 165
 166         post_cache_as_ram();
 167 }
 168