1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
7 void *smp_write_config_table(void *v, unsigned long * processor_map)
9 static const char sig[4] = "PCMP";
10 static const char oem[8] = "LNXI ";
11 static const char productid[12] = "HDAMA ";
12 struct mp_config_table *mc;
13 unsigned char bus_num;
14 unsigned char bus_isa;
15 unsigned char bus_8131_1;
16 unsigned char bus_8131_2;
17 unsigned char bus_8111_1;
19 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
20 memset(mc, 0, sizeof(*mc));
22 memcpy(mc->mpc_signature, sig, sizeof(sig));
23 mc->mpc_length = sizeof(*mc); /* initially just the header */
25 mc->mpc_checksum = 0; /* not yet computed */
26 memcpy(mc->mpc_oem, oem, sizeof(oem));
27 memcpy(mc->mpc_productid, productid, sizeof(productid));
30 mc->mpc_entry_count = 0; /* No entries yet... */
31 mc->mpc_lapic = LAPIC_ADDR;
36 smp_write_processors(mc, processor_map);
42 dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
44 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
45 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
48 printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
54 dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
56 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
58 printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
62 dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
64 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
66 printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
72 /* define bus and isa numbers */
73 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
74 smp_write_bus(mc, bus_num, "PCI ");
76 smp_write_bus(mc, bus_isa, "ISA ");
79 smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
84 dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
86 base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
87 base &= PCI_BASE_ADDRESS_MEM_MASK;
88 smp_write_ioapic(mc, 0x03, 0x11, base);
91 dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
93 base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
94 base &= PCI_BASE_ADDRESS_MEM_MASK;
95 smp_write_ioapic(mc, 0x04, 0x11, base);
99 /* ISA backward compatibility interrupts */
100 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
101 bus_isa, 0x00, 0x02, 0x00);
102 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
103 bus_isa, 0x01, 0x02, 0x01);
104 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
105 bus_isa, 0x00, 0x02, 0x02);
106 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
107 bus_isa, 0x03, 0x02, 0x03);
108 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
109 bus_isa, 0x04, 0x02, 0x04);
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
111 bus_isa, 0x05, 0x02, 0x05);
112 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
113 bus_isa, 0x06, 0x02, 0x06);
114 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
115 bus_isa, 0x07, 0x02, 0x07);
116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
117 bus_isa, 0x08, 0x02, 0x08);
118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
119 bus_isa, 0x09, 0x02, 0x09);
120 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
121 bus_isa, 0x0a, 0x02, 0x0a);
122 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
123 bus_isa, 0x0b, 0x02, 0x0b);
124 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
125 bus_isa, 0x0c, 0x02, 0x0c);
126 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
127 bus_isa, 0x0d, 0x02, 0x0d);
128 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
129 bus_isa, 0x0e, 0x02, 0x0e);
130 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
131 bus_isa, 0x0f, 0x02, 0x0f);
133 /* Standard local interrupt assignments */
134 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
135 bus_isa, 0x00, MP_APIC_ALL, 0x00);
136 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
137 bus_isa, 0x00, MP_APIC_ALL, 0x01);
139 /* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
141 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x03<<2)|0, 0x02, 0x13);
142 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x04<<2)|0, 0x02, 0x13);
145 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|0, 0x02, 0x11);
146 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|1, 0x02, 0x12);
147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|2, 0x02, 0x13);
148 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|3, 0x02, 0x10);
151 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|0, 0x02, 0x12);
152 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|1, 0x02, 0x13);
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|2, 0x02, 0x10);
154 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|3, 0x02, 0x11);
157 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x02, 0x11);
158 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x02, 0x12);
159 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|2, 0x02, 0x13);
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|3, 0x02, 0x10);
163 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|0, 0x02, 0x12);
164 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|1, 0x02, 0x13);
165 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|2, 0x02, 0x10);
166 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|3, 0x02, 0x11);
169 #warning "FIXME get the irqs right, it's just hacked to work for now"
170 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
171 bus_8111_1, (5<<2)|0, 0x02, 0x11);
172 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
173 bus_8111_1, (5<<2)|1, 0x02, 0x12);
174 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
175 bus_8111_1, (5<<2)|2, 0x02, 0x13);
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
177 bus_8111_1, (5<<2)|3, 0x02, 0x10);
180 #warning "FIXME get the irqs right, it's just hacked to work for now"
181 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
182 bus_8111_1, (4<<2)|0, 0x02, 0x10);
183 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
184 bus_8111_1, (4<<2)|1, 0x02, 0x11);
185 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
186 bus_8111_1, (4<<2)|2, 0x02, 0x12);
187 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
188 bus_8111_1, (4<<2)|3, 0x02, 0x13);
190 /* There is no extension information... */
192 /* Compute the checksums */
193 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
194 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
195 printk_debug("Wrote the mp table end at: %p - %p\n",
196 mc, smp_next_mpe_entry(mc));
197 return smp_next_mpe_entry(mc);
200 unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
203 v = smp_write_floating_table(addr);
204 return (unsigned long)smp_write_config_table(v, processor_map);