Union Station: Remove SIO support
[coreboot.git] / src / mainboard / amd / union_station / romstage.c
1 /*
2  * This file is part of the coreboot project.
3  *
4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
18  */
19
20 #include <lib.h>
21 #include <stdint.h>
22 #include <string.h>
23 #include <device/pci_def.h>
24 #include <device/pci_ids.h>
25 #include <arch/io.h>
26 #include <arch/stages.h>
27 #include <device/pnp_def.h>
28 #include <arch/romcc_io.h>
29 #include <arch/cpu.h>
30 #include <cpu/x86/lapic.h>
31 #include <console/console.h>
32 #include <console/loglevel.h>
33 #include "agesawrapper.h"
34 #include "cpu/x86/bist.h"
35 #include "cpu/x86/lapic/boot_cpu.c"
36 #include "sb_cimx.h"
37 #include "SBPLATFORM.h"
38
39 #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
40
41 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
42 {
43         u32 val;
44
45         /*
46          * All cores: allow caching of flash chip code and data
47          * (there are no cache-as-ram reliability concerns with family 14h)
48          */
49         __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
50         __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
51
52         if (!cpu_init_detectedx && boot_cpu()) {
53                 post_code(0x30);
54                 sb_Poweron_Init();
55
56                 post_code(0x31);
57                 console_init();
58         }
59
60         /* Halt if there was a built in self test failure */
61         post_code(0x34);
62         report_bist_failure(bist);
63
64         /* Load MPB */
65         val = cpuid_eax(1);
66         printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
67         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
68
69         post_code(0x35);
70         printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
71         val = agesawrapper_amdinitmmio();
72         if (val)
73                 printk(BIOS_DEBUG, "error level: %x \n", val);
74         else
75                 printk(BIOS_DEBUG, "passed.\n");
76
77         post_code(0x37);
78         printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
79         val = agesawrapper_amdinitreset();
80         if (val)
81                 printk(BIOS_DEBUG, "error level: %x \n", val);
82         else
83                 printk(BIOS_DEBUG, "passed.\n");
84
85         post_code(0x39);
86         printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
87         val = agesawrapper_amdinitearly ();
88         if (val)
89                 printk(BIOS_DEBUG, "error level: %x \n", val);
90         else
91                 printk(BIOS_DEBUG, "passed.\n");
92
93         post_code(0x40);
94         printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
95         val = agesawrapper_amdinitpost ();
96         if (val)
97                 printk(BIOS_DEBUG, "error level: %x \n", val);
98         else
99                 printk(BIOS_DEBUG, "passed.\n");
100
101         post_code(0x41);
102         printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
103         val = agesawrapper_amdinitenv ();
104         if (val)
105                 printk(BIOS_DEBUG, "error level: %x \n", val);
106         else
107                 printk(BIOS_DEBUG, "passed.\n");
108
109         post_code(0x50);
110         copy_and_run(0);
111         printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
112
113         post_code(0x54);  /* Should never see this post code. */
114 }
115