2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #define SYSTEM_TYPE 0 /* SERVER */
21 //#define SYSTEM_TYPE 1 /* DESKTOP */
22 //#define SYSTEM_TYPE 2 /* MOBILE */
24 #define RAMINIT_SYSINFO 1
25 #define CACHE_AS_RAM_ADDRESS_DEBUG 1
27 #define SET_NB_CFG_54 1
30 #define QRANK_DIMM_SUPPORT 1
32 //used by incoherent_ht
33 #define FAM10_SCAN_PCI_BUS 0
34 #define FAM10_ALLOCATE_IO_RANGE 0
36 //used by init_cpus and fidvid
38 #define SET_FIDVID_CORE_RANGE 0
42 #include <device/pci_def.h>
43 #include <device/pci_ids.h>
45 #include <device/pnp_def.h>
46 #include <arch/romcc_io.h>
47 #include <cpu/x86/lapic.h>
48 #include <console/console.h>
49 #include "lib/ramtest.c"
50 #include <cpu/amd/model_10xxx_rev.h>
51 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
52 #include "northbridge/amd/amdfam10/raminit.h"
53 #include "northbridge/amd/amdfam10/amdfam10.h"
55 #include "cpu/x86/lapic/boot_cpu.c"
56 #include "northbridge/amd/amdfam10/reset_test.c"
58 #include <console/loglevel.h>
60 void die(const char *msg);
61 int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
62 #define printk(BIOS_EMERG, fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg)
64 #include "cpu/x86/bist.h"
66 #include "northbridge/amd/amdfam10/debug.c"
67 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
68 #include "cpu/x86/mtrr/earlymtrr.c"
69 #include "northbridge/amd/amdfam10/setup_resource_map.c"
71 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
72 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
74 static void memreset_setup(void)
76 //GPIO on amd8111 to enable MEMRST ????
77 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN=1
78 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
81 static void activate_spd_rom(const struct mem_controller *ctrl)
83 #define SMBUS_HUB 0x18
85 u8 device = ctrl->spd_switch_addr;
87 printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x \n", device, ctrl->node_id);
89 /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
92 ret = smbus_write_byte(SMBUS_HUB, 0x01, (1<<(device & 0x7)));
93 } while ((ret!=0) && (i-->0));
94 smbus_write_byte(SMBUS_HUB, 0x03, 0);
97 static int spd_read_byte(u32 device, u32 address)
100 result = smbus_read_byte(device, address);
104 #include "northbridge/amd/amdfam10/amdfam10.h"
106 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
107 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
109 #include "resourcemap.c"
110 #include "cpu/amd/quadcore/quadcore.c"
112 #include "cpu/amd/car/post_cache_as_ram.c"
113 #include "cpu/amd/microcode/microcode.c"
114 #include "cpu/amd/model_10xxx/update_microcode.c"
115 #include "cpu/amd/model_10xxx/init_cpus.c"
117 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
118 #include "northbridge/amd/amdfam10/early_ht.c"
120 #include "spd_addr.h"
122 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
125 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
130 if (!cpu_init_detectedx && boot_cpu()) {
131 /* Nothing special needs to be done to find bus 0 */
132 /* Allow the HT devices to be found */
133 /* mov bsp to bus 0xff when > 8 nodes */
134 set_bsp_node_CHtExtNodeCfgEn();
135 enumerate_ht_chain();
137 /* Setup the rom access for 4M */
138 amd8111_enable_rom();
144 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
145 /* All cores run this but the BSP(node0,core0) is the only core that returns. */
150 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
153 printk(BIOS_DEBUG, "\n");
155 // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
157 /* Halt if there was a built in self test failure */
158 report_bist_failure(bist);
162 printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
163 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
164 printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
165 printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
167 /* Setup sysinfo defaults */
168 set_sysinfo_in_ram(0);
170 update_microcode(val);
176 amd_ht_init(sysinfo);
179 /* Setup nodes PCI space and start core 0 AP init. */
180 finalize_node_setup(sysinfo);
182 /* Setup any mainboard PCI settings etc. */
183 setup_mb_resource_map();
186 /* wait for all the APs core0 started by finalize_node_setup. */
187 /* FIXME: A bunch of cores are going to start output to serial at once.
188 It would be nice to fixup prink spinlocks for ROM XIP mode.
189 I think it could be done by putting the spinlock flag in the cache
190 of the BSP located right after sysinfo.
192 wait_all_core0_started();
194 #if CONFIG_LOGICAL_CPUS==1
195 /* Core0 on each node is configured. Now setup any additional cores. */
196 printk(BIOS_DEBUG, "start_other_cores()\n");
199 wait_all_other_cores_started(bsp_apicid);
205 msr = rdmsr(0xc0010071);
206 printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
208 /* FIXME: The sb fid change may survive the warm reset and only
209 need to be done once.*/
210 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
214 if (!warm_reset_detect(0)) { // BSP is node 0
215 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
217 init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
222 /* show final fid and vid */
223 msr=rdmsr(0xc0010071);
224 printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
227 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
228 if (!warm_reset_detect(0)) {
229 print_info("...WARM RESET...\n\n\n");
230 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
231 die("After soft_reset_x - shouldn't see this message!!!\n");
236 /* FIXME: Move this to chipset init.
237 enable cf9 for hard reset */
238 print_debug("enable_cf9_x()\n");
239 enable_cf9_x(sysinfo->sbbusn, sysinfo->sbdn);
242 /* It's the time to set ctrl in sysinfo now; */
243 printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
244 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
247 printk(BIOS_DEBUG, "enable_smbus()\n");
254 // die("Die Before MCT init.");
256 printk(BIOS_DEBUG, "raminit_amdmct()\n");
257 raminit_amdmct(sysinfo);
261 dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
262 dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
263 dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
264 dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
267 // ram_check(0x00200000, 0x00200000 + (640 * 1024));
268 // ram_check(0x40200000, 0x40200000 + (640 * 1024));
270 // die("After MCT init before CAR disabled.");
273 printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
274 post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
275 post_code(0x43); // Should never see this post code.