Make fam10 build (but not boot due to bootblock size problems.)
[coreboot.git] / src / mainboard / amd / serengeti_cheetah_fam10 / Kconfig
1 config BOARD_AMD_SERENGETI_CHEETAH_FAM10
2         bool "Serengeti Cheetah (Fam10)"
3         select ARCH_X86
4         select CPU_AMD_FAM10
5         select CPU_AMD_SOCKET_F_1207
6         select NORTHBRIDGE_AMD_AMDFAM10
7         select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
8         select SOUTHBRIDGE_AMD_AMD8111
9         select SOUTHBRIDGE_AMD_AMD8132
10         select SUPERIO_WINBOND_W83627HF
11         select HAVE_PIRQ_TABLE
12         select USE_PRINTK_IN_CAR
13         select USE_DCACHE_RAM
14         select HAVE_HARD_RESET
15         select IOAPIC
16         select SB_HT_CHAIN_UNITID_OFFSET_ONLY
17         select SERIAL_CPU_INIT
18         select AMDMCT
19         select HAVE_ACPI_TABLES
20
21 config MAINBOARD_DIR
22         string
23         default amd/serengeti_cheetah_fam10
24         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
25
26 config APIC_ID_OFFSET
27         hex
28         default 0x0
29         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
30
31 config LB_CKS_RANGE_END
32         int
33         default 122
34         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
35
36 config LB_CKS_LOC
37         int
38         default 123
39         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
40
41 config MAINBOARD_PART_NUMBER
42         string
43         default "Serengeti-Cheetah-Fam10"
44         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
45
46 config HW_MEM_HOLE_SIZEK
47         hex
48         default 0x100000
49         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
50
51 # 6 * MAX_PHYSICAL_CPUS
52 config MAX_CPUS
53         int
54         default 48
55         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
56
57 config MAX_PHYSICAL_CPUS
58         int
59         default 8
60         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
61
62 config HW_MEM_HOLE_SIZE_AUTO_INC
63         bool
64         default n
65         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
66
67 config SB_HT_CHAIN_ON_BUS0
68         int
69         default 2
70         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
71
72 config HT_CHAIN_END_UNITID_BASE
73         hex
74         default 0x6
75         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
76
77 config HT_CHAIN_UNITID_BASE
78         hex
79         default 0xa
80         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
81
82 config USE_INIT
83         bool
84         default n
85         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
86
87 config IRQ_SLOT_COUNT
88         int
89         default 11
90         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
91
92 config AMD_UCODE_PATCH_FILE
93         string
94         default "mc_patch_01000095.h"
95         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
96
97 config LB_MEM_TOPK
98         hex
99         default 0x4000
100         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
101
102 config HEAP_SIZE
103         hex
104         default 0xc0000
105         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
106
107 config ACPI_SSDTX_NUM
108         int
109         default 31
110         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
111
112 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
113         hex
114         default 0x2b80
115         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
116
117 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
118         hex
119         default 0x1022
120         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
121
122 config ENABLE_APIC_EXT_ID
123         bool
124         default y
125         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
126
127 config LIFT_BSP_APIC_ID
128         bool
129         default y
130         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10