1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
7 #if CONFIG_LOGICAL_CPUS==1
8 #include <cpu/amd/multicore.h>
11 #include <cpu/amd/amdk8_sysconf.h>
12 #include "mb_sysconf.h"
16 static void *smp_write_config_table(void *v)
18 static const char sig[4] = "PCMP";
19 static const char oem[8] = "COREBOOT";
20 static const char productid[12] = "SERENGETI ";
21 struct mp_config_table *mc;
23 unsigned char bus_num;
25 struct mb_sysconf_t *m;
27 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
28 memset(mc, 0, sizeof(*mc));
30 memcpy(mc->mpc_signature, sig, sizeof(sig));
31 mc->mpc_length = sizeof(*mc); /* initially just the header */
33 mc->mpc_checksum = 0; /* not yet computed */
34 memcpy(mc->mpc_oem, oem, sizeof(oem));
35 memcpy(mc->mpc_productid, productid, sizeof(productid));
38 mc->mpc_entry_count = 0; /* No entries yet... */
39 mc->mpc_lapic = LAPIC_ADDR;
44 smp_write_processors(mc);
51 /* define bus and isa numbers */
52 for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
53 smp_write_bus(mc, bus_num, "PCI ");
55 smp_write_bus(mc, m->bus_isa, "ISA ");
57 /*I/O APICs: APIC ID Version State Address*/
58 smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
62 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
64 res = find_resource(dev, PCI_BASE_ADDRESS_0);
66 smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
69 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
71 res = find_resource(dev, PCI_BASE_ADDRESS_0);
73 smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
79 for(i=1; i< sysconf.hc_possible_num; i++) {
80 if(!(sysconf.pci1234[i] & 0x1) ) continue;
82 switch(sysconf.hcid[i]) {
85 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
87 res = find_resource(dev, PCI_BASE_ADDRESS_0);
89 smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
92 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
94 res = find_resource(dev, PCI_BASE_ADDRESS_0);
96 smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
106 mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_8111, 0);
108 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
127 //Slot 1 PCI-X 133/100/66
129 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); //
133 //Slot 2 PCI-X 133/100/66
135 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
140 for(i=1; i< sysconf.hc_possible_num; i++) {
141 if(!(sysconf.pci1234[i] & 0x1) ) continue;
144 struct resource *res;
145 switch(sysconf.hcid[i]) {
148 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
150 res = find_resource(dev, PCI_BASE_ADDRESS_0);
152 //Slot 1 PCI-X 133/100/66
153 for(ii=0;ii<4;ii++) {
154 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
159 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
161 res = find_resource(dev, PCI_BASE_ADDRESS_0);
163 //Slot 2 PCI-X 133/100/66
164 for(ii=0;ii<4;ii++) {
165 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
174 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
183 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
184 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
185 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
186 /* There is no extension information... */
188 /* Compute the checksums */
189 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
190 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
191 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
192 mc, smp_next_mpe_entry(mc));
193 return smp_next_mpe_entry(mc);
196 unsigned long write_smp_table(unsigned long addr)
199 v = smp_write_floating_table(addr);
200 return (unsigned long)smp_write_config_table(v);