2 ## Compute the location and size of where this firmware image
3 ## (coreboot plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FAILOVER_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
10 default ROM_SECTION_SIZE = FALLBACK_SIZE
11 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
13 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
14 default ROM_SECTION_OFFSET = 0
19 ## Compute the start location and size size of
20 ## The coreboot bootloader.
22 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
23 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
26 ## Compute where this copy of coreboot will start in the boot rom
28 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
31 ## Compute a range of ROM that can cached to speed up coreboot,
34 ## XIP_ROM_SIZE must be a power of 2.
35 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
37 default XIP_ROM_SIZE=65536
40 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
43 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
45 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
52 ## Build the objects we have code for in this directory.
59 #needed by irq_tables and mptable and acpi_tables
71 # object acpi_tables.o
73 # if SB_HT_CHAIN_ON_BUS0
80 # if SB_HT_CHAIN_ON_BUS0
92 depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
93 action "iasl -p $(PWD)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
94 action "mv dsdt_lb.hex dsdt.c"
98 #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
102 depends "$(MAINBOARD)/dx/pci2.asl"
103 action "iasl -p $(PWD)/pci2 -tc $(MAINBOARD)/dx/pci2.asl"
104 action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
105 action "mv pci2.hex ssdt2.c"
109 depends "$(MAINBOARD)/dx/pci3.asl"
110 action "iasl -p $(PWD)/pci3 -tc $(MAINBOARD)/dx/pci3.asl"
111 action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
112 action "mv pci3.hex ssdt3.c"
116 depends "$(MAINBOARD)/dx/pci4.asl"
117 action "iasl -p $(PWD)/pci4 -tc $(MAINBOARD)/dx/pci4.asl"
118 action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
119 action "mv pci4.hex ssdt4.c"
128 # compile cache_as_ram.c to auto.o
129 makerule ./cache_as_ram_auto.o
130 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
131 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
135 #compile cache_as_ram.c to auto.inc
136 makerule ./cache_as_ram_auto.inc
137 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
138 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
139 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
140 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
145 if USE_FAILOVER_IMAGE
147 if CONFIG_AP_CODE_IN_CAR
148 makerule ./apc_auto.o
149 depends "$(MAINBOARD)/apc_auto.c option_table.h"
150 action "$(CC) -I$(TOP)/src -I. $(DISTRO_CFLAGS) $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
152 ldscript /arch/i386/init/ldscript_apc.lb
157 ## Build our 16 bit and 32 bit coreboot entry code
160 if HAVE_FAILOVER_BOOT
161 if USE_FAILOVER_IMAGE
162 mainboardinit cpu/x86/16bit/entry16.inc
163 ldscript /cpu/x86/16bit/entry16.lds
166 if USE_FALLBACK_IMAGE
167 mainboardinit cpu/x86/16bit/entry16.inc
168 ldscript /cpu/x86/16bit/entry16.lds
172 mainboardinit cpu/x86/32bit/entry32.inc
175 ldscript /cpu/x86/32bit/entry32.lds
179 ldscript /cpu/amd/car/cache_as_ram.lds
184 ## Build our reset vector (This is where coreboot is entered)
186 if HAVE_FAILOVER_BOOT
187 if USE_FAILOVER_IMAGE
188 mainboardinit cpu/x86/16bit/reset16.inc
189 ldscript /cpu/x86/16bit/reset16.lds
191 mainboardinit cpu/x86/32bit/reset32.inc
192 ldscript /cpu/x86/32bit/reset32.lds
195 if USE_FALLBACK_IMAGE
196 mainboardinit cpu/x86/16bit/reset16.inc
197 ldscript /cpu/x86/16bit/reset16.lds
199 mainboardinit cpu/x86/32bit/reset32.inc
200 ldscript /cpu/x86/32bit/reset32.lds
205 ## Include an id string (For safe flashing)
207 mainboardinit arch/i386/lib/id.inc
208 ldscript /arch/i386/lib/id.lds
212 ## Setup Cache-As-Ram
214 mainboardinit cpu/amd/car/cache_as_ram.inc
218 ### This is the early phase of coreboot startup
219 ### Things are delicate and we test to see if we should
220 ### failover to another image.
222 if HAVE_FAILOVER_BOOT
223 if USE_FAILOVER_IMAGE
225 ldscript /arch/i386/lib/failover_failover.lds
229 if USE_FALLBACK_IMAGE
231 ldscript /arch/i386/lib/failover.lds
237 ### O.k. We aren't just an intermediary anymore!
246 initobject cache_as_ram_auto.o
248 mainboardinit ./cache_as_ram_auto.inc
254 ## Include the secondary Configuration files
258 # sample config for amd/serengeti_cheetah
259 chip northbridge/amd/amdk8/root_complex
260 device apic_cluster 0 on
261 chip cpu/amd/socket_F
265 device pci_domain 0 on
266 chip northbridge/amd/amdk8
267 device pci 18.0 on # northbridge
268 # devices on link 0, link 0 == LDT 0
269 chip southbridge/amd/amd8132
270 # the on/off keyword is mandatory
271 device pci 0.0 on end
272 device pci 0.1 on end
273 device pci 1.0 on end
274 device pci 1.1 on end
276 chip southbridge/amd/amd8111
277 # this "device pci 0.0" is the parent the next one
280 device pci 0.0 on end
281 device pci 0.1 on end
282 device pci 0.2 off end
283 device pci 1.0 off end
286 chip superio/winbond/w83627hf
287 device pnp 2e.0 off # Floppy
292 device pnp 2e.1 off # Parallel Port
296 device pnp 2e.2 on # Com1
300 device pnp 2e.3 off # Com2
304 device pnp 2e.5 on # Keyboard
310 device pnp 2e.6 off # CIR
313 device pnp 2e.7 off # GAME_MIDI_GIPO1
318 device pnp 2e.8 off end # GPIO2
319 device pnp 2e.9 off end # GPIO3
320 device pnp 2e.a off end # ACPI
321 device pnp 2e.b on # HW Monitor
327 device pci 1.1 on end
328 device pci 1.2 on end
330 chip drivers/i2c/i2cmux # pca9556 smbus mux
331 device i2c 18 on #0 pca9516 1
332 chip drivers/generic/generic #dimm 0-0-0
335 chip drivers/generic/generic #dimm 0-0-1
338 chip drivers/generic/generic #dimm 0-1-0
341 chip drivers/generic/generic #dimm 0-1-1
345 device i2c 18 on #1 pca9516 2
346 chip drivers/generic/generic #dimm 1-0-0
349 chip drivers/generic/generic #dimm 1-0-1
352 chip drivers/generic/generic #dimm 1-1-0
355 chip drivers/generic/generic #dimm 1-1-1
358 chip drivers/generic/generic #dimm 1-2-0
361 chip drivers/generic/generic #dimm 1-2-1
364 chip drivers/generic/generic #dimm 1-3-0
367 chip drivers/generic/generic #dimm 1-3-1
373 device pci 1.5 off end
374 device pci 1.6 off end
375 register "ide0_enable" = "1"
376 register "ide1_enable" = "1"
378 end # device pci 18.0
380 device pci 18.0 on end
381 device pci 18.0 on end
382 device pci 18.1 on end
383 device pci 18.2 on end
384 device pci 18.3 on end
386 chip northbridge/amd/amdk8
387 device pci 19.0 on # northbridge
388 chip southbridge/amd/amd8151
389 # the on/off keyword is mandatory
390 device pci 0.0 on end
391 device pci 1.0 on end
393 end # device pci 19.0
395 device pci 19.0 on end
396 device pci 19.0 on end
397 device pci 19.1 on end
398 device pci 19.2 on end
399 device pci 19.3 on end
404 # chip drivers/generic/debug
405 # device pnp 0.0 off end # chip name
406 # device pnp 0.1 on end # pci_regs_all
407 # device pnp 0.2 off end # mem
408 # device pnp 0.3 off end # cpuid
409 # device pnp 0.4 off end # smbus_regs_all
410 # device pnp 0.5 off end # dual core msr
411 # device pnp 0.6 off end # cache size
412 # device pnp 0.7 off end # tsc