2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
24 #include <boot/coreboot_tables.h>
25 #include <cpu/x86/msr.h>
26 #include <cpu/amd/mtrr.h>
27 #include <device/pci_def.h>
28 #include <../southbridge/amd/sb600/sb600.h>
31 #define ADT7461_ADDRESS 0x4C
32 #define ARA_ADDRESS 0x0C /* Alert Response Address */
33 #define SMBUS_IO_BASE 0x1000
35 extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
36 extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
38 extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
39 uint64_t start, uint64_t size);
40 #define ADT7461_read_byte(address) \
41 do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
42 #define ARA_read_byte(address) \
43 do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
44 #define ADT7461_write_byte(address, val) \
45 do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
47 unsigned long uma_memory_start, uma_memory_size;
49 /********************************************************
50 * dbm690t uses a BCM5789 as on-board NIC.
51 * It has a pin named LOW_POWER to enable it into LOW POWER state.
52 * In order to run NIC, we should let it out of Low power state. This pin is
53 * controlled by sb600 GPM3.
54 * RRG4.2.3 GPM as GPIO
55 * GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
56 * I/O C50, C51, C52, PM I/O94, 95, 96.
57 * RRG4.2.3.1 GPM pins as Input
58 * RRG4.2.3.2 GPM pins as Output
59 ********************************************************/
60 static void enable_onboard_nic()
64 printk_info("enable_onboard_nic.\n");
66 /* set index register 0C50h to 13h (miscellaneous control) */
67 outb(0x13, 0xC50); /* CMIndex */
69 /* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
75 /* set GPM port 0C52h bit 3 to 0 to enable output for GPM3 */
80 /* set CM data register 0C51h bits [7:6] to 10b to set Output state control */
83 byte |= 0x80; /* 7:6=10 */
86 /* set GPM port 0C52h bit 3 to 0 to output 0 on GPM3 */
92 /********************************************************
93 * dbm690t uses SB600 GPIO9 to detect IDE_DMA66.
94 * IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
95 * get the cable type, 40 pin or 80 pin?
96 ********************************************************/
97 static void get_ide_dma66()
100 /*u32 sm_dev, ide_dev; */
101 device_t sm_dev, ide_dev;
104 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
107 pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,
108 sm_dev->path.u.pci.devfn, 0xA9);
109 byte |= (1 << 5); /* Set Gpio9 as input */
110 pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary,
111 sm_dev->path.u.pci.devfn, 0xA9, byte);
113 ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
115 pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary,
116 ide_dev->path.u.pci.devfn, 0x56);
118 if ((1 << 5) & pci_cf8_conf1.
119 read8(&pbus, sm_dev->bus->secondary, sm_dev->path.u.pci.devfn,
121 byte |= 2 << 0; /* mode 2 */
123 byte |= 5 << 0; /* mode 5 */
124 pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary,
125 ide_dev->path.u.pci.devfn, 0x56, byte);
131 static void set_thermal_config()
139 ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
140 ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
141 ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
142 ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
144 ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
145 ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
147 byte = ADT7461_read_byte(0x02); /* read status register to clear it */
148 ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
149 printk_info("Init adt7461 end , status 0x02 %02x\n", byte);
151 /* sb600 settings for thermal config */
152 /* set SB600 GPIO 64 to GPIO with pull-up */
153 byte = pm2_ioread(0x42);
155 pm2_iowrite(0x42, byte);
157 /* set GPIO 64 to input */
158 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
160 pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,
161 sm_dev->path.u.pci.devfn, 0x56);
163 pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,
164 sm_dev->path.u.pci.devfn, 0x56, word);
166 /* set GPIO 64 internal pull-up */
167 byte = pm2_ioread(0xf0);
169 pm2_iowrite(0xf0, byte);
171 /* set Talert to be active low */
172 byte = pm_ioread(0x67);
174 pm_iowrite(0x67, byte);
176 /* set Talert to generate ACPI event */
177 byte = pm_ioread(0x3c);
179 pm_iowrite(0x3c, byte);
182 /* byte = pm_ioread(0x68);
184 * pm_iowrite(0x68, byte);
186 * byte = pm_ioread(0x55);
188 * pm_iowrite(0x55, byte);
190 * byte = pm_ioread(0x67);
191 * byte &= ~( 1 << 6);
192 * pm_iowrite(0x67, byte);
196 /*************************************************
197 * enable the dedicated function in dbm690t board.
198 * This function called early than rs690_enable.
199 *************************************************/
200 void dbm690t_enable(device_t dev)
202 struct mainboard_amd_dbm690t_config *mainboard =
203 (struct mainboard_amd_dbm690t_config *)dev->chip_info;
205 printk_info("Mainboard DBM690T Enable. dev=0x%x\n", dev);
207 #if (CONFIG_GFXUMA == 1)
210 /* TOP_MEM: the top of DRAM below 4G */
211 msr = rdmsr(TOP_MEM);
212 printk_info("%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
213 __func__, msr.lo, msr.hi);
215 /* TOP_MEM2: the top of DRAM above 4G */
216 msr2 = rdmsr(TOP_MEM2);
217 printk_info("%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
218 __func__, msr2.lo, msr2.hi);
221 case 0x10000000: /* 256M system memory */
222 uma_memory_size = 0x2000000; /* 32M recommended UMA */
225 case 0x18000000: /* 384M system memory */
226 uma_memory_size = 0x4000000; /* 64M recommended UMA */
229 case 0x20000000: /* 512M system memory */
230 uma_memory_size = 0x4000000; /* 64M recommended UMA */
233 default: /* 1GB and above system memory */
234 uma_memory_size = 0x8000000; /* 128M recommended UMA */
238 uma_memory_start = msr.lo - uma_memory_size; /* TOP_MEM1 */
239 printk_info("%s: uma size 0x%08x, memory start 0x%08x\n",
240 __func__, uma_memory_size, uma_memory_start);
244 uma_memory_size = 0x8000000; /* 128M recommended UMA */
245 uma_memory_start = 0x38000000; /* 1GB system memory supposed */
248 enable_onboard_nic();
250 set_thermal_config();
253 int add_mainboard_resources(struct lb_memory *mem)
255 /* UMA is removed from system memory in the northbridge code, but
256 * in some circumstances we want the memory mentioned as reserved.
258 #if (CONFIG_GFXUMA == 1)
259 printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n",
260 uma_memory_start, uma_memory_size);
261 lb_add_memory_range(mem, LB_MEM_RESERVED,
262 uma_memory_start, uma_memory_size);
267 * CONFIG_CHIP_NAME defined in Option.lb.
269 struct chip_operations mainboard_amd_dbm690t_ops = {
270 CHIP_NAME("AMD DBM690T Mainboard")
271 .enable_dev = dbm690t_enable,