2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 Advanced Micro Devices, Inc.
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
23 default CONFIG_XIP_ROM_SIZE = 64 * 1024
24 include /config/nofailovercalculation.lb
29 ## Build the objects we have code for in this directory.
36 if CONFIG_GENERATE_MP_TABLE object mptable.o end
37 if CONFIG_GENERATE_PIRQ_TABLE
42 if CONFIG_GENERATE_ACPI_TABLES
46 depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
47 action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
48 action "mv dsdt.hex dsdt.c"
55 makerule ./cache_as_ram_auto.o
56 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
57 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
62 makerule ./cache_as_ram_auto.inc
63 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
64 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
65 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
66 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
72 ## Build our 16 bit and 32 bit coreboot entry code
74 mainboardinit cpu/x86/16bit/entry16.inc
75 mainboardinit cpu/x86/32bit/entry32.inc
76 ldscript /cpu/x86/16bit/entry16.lds
78 ldscript /cpu/x86/32bit/entry32.lds
82 ldscript /cpu/amd/car/cache_as_ram.lds
86 ## Build our reset vector (This is where coreboot is entered)
88 if CONFIG_USE_FALLBACK_IMAGE
89 mainboardinit cpu/x86/16bit/reset16.inc
90 ldscript /cpu/x86/16bit/reset16.lds
92 mainboardinit cpu/x86/32bit/reset32.inc
93 ldscript /cpu/x86/32bit/reset32.lds
97 ## Include an id string (For safe flashing)
99 mainboardinit arch/i386/lib/id.inc
100 ldscript /arch/i386/lib/id.lds
103 ## Setup Cache-As-Ram
105 mainboardinit cpu/amd/car/cache_as_ram.inc
108 ### This is the early phase of coreboot startup
109 ### Things are delicate and we test to see if we should
110 ### failover to another image.
112 if CONFIG_USE_FALLBACK_IMAGE
113 ldscript /arch/i386/lib/failover.lds
117 ### O.k. We aren't just an intermediary anymore!
124 initobject cache_as_ram_auto.o
126 mainboardinit ./cache_as_ram_auto.inc
130 ## Include the secondary Configuration files
134 #The variables belong to mainboard are defined here.
136 #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
137 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
138 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
139 # 1: the system allows a PCIE link to be established on Dev2 or Dev3.
140 #Define gfx_dual_slot, 0: single slot, 1: dual slot
141 #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
142 #Define gfx_tmds, 0: didn't support TMDS, 1: support
143 #Define gfx_compliance, 0: didn't support compliance, 1: support
144 #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
145 #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
146 chip northbridge/amd/amdk8/root_complex
147 device apic_cluster 0 on
148 chip cpu/amd/socket_S1G1
152 device pci_domain 0 on
153 chip northbridge/amd/amdk8
154 device pci 18.0 on # southbridge
155 chip southbridge/amd/rs690
156 device pci 0.0 on end # HT 0x7910
157 device pci 1.0 on # Internal Graphics P2P bridge 0x7912
158 chip drivers/pci/onboard
159 device pci 5.0 on end # Internal Graphics 0x791F
162 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
163 device pci 3.0 off end # PCIE P2P bridge 0x791b
164 device pci 4.0 on end # PCIE P2P bridge 0x7914
165 device pci 5.0 on end # PCIE P2P bridge 0x7915
166 device pci 6.0 on end # PCIE P2P bridge 0x7916
167 device pci 7.0 on end # PCIE P2P bridge 0x7917
168 device pci 8.0 off end # NB/SB Link P2P bridge
169 register "gpp_configuration" = "4"
170 register "port_enable" = "0xfc"
171 register "gfx_dev2_dev3" = "1"
172 register "gfx_dual_slot" = "0"
173 register "gfx_lane_reversal" = "0"
174 register "gfx_tmds" = "0"
175 register "gfx_compliance" = "0"
176 register "gfx_reconfiguration" = "1"
177 register "gfx_link_width" = "0"
179 chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
180 device pci 12.0 on end # SATA 0x4380
181 device pci 13.0 on end # USB 0x4387
182 device pci 13.1 on end # USB 0x4388
183 device pci 13.2 on end # USB 0x4389
184 device pci 13.3 on end # USB 0x438a
185 device pci 13.4 on end # USB 0x438b
186 device pci 13.5 on end # USB 2 0x4386
187 device pci 14.0 on # SM 0x4385
188 chip drivers/generic/generic #dimm 0-0-0
191 chip drivers/generic/generic #dimm 0-0-1
194 chip drivers/generic/generic #dimm 0-1-0
197 chip drivers/generic/generic #dimm 0-1-1
201 device pci 14.1 on end # IDE 0x438c
202 device pci 14.2 on end # HDA 0x4383
203 device pci 14.3 on # LPC 0x438d
204 chip superio/ite/it8712f
205 device pnp 2e.0 off # Floppy
210 device pnp 2e.1 on # Com1
214 device pnp 2e.2 off # Com2
218 device pnp 2e.3 off # Parallel Port
222 device pnp 2e.4 off end # EC
223 device pnp 2e.5 on # Keyboard
228 device pnp 2e.6 on # Mouse
231 device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
233 device pnp 2e.8 off # MIDI
237 device pnp 2e.9 off # GAME
240 device pnp 2e.a off end # CIR
241 end #superio/ite/it8712f
243 device pci 14.4 on end # PCI 0x4384
244 device pci 14.5 on end # ACI 0x4382
245 device pci 14.6 on end # MCI 0x438e
246 register "ide0_enable" = "1"
247 register "sata0_enable" = "1"
248 register "hda_viddid" = "0x10ec0882"
249 end #southbridge/amd/sb600
250 end # device pci 18.0
252 device pci 18.0 on end
253 device pci 18.0 on end
254 device pci 18.1 on end
255 device pci 18.2 on end
256 device pci 18.3 on end
257 end #northbridge/amd/amdk8
259 end #northbridge/amd/amdk8/root_complex