All these boards already had the CACHE_AS_RAM option in their individual
[coreboot.git] / src / mainboard / amd / db800 / Kconfig
1 if BOARD_AMD_DB800
2
3 config BOARD_SPECIFIC_OPTIONS # dummy
4         def_bool y
5         select ARCH_X86
6         select CPU_AMD_LX
7         select NORTHBRIDGE_AMD_LX
8         select SOUTHBRIDGE_AMD_CS5536
9         select SUPERIO_WINBOND_W83627HF
10         select HAVE_PIRQ_TABLE
11         select PIRQ_ROUTE
12         select UDELAY_TSC
13         select BOARD_ROMSIZE_KB_256
14
15 config MAINBOARD_DIR
16         string
17         default amd/db800
18
19 config MAINBOARD_PART_NUMBER
20         string
21         default "DB800"
22
23 config IRQ_SLOT_COUNT
24         int
25         default 4
26
27 endif # BOARD_AMD_DB800