2 * This file is part of the coreboot project.
4 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
5 * Copyright (C) 2007-2008 coresystems GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
22 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
23 #define post_code(x) intel_chip_post_macro(x)
25 #include <cpu/x86/mtrr.h>
26 #include <cpu/amd/mtrr.h>
28 /* Save the BIST result */
32 #if CONFIG_USE_FALLBACK_IMAGE == 1
36 /* Send INIT IPI to all excluding ourself */
37 movl $0x000C4500, %eax
38 movl $0xFEE00300, %esi
41 /* Disable prefetchers */
44 orl $((1 << 9) | (1 << 19)), %eax
45 orl $((1 << 5) | (1 << 7)), %edx
48 /* Zero out all Fixed Range and Variable Range MTRRs */
49 movl $mtrr_table, %esi
50 movl $( (mtrr_table_end - mtrr_table) / 2), %edi
61 /* Configure the default memory type to uncacheable */
62 movl $MTRRdefType_MSR, %ecx
64 andl $(~0x00000cff), %eax
67 /* Set cache as ram base address */
68 movl $(MTRRphysBase_MSR(0)), %ecx
69 movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
73 /* Set cache as ram mask */
74 movl $(MTRRphysMask_MSR(0)), %ecx
75 movl $(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax
76 movl $0x0000000f, %edx
80 movl $MTRRdefType_MSR, %ecx
91 /* CR0.CD = 0, CR0.NW = 0 */
93 andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
97 /* Clear the cache memory reagion */
98 movl $CACHE_AS_RAM_BASE, %esi
100 movl $(CACHE_AS_RAM_SIZE / 4), %ecx
101 //movl $0x23322332, %eax
106 /* Enable Cache As RAM mode by disabling cache */
111 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
112 /* Enable cache for our code in Flash because we do XIP here */
113 movl $MTRRphysBase_MSR(1), %ecx
115 movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
118 movl $MTRRphysMask_MSR(1), %ecx
119 movl $0x0000000f, %edx
120 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
122 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
126 andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
129 /* Set up stack pointer */
130 movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
133 /* Restore the BIST result */
149 .word 0x250, 0x258, 0x259
150 .word 0x268, 0x269, 0x26A
151 .word 0x26B, 0x26C, 0x26D
154 .word 0x200, 0x201, 0x202, 0x203
155 .word 0x204, 0x205, 0x206, 0x207
156 .word 0x208, 0x209, 0x20A, 0x20B
157 .word 0x20C, 0x20D, 0x20E, 0x20F