2 * This file is part of the coreboot project.
4 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
5 * Copyright (C) 2007-2008 coresystems GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
22 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
23 #define post_code(x) intel_chip_post_macro(x)
25 #include <cpu/x86/mtrr.h>
26 #include <cpu/amd/mtrr.h>
28 /* Save the BIST result */
32 #if CONFIG_USE_FALLBACK_IMAGE == 1
36 /* Send INIT IPI to all excluding ourself */
37 movl $0x000C4500, %eax
38 movl $0xFEE00300, %esi
41 /* Zero out all Fixed Range and Variable Range MTRRs */
42 movl $mtrr_table, %esi
43 movl $( (mtrr_table_end - mtrr_table) / 2), %edi
54 /* Configure the default memory type to uncacheable */
55 movl $MTRRdefType_MSR, %ecx
57 andl $(~0x00000cff), %eax
60 /* Set cache as ram base address */
61 movl $(MTRRphysBase_MSR(0)), %ecx
62 movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
66 /* Set cache as ram mask */
67 movl $(MTRRphysMask_MSR(0)), %ecx
68 movl $(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax
69 movl $0x0000000f, %edx
73 movl $MTRRdefType_MSR, %ecx
84 /* CR0.CD = 0, CR0.NW = 0 */
86 andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
90 /* Clear the cache memory reagion */
91 movl $CACHE_AS_RAM_BASE, %esi
93 movl $(CACHE_AS_RAM_SIZE / 4), %ecx
94 //movl $0x23322332, %eax
99 /* Enable Cache As RAM mode by disabling cache */
104 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
105 /* Enable cache for our code in Flash because we do XIP here */
106 movl $MTRRphysBase_MSR(1), %ecx
108 movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
111 movl $MTRRphysMask_MSR(1), %ecx
112 movl $0x0000000f, %edx
113 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
115 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
119 andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
122 /* Set up stack pointer */
123 movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
126 /* Restore the BIST result */
142 .word 0x250, 0x258, 0x259
143 .word 0x268, 0x269, 0x26A
144 .word 0x26B, 0x26C, 0x26D
147 .word 0x200, 0x201, 0x202, 0x203
148 .word 0x204, 0x205, 0x206, 0x207
149 .word 0x208, 0x209, 0x20A, 0x20B
150 .word 0x20C, 0x20D, 0x20E, 0x20F