2 * This file is part of the coreboot project.
4 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
5 * Copyright (C) 2007-2008 coresystems GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <cpu/x86/stack.h>
22 #include <cpu/x86/mtrr.h>
24 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
25 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
27 /* Save the BIST result. */
33 /* Send INIT IPI to all excluding ourself. */
34 movl $0x000C4500, %eax
35 movl $0xFEE00300, %esi
38 /* Zero out all fixed range and variable range MTRRs. */
39 movl $mtrr_table, %esi
40 movl $((mtrr_table_end - mtrr_table) / 2), %edi
51 /* Configure the default memory type to uncacheable. */
52 movl $MTRRdefType_MSR, %ecx
54 andl $(~0x00000cff), %eax
57 /* Set Cache-as-RAM base address. */
58 movl $(MTRRphysBase_MSR(0)), %ecx
59 movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
63 /* Set Cache-as-RAM mask. */
64 movl $(MTRRphysMask_MSR(0)), %ecx
65 movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
66 movl $0x0000000f, %edx
70 movl $MTRRdefType_MSR, %ecx
75 /* Enable L2 cache. */
81 /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
83 andl $(~((1 << 30) | (1 << 29))), %eax
87 /* Clear the cache memory reagion. */
88 movl $CACHE_AS_RAM_BASE, %esi
90 movl $(CACHE_AS_RAM_SIZE / 4), %ecx
91 // movl $0x23322332, %eax
95 /* Enable Cache-as-RAM mode by disabling cache. */
100 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
101 /* Enable cache for our code in Flash because we do XIP here */
102 movl $MTRRphysBase_MSR(1), %ecx
104 #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
105 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
107 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
110 * IMPORTANT: The two lines below can _not_ be written like this:
111 * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
112 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
114 movl $REAL_XIP_ROM_BASE, %eax
115 orl $MTRR_TYPE_WRBACK, %eax
118 movl $MTRRphysMask_MSR(1), %ecx
119 movl $0x0000000f, %edx
120 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
122 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
126 andl $(~((1 << 30) | (1 << 29))), %eax
129 /* Set up the stack pointer. */
130 #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
131 /* Leave some space for the struct ehci_debug_info. */
132 movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
134 movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
138 /* Restore the BIST result. */
145 /* Call romstage.c main function. */
160 movl $MTRRdefType_MSR, %ecx
162 andl $(~(1 << 11)), %eax
171 movl $MTRRphysBase_MSR(0), %ecx
173 movl $MTRRphysMask_MSR(0), %ecx
175 movl $MTRRphysBase_MSR(1), %ecx
177 movl $MTRRphysMask_MSR(1), %ecx
185 andl $~((1 << 30) | (1 << 29)), %eax
197 /* Enable Write Back and Speculative Reads for the first 1MB. */
198 movl $MTRRphysBase_MSR(0), %ecx
199 movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
202 movl $MTRRphysMask_MSR(0), %ecx
203 movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax
204 movl $0x0000000f, %edx // 36bit address space
209 /* And enable cache again after setting MTRRs. */
211 andl $~((1 << 30) | (1 << 29)), %eax
217 movl $MTRRdefType_MSR, %ecx
224 /* Invalidate the cache again. */
229 /* Clear boot_complete flag. */
233 cld /* Clear direction flag. */
237 movl $ROMSTAGE_STACK, %esp
249 .word 0x250, 0x258, 0x259
250 .word 0x268, 0x269, 0x26A
251 .word 0x26B, 0x26C, 0x26D
254 .word 0x200, 0x201, 0x202, 0x203
255 .word 0x204, 0x205, 0x206, 0x207
256 .word 0x208, 0x209, 0x20A, 0x20B
257 .word 0x20C, 0x20D, 0x20E, 0x20F