1 /* microcode.c: Microcode update for PIII and later CPUS
5 #include <console/console.h>
7 #include <cpu/x86/msr.h>
8 #include <cpu/intel/microcode.h>
11 u32 hdrver; /* Header Version */
12 u32 rev; /* Patch ID */
16 u32 cksum; /* Checksum */
17 u32 ldrver; /* Loader Version */
18 u32 pf; /* Platform ID */
20 u32 data_size; /* Data size */
21 u32 total_size; /* Total size */
27 static inline u32 read_microcode_rev(void)
29 /* Some Intel Cpus can be very finicky about the
30 * CPUID sequence used. So this is implemented in
31 * assembly so that it works reliably.
36 "xorl %%eax, %%eax\n\t"
37 "xorl %%edx, %%edx\n\t"
38 "movl $0x8b, %%ecx\n\t"
40 "movl $0x01, %%eax\n\t"
42 "movl $0x08b, %%ecx\n\t"
45 "=a" (msr.lo), "=d" (msr.hi)
53 void intel_update_microcode(const void *microcode_updates)
56 unsigned int pf, rev, sig;
57 unsigned int x86_model, x86_family;
58 const struct microcode *m;
62 /* cpuid sets msr 0x8B iff a microcode update has been loaded. */
69 x86_model = (eax >>4) & 0x0f;
70 x86_family = (eax >>8) & 0x0f;
74 if ((x86_model >= 5)||(x86_family>6)) {
76 pf = 1 << ((msr.hi >> 18) & 7);
78 print_debug("microcode_info: sig = 0x");
79 print_debug_hex32(sig);
80 print_debug(" pf=0x");
81 print_debug_hex32(pf);
82 print_debug(" rev = 0x");
83 print_debug_hex32(rev);
86 m = microcode_updates;
87 for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) {
88 if ((m->sig == sig) && (m->pf & pf)) {
90 msr.lo = (unsigned long)(&m->bits) & 0xffffffff;
94 /* Read back the new microcode version */
95 new_rev = read_microcode_rev();
97 print_debug("microcode updated to revision: ");
98 print_debug_hex32(new_rev);
99 print_debug(" from revision ");
100 print_debug_hex32(rev);