Add support for Intel Sandybridge CPU

Change-Id: I9f37e291c00c0640c6600d8fdd6dcc13c3e5b8d5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/855
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index 81a834c5d5c7e17ce158eb1905daef0021eb96de..c6dab12cccc5548d1aabff9b7aa92a936e92c611 100644 (file)
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -9,6 +9,7 @@ source src/cpu/intel/model_6ex/Kconfig
 source src/cpu/intel/model_6fx/Kconfig
 source src/cpu/intel/model_1067x/Kconfig
 source src/cpu/intel/model_106cx/Kconfig
+source src/cpu/intel/model_206ax/Kconfig
 source src/cpu/intel/model_f0x/Kconfig
 source src/cpu/intel/model_f1x/Kconfig
 source src/cpu/intel/model_f2x/Kconfig
@@ -29,3 +30,4 @@ source src/cpu/intel/socket_mPGA604/Kconfig
 source src/cpu/intel/socket_PGA370/Kconfig
 source src/cpu/intel/socket_441/Kconfig
 source src/cpu/intel/socket_LGA771/Kconfig
+source src/cpu/intel/socket_rPGA989/Kconfig

diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index 05f947dffbd850f88fea79f2654aded1b604d1b4..9e498f194a8d65f1241fed76a8cd7c3c3da65e8b 100644 (file)
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -14,6 +14,9 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA479M) += socket_mPGA479M
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax
 subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2
 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA771) += socket_LGA771

diff --git a/src/cpu/intel/microcode/update-microcodes.sh b/src/cpu/intel/microcode/update-microcodes.sh
index 7a234a83bc0dfe3437384d003d97600cb2f4e842..cd1428a60b2d440312a1badbe11d6a27a6c7870d 100755 (executable)
--- a/src/cpu/intel/microcode/update-microcodes.sh
+++ b/src/cpu/intel/microcode/update-microcodes.sh
@@ -18,10 +18,10 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
-MICROCODE_VERSION=20100914
+MICROCODE_VERSION=20111110
 MICROCODE_ARCHIVE=microcode-$MICROCODE_VERSION.tgz
-MICROCODE_FILE=microcode-$MICROCODE_VERSION.dat
-INTEL_MICROCODE=http://downloadmirror.intel.com/19342/eng/$MICROCODE_ARCHIVE
+MICROCODE_FILE=microcode.dat
+INTEL_MICROCODE=http://downloadmirror.intel.com/20728/eng/$MICROCODE_ARCHIVE
 
 #
 # Getting Intel(R) Microcode

diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
new file mode 100644 (file)
index 0000000..c11f21a
--- /dev/null
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -0,0 +1,53 @@
+config CPU_INTEL_MODEL_206AX
+       bool
+
+config CPU_INTEL_MODEL_306AX
+       bool
+
+if CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX
+
+config CPU_SPECIFIC_OPTIONS
+       def_bool y
+       select SMP
+       select SSE2
+       select UDELAY_LAPIC
+       select SMM_TSEG
+       #select AP_IN_SIPI_WAIT
+
+config BOOTBLOCK_CPU_INIT
+       string
+       default "cpu/intel/model_206ax/bootblock.c"
+
+config SERIAL_CPU_INIT
+       bool
+       default n
+
+config SMM_TSEG_SIZE
+       hex
+       default 0x800000
+
+config ENABLE_VMX
+       bool "Enable VMX for virtualization"
+       default n
+
+endif
+
+if CPU_INTEL_MODEL_206AX
+   config CPU_MODEL_NAME
+       string
+       default "Intel SandyBridge CPU"
+
+   config CPU_MODEL_INDEX
+       hex
+       default 0x2a
+endif
+
+if CPU_INTEL_MODEL_306AX
+   config CPU_MODEL_NAME
+       string
+       default "Intel IvyBridge CPU"
+
+   config CPU_MODEL_INDEX
+       hex
+       default 0x3a
+endif

diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
new file mode 100644 (file)
index 0000000..e9b8e6d
--- /dev/null
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -0,0 +1,8 @@
+driver-y += model_206ax_init.c
+subdirs-y += ../../x86/name
+
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
+
+cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc

diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c
new file mode 100644 (file)
index 0000000..3a3a1fd
--- /dev/null
+++ b/src/cpu/intel/model_206ax/acpi.c
@@ -0,0 +1,357 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+#include <cpu/intel/acpi.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/turbo.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include "model_206ax.h"
+#include "chip.h"
+
+static int get_cores_per_package(void)
+{
+       struct cpuinfo_x86 c;
+       struct cpuid_result result;
+       int cores = 1;
+
+       get_fms(&c, cpuid_eax(1));
+       if (c.x86 != 6)
+               return 1;
+
+       switch (c.x86_model) {
+       case CONFIG_CPU_MODEL_INDEX:
+               result = cpuid_ext(0xb, 1);
+               cores = result.ebx & 0xff;
+               break;
+       default:
+               cores = (cpuid_ebx(1) >> 16) & 0xff;
+               break;
+       }
+
+       return cores;
+}
+
+static int generate_cstate_entries(acpi_cstate_t *cstates,
+                                  int c1, int c2, int c3)
+{
+       int length, cstate_count = 0;
+
+       /* Count number of active C-states */
+       if (c1 > 0)
+               ++cstate_count;
+       if (c2 > 0)
+               ++cstate_count;
+       if (c3 > 0)
+               ++cstate_count;
+       if (!cstate_count)
+               return 0;
+
+       length = acpigen_write_package(cstate_count + 1);
+       length += acpigen_write_byte(cstate_count);
+
+       /* Add an entry if the level is enabled */
+       if (c1 > 0)
+               length += acpigen_write_CST_package(1, &cstates[c1]);
+       if (c2 > 0)
+               length += acpigen_write_CST_package(2, &cstates[c2]);
+       if (c3 > 0)
+               length += acpigen_write_CST_package(3, &cstates[c3]);
+
+       acpigen_patch_len(length - 1);
+       return length;
+}
+
+static int generate_C_state_entries(void)
+{
+       struct cpu_info *info;
+       struct cpu_driver *cpu;
+       int len, lenif;
+       device_t lapic;
+       struct cpu_intel_model_206ax_config *conf = NULL;
+
+       /* Find the SpeedStep CPU in the device tree using magic APIC ID */
+       lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+       if (!lapic)
+               return 0;
+       conf = lapic->chip_info;
+       if (!conf)
+               return 0;
+
+       /* Find CPU map of supported C-states */
+       info = cpu_info();
+       if (!info)
+               return 0;
+       cpu = find_cpu_driver(info->cpu);
+       if (!cpu || !cpu->cstates)
+               return 0;
+
+       len = acpigen_emit_byte(0x14);          /* MethodOp */
+       len += acpigen_write_len_f();           /* PkgLength */
+       len += acpigen_emit_namestring("_CST");
+       len += acpigen_emit_byte(0x00);         /* No Arguments */
+
+       /* If running on AC power */
+       len += acpigen_emit_byte(0xa0);         /* IfOp */
+       lenif = acpigen_write_len_f();          /* PkgLength */
+       lenif += acpigen_emit_namestring("PWRS");
+       lenif += acpigen_emit_byte(0xa4);       /* ReturnOp */
+       lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower,
+                                        conf->c2_acpower, conf->c3_acpower);
+       acpigen_patch_len(lenif - 1);
+       len += lenif;
+
+       /* Else on battery power */
+       len += acpigen_emit_byte(0xa4); /* ReturnOp */
+       len += generate_cstate_entries(cpu->cstates, conf->c1_battery,
+                                       conf->c2_battery, conf->c3_battery);
+       acpigen_patch_len(len - 1);
+       return len;
+}
+
+static acpi_tstate_t tss_table_fine[] = {
+       { 100, 1000, 0, 0x00, 0 },
+       { 94, 940, 0, 0x1f, 0 },
+       { 88, 880, 0, 0x1e, 0 },
+       { 82, 820, 0, 0x1d, 0 },
+       { 75, 760, 0, 0x1c, 0 },
+       { 69, 700, 0, 0x1b, 0 },
+       { 63, 640, 0, 0x1a, 0 },
+       { 57, 580, 0, 0x19, 0 },
+       { 50, 520, 0, 0x18, 0 },
+       { 44, 460, 0, 0x17, 0 },
+       { 38, 400, 0, 0x16, 0 },
+       { 32, 340, 0, 0x15, 0 },
+       { 25, 280, 0, 0x14, 0 },
+       { 19, 220, 0, 0x13, 0 },
+       { 13, 160, 0, 0x12, 0 },
+};
+
+static acpi_tstate_t tss_table_coarse[] = {
+       { 100, 1000, 0, 0x00, 0 },
+       { 88, 875, 0, 0x1f, 0 },
+       { 75, 750, 0, 0x1e, 0 },
+       { 63, 625, 0, 0x1d, 0 },
+       { 50, 500, 0, 0x1c, 0 },
+       { 38, 375, 0, 0x1b, 0 },
+       { 25, 250, 0, 0x1a, 0 },
+       { 13, 125, 0, 0x19, 0 },
+};
+
+static int generate_T_state_entries(int core, int cores_per_package)
+{
+       int len;
+
+       /* Indicate SW_ALL coordination for T-states */
+       len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
+
+       /* Indicate FFixedHW so OS will use MSR */
+       len += acpigen_write_empty_PTC();
+
+       /* Set a T-state limit that can be modified in NVS */
+       len += acpigen_write_TPC("\\TLVL");
+
+       /*
+        * CPUID.(EAX=6):EAX[5] indicates support
+        * for extended throttle levels.
+        */
+       if (cpuid_eax(6) & (1 << 5))
+               len += acpigen_write_TSS_package(
+                       ARRAY_SIZE(tss_table_fine), tss_table_fine);
+       else
+               len += acpigen_write_TSS_package(
+                       ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
+
+       return len;
+}
+
+static int calculate_power(int tdp, int p1_ratio, int ratio)
+{
+       u32 m;
+       u32 power;
+
+       /*
+        * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
+        *
+        * Power = (ratio / p1_ratio) * m * tdp
+        */
+
+       m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
+       m = (m * m) / 1000;
+
+       power = ((ratio * 100000 / p1_ratio) / 100);
+       power *= (m / 100) * (tdp / 1000);
+       power /= 1000;
+
+       return (int)power;
+}
+
+static int generate_P_state_entries(int core, int cores_per_package)
+{
+       int len, len_pss;
+       int ratio_min, ratio_max, ratio_turbo, ratio_step;
+       int coord_type, power_max, power_unit, num_entries;
+       int ratio, power, clock, clock_max;
+       msr_t msr;
+
+       /* Determine P-state coordination type from MISC_PWR_MGMT[0] */
+       msr = rdmsr(MSR_MISC_PWR_MGMT);
+       if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
+               coord_type = SW_ANY;
+       else
+               coord_type = HW_ALL;
+
+       /* Get bus ratio limits and calculate clock speeds */
+       msr = rdmsr(MSR_PLATFORM_INFO);
+       ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
+       ratio_max = (msr.lo >> 8) & 0xff;       /* Max Non-Turbo Ratio */
+       clock_max = ratio_max * SANDYBRIDGE_BCLK;
+
+       /* Calculate CPU TDP in mW */
+       msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
+       power_unit = 2 << ((msr.lo & 0xf) - 1);
+       msr = rdmsr(MSR_PKG_POWER_SKU);
+       power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
+
+       /* Write _PCT indicating use of FFixedHW */
+       len = acpigen_write_empty_PCT();
+
+       /* Write _PPC with no limit on supported P-state */
+       len += acpigen_write_PPC(0);
+
+       /* Write PSD indicating configured coordination type */
+       len += acpigen_write_PSD_package(core, cores_per_package, coord_type);
+
+       /* Add P-state entries in _PSS table */
+       len += acpigen_write_name("_PSS");
+
+       /* Determine ratio points */
+       ratio_step = PSS_RATIO_STEP;
+       num_entries = (ratio_max - ratio_min) / ratio_step;
+       while (num_entries > PSS_MAX_ENTRIES-1) {
+               ratio_step <<= 1;
+               num_entries >>= 1;
+       }
+
+       /* P[T] is Turbo state if enabled */
+       if (get_turbo_state() == TURBO_ENABLED) {
+               /* _PSS package count including Turbo */
+               len_pss = acpigen_write_package(num_entries + 2);
+
+               msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
+               ratio_turbo = msr.lo & 0xff;
+
+               /* Add entry for Turbo ratio */
+               len_pss += acpigen_write_PSS_package(
+                       clock_max + 1,          /*MHz*/
+                       power_max,              /*mW*/
+                       PSS_LATENCY_TRANSITION, /*lat1*/
+                       PSS_LATENCY_BUSMASTER,  /*lat2*/
+                       ratio_turbo << 8,       /*control*/
+                       ratio_turbo << 8);      /*status*/
+       } else {
+               /* _PSS package count without Turbo */
+               len_pss = acpigen_write_package(num_entries + 1);
+       }
+
+       /* First regular entry is max non-turbo ratio */
+       len_pss += acpigen_write_PSS_package(
+               clock_max,              /*MHz*/
+               power_max,              /*mW*/
+               PSS_LATENCY_TRANSITION, /*lat1*/
+               PSS_LATENCY_BUSMASTER,  /*lat2*/
+               ratio_max << 8,         /*control*/
+               ratio_max << 8);        /*status*/
+
+       /* Generate the remaining entries */
+       for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
+            ratio >= ratio_min; ratio -= ratio_step) {
+
+               /* Calculate power at this ratio */
+               power = calculate_power(power_max, ratio_max, ratio);
+               clock = ratio * SANDYBRIDGE_BCLK;
+
+               len_pss += acpigen_write_PSS_package(
+                       clock,                  /*MHz*/
+                       power,                  /*mW*/
+                       PSS_LATENCY_TRANSITION, /*lat1*/
+                       PSS_LATENCY_BUSMASTER,  /*lat2*/
+                       ratio << 8,             /*control*/
+                       ratio << 8);            /*status*/
+       }
+
+       /* Fix package length */
+       len_pss--;
+       acpigen_patch_len(len_pss);
+
+       return len + len_pss;
+}
+
+void generate_cpu_entries(void)
+{
+       int len_pr;
+       int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
+       int totalcores = dev_count_cpu();
+       int cores_per_package = get_cores_per_package();
+       int numcpus = totalcores/cores_per_package;
+
+       printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
+              numcpus, cores_per_package);
+
+       for (cpuID=1; cpuID <=numcpus; cpuID++) {
+               for (coreID=1; coreID<=cores_per_package; coreID++) {
+                       if (coreID>1) {
+                               pcontrol_blk = 0;
+                               plen = 0;
+                       }
+
+                       /* Generate processor \_PR.CPUx */
+                       len_pr = acpigen_write_processor(
+                               (cpuID-1)*cores_per_package+coreID-1,
+                               pcontrol_blk, plen);
+
+                       /* Generate P-state tables */
+                       len_pr += generate_P_state_entries(
+                               cpuID-1, cores_per_package);
+
+                       /* Generate C-state tables */
+                       len_pr += generate_C_state_entries();
+
+                       /* Generate T-state tables */
+                       len_pr += generate_T_state_entries(
+                               cpuID-1, cores_per_package);
+
+                       len_pr--;
+                       acpigen_patch_len(len_pr);
+               }
+       }
+}
+
+struct chip_operations cpu_intel_model_206ax_ops = {
+       CHIP_NAME(CONFIG_CPU_MODEL_NAME)
+};

diff --git a/src/cpu/intel/model_206ax/acpi/cpu.asl b/src/cpu/intel/model_206ax/acpi/cpu.asl
new file mode 100644 (file)
index 0000000..a9d5eeb
--- /dev/null
+++ b/src/cpu/intel/model_206ax/acpi/cpu.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* These devices are created at runtime */
+External (\_PR.CPU0, DeviceObj)
+External (\_PR.CPU1, DeviceObj)
+External (\_PR.CPU2, DeviceObj)
+External (\_PR.CPU3, DeviceObj)
+External (\_PR.CPU4, DeviceObj)
+External (\_PR.CPU5, DeviceObj)
+External (\_PR.CPU6, DeviceObj)
+External (\_PR.CPU7, DeviceObj)
+
+/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
+Method (PNOT)
+{
+       If (LGreaterEqual (\PCNT, 2)) {
+               Notify (\_PR.CPU0, 0x80)  // _PPC
+               Notify (\_PR.CPU0, 0x81)  // _CST
+               Notify (\_PR.CPU1, 0x80)  // _PPC
+               Notify (\_PR.CPU1, 0x81)  // _CST
+       }
+       If (LGreaterEqual (\PCNT, 4)) {
+               Notify (\_PR.CPU2, 0x80)  // _PPC
+               Notify (\_PR.CPU2, 0x81)  // _CST
+               Notify (\_PR.CPU3, 0x80)  // _PPC
+               Notify (\_PR.CPU3, 0x81)  // _CST
+       }
+       If (LGreaterEqual (\PCNT, 8)) {
+               Notify (\_PR.CPU4, 0x80)  // _PPC
+               Notify (\_PR.CPU4, 0x81)  // _CST
+               Notify (\_PR.CPU5, 0x80)  // _PPC
+               Notify (\_PR.CPU5, 0x81)  // _CST
+               Notify (\_PR.CPU6, 0x80)  // _PPC
+               Notify (\_PR.CPU6, 0x81)  // _CST
+               Notify (\_PR.CPU7, 0x80)  // _PPC
+               Notify (\_PR.CPU7, 0x81)  // _CST
+       }
+}
+
+/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */
+Method (TNOT)
+{
+       If (LGreaterEqual (\PCNT, 2)) {
+               Notify (\_PR.CPU0, 0x82)  // _TPC
+               Notify (\_PR.CPU1, 0x82)  // _TPC
+       }
+       If (LGreaterEqual (\PCNT, 4)) {
+               Notify (\_PR.CPU2, 0x82)  // _TPC
+               Notify (\_PR.CPU3, 0x82)  // _TPC
+       }
+       If (LGreaterEqual (\PCNT, 8)) {
+               Notify (\_PR.CPU4, 0x82)  // _TPC
+               Notify (\_PR.CPU5, 0x82)  // _TPC
+               Notify (\_PR.CPU6, 0x82)  // _TPC
+               Notify (\_PR.CPU7, 0x82)  // _TPC
+       }
+}
+
+/* Return a package containing enabled processor entries */
+Method (PPKG)
+{
+       If (LGreaterEqual (\PCNT, 8)) {
+               Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3,
+                                  \_PR.CPU4, \_PR.CPU5, \_PR.CPU6, \_PR.CPU7})
+       } ElseIf (LGreaterEqual (\PCNT, 4)) {
+               Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3})
+       } ElseIf (LGreaterEqual (\PCNT, 2)) {
+               Return (Package() {\_PR.CPU0, \_PR.CPU1})
+       } Else {
+               Return (Package() {\_PR.CPU0})
+       }
+}

diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
new file mode 100644 (file)
index 0000000..7925315
--- /dev/null
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -0,0 +1,152 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+
+static const uint32_t microcode_updates[] = {
+       #include "x06_microcode.h"
+};
+
+struct microcode {
+       u32 hdrver;     /* Header Version */
+       u32 rev;        /* Patch ID       */
+       u32 date;       /* DATE           */
+       u32 sig;        /* CPUID          */
+
+       u32 cksum;      /* Checksum       */
+       u32 ldrver;     /* Loader Version */
+       u32 pf;         /* Platform ID    */
+
+       u32 data_size;  /* Data size      */
+       u32 total_size; /* Total size     */
+
+       u32 reserved[3];
+       u32 bits[1012];
+};
+
+static inline u32 read_microcode_rev(void)
+{
+       /* Some Intel Cpus can be very finicky about the
+        * CPUID sequence used.  So this is implemented in
+        * assembly so that it works reliably.
+        */
+       msr_t msr;
+       __asm__ volatile (
+               "wrmsr\n\t"
+               "xorl %%eax, %%eax\n\t"
+               "xorl %%edx, %%edx\n\t"
+               "movl $0x8b, %%ecx\n\t"
+               "wrmsr\n\t"
+               "movl $0x01, %%eax\n\t"
+               "cpuid\n\t"
+               "movl $0x08b, %%ecx\n\t"
+               "rdmsr \n\t"
+               : /* outputs */
+               "=a" (msr.lo), "=d" (msr.hi)
+               : /* inputs */
+               : /* trashed */
+                "ecx"
+       );
+       return msr.hi;
+}
+
+void intel_update_microcode(const void *microcode_updates)
+{
+       unsigned int eax;
+       unsigned int pf, rev, sig;
+       unsigned int x86_model, x86_family;
+       const struct microcode *m;
+       const char *c;
+       msr_t msr;
+
+       /* cpuid sets msr 0x8B iff a microcode update has been loaded. */
+       msr.lo = 0;
+       msr.hi = 0;
+       wrmsr(0x8B, msr);
+       eax = cpuid_eax(1);
+       msr = rdmsr(0x8B);
+       rev = msr.hi;
+       x86_model = (eax >>4) & 0x0f;
+       x86_family = (eax >>8) & 0x0f;
+       sig = eax;
+
+       pf = 0;
+       if ((x86_model >= 5)||(x86_family>6)) {
+               msr = rdmsr(0x17);
+               pf = 1 << ((msr.hi >> 18) & 7);
+       }
+
+       m = microcode_updates;
+       for(c = microcode_updates; m->hdrver;  m = (const struct microcode *)c) {
+               if ((m->sig == sig) && (m->pf & pf)) {
+                       unsigned int new_rev;
+                       msr.lo = (unsigned long)(&m->bits) & 0xffffffff;
+                       msr.hi = 0;
+                       wrmsr(0x79, msr);
+
+                       /* Read back the new microcode version */
+                       new_rev = read_microcode_rev();
+                       break;
+               }
+               if (m->total_size) {
+                       c += m->total_size;
+               } else {
+                       c += 2048;
+               }
+       }
+}
+
+static void set_var_mtrr(
+       unsigned reg, unsigned base, unsigned size, unsigned type)
+
+{
+       /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
+       /* FIXME: It only support 4G less range */
+       msr_t basem, maskm;
+       basem.lo = base | type;
+       basem.hi = 0;
+       wrmsr(MTRRphysBase_MSR(reg), basem);
+       maskm.lo = ~(size - 1) | MTRRphysMaskValid;
+       maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
+       wrmsr(MTRRphysMask_MSR(reg), maskm);
+}
+
+static void enable_rom_caching(void)
+{
+       msr_t msr;
+
+       disable_cache();
+       set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);
+       enable_cache();
+
+       /* Enable Variable MTRRs */
+       msr.hi = 0x00000000;
+       msr.lo = 0x00000800;
+       wrmsr(MTRRdefType_MSR, msr);
+}
+
+static void bootblock_cpu_init(void)
+{
+       enable_rom_caching();
+       intel_update_microcode(microcode_updates);
+}

diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
new file mode 100644 (file)
index 0000000..c4d3701
--- /dev/null
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -0,0 +1,348 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <cpu/x86/stack.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/post_code.h>
+#include <cbmem.h>
+
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+
+/* Cache 4GB - MRC_SIZE_KB for MRC */
+#define CACHE_MRC_BYTES   ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
+#define CACHE_MRC_BASE    (0xFFFFFFFF - CACHE_MRC_BYTES)
+#define CACHE_MRC_MASK    (~CACHE_MRC_BYTES)
+
+#define CPU_MAXPHYSADDR 36
+#define CPU_PHYSMASK_HI  (1 << (CPU_MAXPHYSADDR - 32) - 1)
+
+#define NoEvictMod_MSR 0x2e0
+
+       /* Save the BIST result. */
+       movl    %eax, %ebp
+
+cache_as_ram:
+       post_code(0x20)
+
+       /* Send INIT IPI to all excluding ourself. */
+       movl    $0x000C4500, %eax
+       movl    $0xFEE00300, %esi
+       movl    %eax, (%esi)
+
+       /* All CPUs need to be in Wait for SIPI state */
+wait_for_sipi:
+       movl    (%esi), %eax
+       bt      $12, %eax
+       jc      wait_for_sipi
+
+       post_code(0x21)
+       /* Zero out all fixed range and variable range MTRRs. */
+       movl    $mtrr_table, %esi
+       movl    $((mtrr_table_end - mtrr_table) / 2), %edi
+       xorl    %eax, %eax
+       xorl    %edx, %edx
+clear_mtrrs:
+       movw    (%esi), %bx
+       movzx   %bx, %ecx
+       wrmsr
+       add     $2, %esi
+       dec     %edi
+       jnz     clear_mtrrs
+
+       post_code(0x22)
+       /* Configure the default memory type to uncacheable. */
+       movl    $MTRRdefType_MSR, %ecx
+       rdmsr
+       andl    $(~0x00000cff), %eax
+       wrmsr
+
+       post_code(0x23)
+       /* Set Cache-as-RAM base address. */
+       movl    $(MTRRphysBase_MSR(0)), %ecx
+       movl    $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
+       xorl    %edx, %edx
+       wrmsr
+
+       post_code(0x24)
+       /* Set Cache-as-RAM mask. */
+       movl    $(MTRRphysMask_MSR(0)), %ecx
+       movl    $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
+       movl    $CPU_PHYSMASK_HI, %edx
+       wrmsr
+
+       post_code(0x25)
+
+       /* Enable MTRR. */
+       movl    $MTRRdefType_MSR, %ecx
+       rdmsr
+       orl     $MTRRdefTypeEn, %eax
+       wrmsr
+
+       /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
+        movl   %cr0, %eax
+       andl    $(~((1 << 30) | (1 << 29))), %eax
+       invd
+       movl    %eax, %cr0
+
+       /* enable the 'no eviction' mode */
+       movl    $NoEvictMod_MSR, %ecx
+       rdmsr
+       orl     $1, %eax
+       andl    $~2, %eax
+       wrmsr
+
+       /* Clear the cache memory region. This will also fill up the cache */
+       movl    $CACHE_AS_RAM_BASE, %esi
+       movl    %esi, %edi
+       movl    $(CACHE_AS_RAM_SIZE / 4), %ecx
+       // movl $0x23322332, %eax
+       xorl    %eax, %eax
+       rep     stosl
+
+       /* enable the 'no eviction run' state */
+       movl    $NoEvictMod_MSR, %ecx
+       rdmsr
+       orl     $3, %eax
+       wrmsr
+
+       post_code(0x26)
+       /* Enable Cache-as-RAM mode by disabling cache. */
+       movl    %cr0, %eax
+       orl     $(1 << 30), %eax
+       movl    %eax, %cr0
+
+       /* Enable cache for our code in Flash because we do XIP here */
+       movl    $MTRRphysBase_MSR(1), %ecx
+       xorl    %edx, %edx
+       /*
+        * IMPORTANT: The following calculation _must_ be done at runtime. See
+        * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+        */
+       movl    $copy_and_run, %eax
+       andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
+       orl     $MTRR_TYPE_WRPROT, %eax
+       wrmsr
+
+       movl    $MTRRphysMask_MSR(1), %ecx
+       movl    $CPU_PHYSMASK_HI, %edx
+       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+       wrmsr
+
+       post_code(0x27)
+#if CONFIG_CACHE_MRC_BIN
+       /* Enable caching for ram init code to run faster */
+       movl    $MTRRphysBase_MSR(2), %ecx
+       movl    $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
+       xorl    %edx, %edx
+       wrmsr
+       movl    $MTRRphysMask_MSR(2), %ecx
+       movl    $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
+       movl    $CPU_PHYSMASK_HI, %edx
+       wrmsr
+#endif
+
+       post_code(0x28)
+       /* Enable cache. */
+       movl    %cr0, %eax
+       andl    $(~((1 << 30) | (1 << 29))), %eax
+       movl    %eax, %cr0
+
+       /* Set up the stack pointer below MRC variable space. */
+       movl    $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - \
+                 CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 4), %eax
+       movl    %eax, %esp
+
+       /* Restore the BIST result. */
+       movl    %ebp, %eax
+       movl    %esp, %ebp
+       pushl   %eax
+
+before_romstage:
+       post_code(0x29)
+       /* Call romstage.c main function. */
+       call    main
+
+       post_code(0x2f)
+
+       /* Copy global variable space (for USBDEBUG) to memory */
+#if CONFIG_USBDEBUG
+       cld
+       movl    $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 24), %esi
+       movl    $(CONFIG_RAMTOP - 24), %edi
+       movl    $24, %ecx
+       rep     movsb
+#endif
+
+       post_code(0x30)
+
+       /* Disable cache. */
+       movl    %cr0, %eax
+       orl     $(1 << 30), %eax
+       movl    %eax, %cr0
+
+       post_code(0x31)
+
+       /* Disable MTRR. */
+       movl    $MTRRdefType_MSR, %ecx
+       rdmsr
+       andl    $(~MTRRdefTypeEn), %eax
+       wrmsr
+
+       post_code(0x31)
+
+       /* Disable the no eviction run state */
+       movl    $NoEvictMod_MSR, %ecx
+       rdmsr
+       andl    $~2, %eax
+       wrmsr
+
+       invd
+
+       /* Disable the no eviction mode */
+       rdmsr
+       andl    $~1, %eax
+       wrmsr
+
+#if CONFIG_CACHE_MRC_BIN
+       /* Clear MTRR that was used to cache MRC */
+       xorl    %eax, %eax
+       xorl    %edx, %edx
+       movl    $MTRRphysBase_MSR(2), %ecx
+       wrmsr
+       movl    $MTRRphysMask_MSR(2), %ecx
+       wrmsr
+#endif
+
+       post_code(0x33)
+
+       /* Enable cache. */
+       movl    %cr0, %eax
+       andl    $~((1 << 30) | (1 << 29)), %eax
+       movl    %eax, %cr0
+
+       post_code(0x36)
+
+       /* Disable cache. */
+       movl    %cr0, %eax
+       orl     $(1 << 30), %eax
+       movl    %eax, %cr0
+
+       post_code(0x38)
+
+       /* Enable Write Back and Speculative Reads for the first MB
+        * and coreboot_ram.
+        */
+       movl    $MTRRphysBase_MSR(0), %ecx
+       movl    $(0x00000000 | MTRR_TYPE_WRBACK), %eax
+       xorl    %edx, %edx
+       wrmsr
+       movl    $MTRRphysMask_MSR(0), %ecx
+       movl    $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+       movl    $CPU_PHYSMASK_HI, %edx  // 36bit address space
+       wrmsr
+
+       /* Enable Caching and speculative Reads for the
+        * complete ROM now that we actually have RAM.
+        */
+       movl    $MTRRphysBase_MSR(1), %ecx
+       movl    $(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+       xorl    %edx, %edx
+       wrmsr
+       movl    $MTRRphysMask_MSR(1), %ecx
+       movl    $(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax
+       movl    $CPU_PHYSMASK_HI, %edx
+       wrmsr
+
+       post_code(0x39)
+
+       /* And enable cache again after setting MTRRs. */
+       movl    %cr0, %eax
+       andl    $~((1 << 30) | (1 << 29)), %eax
+       movl    %eax, %cr0
+
+       post_code(0x3a)
+
+       /* Enable MTRR. */
+       movl    $MTRRdefType_MSR, %ecx
+       rdmsr
+       orl     $MTRRdefTypeEn, %eax
+       wrmsr
+
+       post_code(0x3b)
+
+       /* Invalidate the cache again. */
+       invd
+
+       post_code(0x3c)
+
+#if CONFIG_HAVE_ACPI_RESUME
+       movl    CBMEM_BOOT_MODE, %eax
+       cmpl    $0x2, %eax // Resume?
+       jne     __acpi_resume_backup_done
+
+       /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+        * through stage 2. We could keep stuff like stack and heap in high
+        * tables memory completely, but that's a wonderful clean up task for
+        * another day.
+        */
+       cld
+       movl    $CONFIG_RAMBASE, %esi
+       movl    CBMEM_RESUME_BACKUP, %edi
+       movl    $HIGH_MEMORY_SAVE / 4, %ecx
+       rep     movsl
+
+__acpi_resume_backup_done:
+#endif
+
+       post_code(0x3d)
+
+       /* Clear boot_complete flag. */
+       xorl    %ebp, %ebp
+__main:
+       post_code(POST_PREPARE_RAMSTAGE)
+       cld                     /* Clear direction flag. */
+
+       movl    %ebp, %esi
+
+       movl    $ROMSTAGE_STACK, %esp
+       movl    %esp, %ebp
+       pushl   %esi
+       call    copy_and_run
+
+.Lhlt:
+       post_code(POST_DEAD_CODE)
+       hlt
+       jmp     .Lhlt
+
+mtrr_table:
+       /* Fixed MTRRs */
+       .word 0x250, 0x258, 0x259
+       .word 0x268, 0x269, 0x26A
+       .word 0x26B, 0x26C, 0x26D
+       .word 0x26E, 0x26F
+       /* Variable MTRRs */
+       .word 0x200, 0x201, 0x202, 0x203
+       .word 0x204, 0x205, 0x206, 0x207
+       .word 0x208, 0x209, 0x20A, 0x20B
+       .word 0x20C, 0x20D, 0x20E, 0x20F
+       .word 0x210, 0x211, 0x212, 0x213
+mtrr_table_end:
+

diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h
new file mode 100644 (file)
index 0000000..48e0c89
--- /dev/null
+++ b/src/cpu/intel/model_206ax/chip.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations cpu_intel_model_206ax_ops;
+
+/* Magic value used to locate this chip in the device tree */
+#define SPEEDSTEP_APIC_MAGIC 0xACAC
+
+struct cpu_intel_model_206ax_config {
+       u8 disable_acpi;        /* Do not generate CPU ACPI tables */
+
+       u8 pstate_coord_type;   /* Processor Coordination Type */
+
+       int c1_battery;         /* ACPI C1 on Battery Power */
+       int c2_battery;         /* ACPI C2 on Battery Power */
+       int c3_battery;         /* ACPI C3 on Battery Power */
+
+       int c1_acpower;         /* ACPI C1 on AC Power */
+       int c2_acpower;         /* ACPI C2 on AC Power */
+       int c3_acpower;         /* ACPI C3 on AC Power */
+};

diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c
new file mode 100644 (file)
index 0000000..9de94c4
--- /dev/null
+++ b/src/cpu/intel/model_206ax/finalize.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include "model_206ax.h"
+
+static void msr_set_bit(unsigned reg, unsigned bit)
+{
+       msr_t msr = rdmsr(reg);
+
+       if (bit < 32) {
+               if (msr.lo & (1 << bit))
+                       return;
+               msr.lo |= 1 << bit;
+       } else {
+               if (msr.hi & (1 << (bit - 32)))
+                       return;
+               msr.hi |= 1 << (bit - 32);
+       }
+
+       wrmsr(reg, msr);
+}
+
+void intel_model_206ax_finalize_smm(void)
+{
+       msr_set_bit(IA32_FEATURE_CONTROL, 0);
+       msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
+
+       /* Lock AES-NI only if supported */
+       if (cpuid_ecx(1) & (1 << 25))
+               msr_set_bit(MSR_FEATURE_CONFIG, 0);
+
+       msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31);
+       msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31);
+       msr_set_bit(MSR_PKG_POWER_LIMIT, 63);
+       msr_set_bit(MSR_PP0_POWER_LIMIT, 31);
+       msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
+       msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+       msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
+}

diff --git a/src/cpu/intel/model_206ax/microcode-m12206a7_00000025.h b/src/cpu/intel/model_206ax/microcode-m12206a7_00000025.h
new file mode 100644 (file)
index 0000000..229fba2
--- /dev/null
+++ b/src/cpu/intel/model_206ax/microcode-m12206a7_00000025.h
@@ -0,0 +1,611 @@
+//+++
+//     Copyright (c) <1995-2011>, Intel Corporation.
+//     All rights reserved.
+//
+//     Redistribution. Redistribution and use in binary form, without modification, are
+//     permitted provided that the following conditions are met:
+//             .Redistributions must reproduce the above copyright notice and the following
+//     disclaimer in the documentation and/or other materials provided with the
+//     distribution.
+//             .Neither the name of Intel Corporation nor the names of its suppliers may be used
+//     to endorse or promote products derived from this software without specific prior
+//     written permission.
+//             .No reverse engineering, decompilation, or disassembly of this software is
+//     permitted.
+//             ."Binary form" includes any format commonly used for electronic conveyance
+//     which is a reversible, bit-exact translation of binary representation to ASCII or
+//     ISO text, for example, "uuencode."
+//
+//     DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+//     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+//     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+//     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+//     PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+//     OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+//     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+//     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+//     CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+//     STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+//     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+//     ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//---
+/*  Thu Nov 10 10:30:59 CST 2011  */
+/*  m12206a7_00000025.inc  */
+0x00000001,    0x00000025,     0x10112011,     0x000206a7,
+0x6aa14554,    0x00000001,     0x00000012,     0x000023d0,
+0x00002400,    0x00000000,     0x00000000,     0x00000000,
+0x00000000,    0x000000a1,     0x00020001,     0x00000025,
+0x00000000,    0x00000000,     0x20111011,     0x000008d1,
+0x00000001,    0x000206a7,     0x00000000,     0x00000000,
+0x00000000,    0x00000000,     0x00000000,     0x00000000,
+0x00000000,    0x000008d1,     0x00000000,     0x00000000,
+0x00000000,    0x00000000,     0x00000000,     0x00000000,
+0x9d225b45,    0x6ab4c3b0,     0xebba1c32,     0x469a230a,
+0x8a7d6315,    0x2fc24d3e,     0x82506f79,     0x18dbb9d6,
+0x1a7bbeb1,    0x355a1d62,     0x2e7eb594,     0x09f8dea9,
+0x432a49e4,    0xbf520253,     0xdafa4010,     0x893a858a,
+0x766e0efb,    0xd91e196d,     0x838bd2ef,     0xe5146494,
+0xd515f413,    0x29704828,     0xe85598b6,     0xdcbe6c51,
+0x88eabbfa,    0xa1e8909f,     0xd8931721,     0x35386554,
+0x089a78a7,    0xd9914775,     0xd4644748,     0x1556a4dc,
+0xf44448f6,    0xd054d7db,     0xf30f2b7d,     0x5ae223d0,
+0xcbbb48b0,    0x5c8b0383,     0x177de157,     0x9c1e5f73,
+0x2ec28289,    0xd72a7b6c,     0x823b6eb2,     0x35e02171,
+0xba8deae4,    0x06f4d468,     0x13dbafaa,     0x72b419f1,
+0x033385b5,    0x05806920,     0x4c6034cf,     0x9bd117dc,
+0x976e2d04,    0x250330f0,     0x7250b5e1,     0x184980c2,
+0x12a9d7d6,    0x1bc808f9,     0xae79994f,     0xc6f87901,
+0xc0e3132f,    0x671491c5,     0x236cad39,     0x37889d9c,
+0x67f7c3f3,    0x964a6be5,     0xbcced7da,     0x57eeaa6e,
+0x7bca1522,    0x654fee4c,     0x2a1ca5d9,     0xa1803cf3,
+0x00000011,    0x3f96e33b,     0xbcc97e7d,     0xfecb5781,
+0x24a87ac3,    0x281fad3d,     0x6c5d0169,     0x406f3d4b,
+0x1bedf9bf,    0x514f3332,     0xb33e1926,     0x539139d4,
+0x0b5a03bb,    0x7948224c,     0x403919aa,     0xd30c64b2,
+0xb1df420a,    0xbc62cb65,     0x8b036cd8,     0x662064a0,
+0x7381ae61,    0xfb070274,     0x9a3978d9,     0x051c1cbd,
+0x7bcfb857,    0x2c94fcc0,     0x25f643f1,     0xda3d4463,
+0x8aad6318,    0xabd2966c,     0x663d015a,     0x9fe4c504,
+0x43786fce,    0xa1b3dfdc,     0x435783a4,     0x1e44e90a,
+0x85ae6018,    0x9402a6c9,     0x709f4d13,     0x1bdec841,
+0x4840a539,    0xaa446221,     0x27401d2d,     0x1e0d39c6,
+0x6ae8973f,    0xc8b603b8,     0x8044340d,     0x9a4846e1,
+0xf7e68ad9,    0xd2a0cbd1,     0xc64bf2bf,     0x51286697,
+0xf3110b6f,    0x1562e9dc,     0xc682712e,     0x5cfbda8f,
+0x0d575c4f,    0x929f8530,     0x69abd158,     0x41c783e1,
+0xbfe313de,    0x33cbec29,     0xbcbddb8a,     0xe0861b12,
+0x866f3884,    0xf3b79ad6,     0x3415ad37,     0x3a17893c,
+0xb29694df,    0xecd242ce,     0x5d8231ef,     0x5b208f8f,
+0xc781cb94,    0xeb8dc8b8,     0x9d04fd73,     0x4639b3f9,
+0x543fbc28,    0x3957879c,     0xc7f0d4a1,     0x29ac4965,
+0x10f47a96,    0xf7d5b5ce,     0x8ed0c39f,     0x5a36d20f,
+0xff5bd157,    0xf4a3152e,     0xfa9087b4,     0xe4021354,
+0x2b394395,    0x118d8abd,     0xa6ef26da,     0xe47688e5,
+0x15352ccd,    0xa2a1120c,     0xf86a3b13,     0x3453d233,
+0x74d464e9,    0x28cb0910,     0x1c0d9908,     0xf7a672c4,
+0xa725013d,    0xfd618f4a,     0x2035f826,     0x2544d00b,
+0xe6bd2f30,    0xd6e3992f,     0xf7f39f5e,     0x282a3593,
+0x00de27bf,    0x5d0470c2,     0x14473c88,     0xc763ad23,
+0x2ccd5c60,    0x71f0d333,     0x09e8b8cd,     0x716fd1e1,
+0x2dfd1003,    0x006b819f,     0x7b157ad2,     0xa6305470,
+0xcde50f1a,    0x955bc9c8,     0xbe464835,     0xf67f9b33,
+0x21ab56ea,    0xc133d4c6,     0x77d754bf,     0x130877e0,
+0xbd1b247a,    0x7840690d,     0xe6174dd0,     0x61d13bfd,
+0x675ae943,    0x9149e21b,     0xce8ddf65,     0xe06ca163,
+0x33ee3750,    0xa89318e4,     0xa5476a0f,     0x72d15429,
+0x1442d6e5,    0x13f70d65,     0x81923d22,     0x4eefbbc5,
+0x1af2cbf1,    0x052ae881,     0x2fcb621a,     0x44e6c1f6,
+0x10c0c127,    0x6132dbfc,     0x0b3e5d38,     0x18379c7c,
+0x24848ccf,    0xb929cddf,     0xbd0c9549,     0x68d44ac1,
+0xf1a4967b,    0x60d466f9,     0x60a12700,     0x6bdf875f,
+0x2d8255a9,    0x464c149d,     0x32c047ee,     0x5d744d6c,
+0xdf44c2b2,    0xda41f152,     0xb83bd853,     0x3f612ed9,
+0xcecd3f95,    0xde938fc5,     0x2120712d,     0x6e895650,
+0xa5d34947,    0xb5d7459d,     0x13df64d9,     0xf8d40e55,
+0x7f590e01,    0x1724e7cf,     0x5843ee08,     0xdce43dd9,
+0x574cae1c,    0x5ec349e6,     0x56ab1066,     0x7d518ee9,
+0x1f83b1fe,    0xac633b58,     0xcef8a5fd,     0xacf35357,
+0xa93932b1,    0x64e73ca0,     0xb824e2b0,     0xb6c68da4,
+0x287ee847,    0xec1dbf97,     0xd313d2fa,     0x9fe37eec,
+0x281d8559,    0x2fd0c6c7,     0x15e9a89a,     0x273e9932,
+0xf081dec8,    0xa04d5e16,     0x8a3ac66a,     0xe5b25b5c,
+0x4138b7b3,    0xace013c4,     0xe5bee1c8,     0xd9daafd4,
+0x952af837,    0xf28c36bf,     0xcdff2a71,     0xa1cf3b94,
+0x8821440c,    0x3693fab8,     0xd6d2d0d0,     0xa2ccd66d,
+0xe8736467,    0x8a8952f8,     0xe32db4d9,     0x47b71bdf,
+0x620f3c22,    0xdb2922a7,     0x98e5cc6b,     0x905be886,
+0x822feb82,    0xf722cf0c,     0x7a356d80,     0x9c6b3ab6,
+0x19a3cc17,    0x08dfaf09,     0x4c99a23d,     0x0926d99e,
+0xa81577e5,    0xc684495a,     0x359aa743,     0xbc7aa166,
+0xaac2e24d,    0x16110785,     0x8ccc6fbc,     0xfd90cf70,
+0xb34be19c,    0xf57fef0d,     0x9c29c8a7,     0x022c249d,
+0x946cef68,    0xe07b7779,     0x4f6ea6b4,     0xe3a4eef4,
+0xfed31061,    0x96e78ae9,     0x220c0f91,     0x30aca707,
+0xa081c7b9,    0x159dc936,     0x4cbaa290,     0x447910e2,
+0x6ec95f93,    0x3cc3fde8,     0xce2c17a1,     0x4f18c4cb,
+0x025605b1,    0xbce02471,     0x21656693,     0x9368f6cd,
+0x0c19760f,    0xcc35da81,     0x4c5edab1,     0x85a0890e,
+0xbc5b861e,    0x203a23a6,     0xddc7d7ed,     0x0b585825,
+0xec9e7ab2,    0x1f1ad49a,     0xa7444b1f,     0xe77976b4,
+0x99e8c05e,    0x8b04c7c2,     0xb1aeb88b,     0x416d07ac,
+0x5a5689be,    0xe4094686,     0xe048c8e6,     0x2e0259dd,
+0xd2fe1113,    0x6190504b,     0xa0352318,     0x6f0cae7c,
+0x040da641,    0x29fab483,     0x2e354a07,     0xab62c485,
+0xbd787e0a,    0xc345308c,     0xc8ab8568,     0xf75adc1d,
+0x82b55654,    0x6cf29bbf,     0x8786a46e,     0x433c20d2,
+0x9229c1ee,    0x5e8eedf5,     0xab9bb981,     0x1a1a5419,
+0x97994816,    0x010eef10,     0x0172fd65,     0x975b8297,
+0xff6c4377,    0x6fca39f8,     0x13accf88,     0x94f05a02,
+0x5a772f20,    0xfbf97bca,     0x60801139,     0x64cbd0a6,
+0x72512821,    0x0830cb9a,     0x402f033c,     0xd0e2a50d,
+0x7ac45ee3,    0xbae23515,     0xd213695d,     0x72016572,
+0x20651143,    0x3552bc4d,     0xf014ebb1,     0x9aeebedf,
+0xee65d90f,    0x53abd424,     0x841f5383,     0xa43a2e44,
+0xee379480,    0x1638e568,     0x2573aad0,     0x2e935090,
+0xb9dcbe13,    0x9cdc4e30,     0xce8d170c,     0xbc546d14,
+0x18b77a7b,    0x3b652642,     0x79ae26c2,     0x5ab240c2,
+0xf74cfe35,    0x30be64cf,     0x3b5e7456,     0x81be84d1,
+0x12bb10db,    0x573da6b3,     0x83e28efe,     0x395c1512,
+0xf11928ee,    0xe64d50b5,     0x6f714c8b,     0xb3393f61,
+0x13b6b2f4,    0x0ab3b2aa,     0x5cada4c7,     0x19dfb423,
+0xe7b1c195,    0x47ee32d7,     0x03ab86bd,     0x08b8a8c6,
+0xdc7a6cdf,    0x3e5b4f68,     0x9ea0e297,     0x13193f7e,
+0x8fe31f30,    0x6118a11c,     0xc0762196,     0x9fd26fc0,
+0x9f515662,    0x5a1abb55,     0x5e434855,     0x4c6af26a,
+0x163cf95d,    0xa54ee076,     0xb41a0c1a,     0xf8a8affb,
+0x69db8391,    0xa7204db3,     0x86dc9909,     0x25ba82c5,
+0x04154f7a,    0xa191c23a,     0x6f3ee8ed,     0x55162d2b,
+0x14f9478d,    0xc717fb1c,     0x91408cdd,     0x7a87a50d,
+0x44d10ceb,    0xd04b5347,     0x82a3b3ce,     0x07e3998e,
+0x1dafee6f,    0x77c24219,     0x4ff885ef,     0xd994194a,
+0xfeff078a,    0x20f4b18a,     0x529676bd,     0x17738de7,
+0x01f8491b,    0xe31d2728,     0x34e5155b,     0x87120d79,
+0xb96f615c,    0xd6d15cd2,     0x4a1f66a8,     0xa0b37474,
+0x0713a36e,    0x70df574c,     0xe6015de6,     0x5f50f282,
+0xbd828397,    0xda75bb9f,     0x13e35581,     0x5bb84a7f,
+0xf66216ca,    0xac35d098,     0xff3a8f78,     0xb43a2d55,
+0xcb820994,    0x74f97ab1,     0x0ebb37aa,     0x5457d670,
+0xc7617908,    0x5f0ad21e,     0xeb8a4b9f,     0x0c678bc7,
+0x705cb6ce,    0xc2b3ef2a,     0x89c0c723,     0xab4399a9,
+0xc2216b3e,    0x9adda9ee,     0x82c7bfa0,     0x9d56f661,
+0x0f715ee5,    0x627d8182,     0x306a00b9,     0x2d9c259c,
+0x251b933c,    0x67fbe9e7,     0x103e2322,     0x29d1c68a,
+0x8f019d2f,    0x077e80b4,     0xbbbd9c2a,     0x266f4f74,
+0x96b32213,    0x5019c61d,     0x4a59782c,     0x8810efb7,
+0xfa55eaae,    0xbabe0b82,     0x956cae7f,     0xf016453c,
+0x255e2b2a,    0x1b805b17,     0x9c9b51cb,     0x0eaafa33,
+0x45fb3835,    0x2c2070d2,     0x70005da8,     0xf39c43b4,
+0x78c372ac,    0xa6fe8b80,     0x473ab824,     0x758cf1c0,
+0x8d012210,    0x8e26dc51,     0xf8f88450,     0xd1ffe2b8,
+0xa36a40ff,    0xbed11609,     0xaaa32039,     0xbc6ee3b5,
+0x36f84b62,    0xbacf3880,     0x26af8917,     0x9c6cb47f,
+0xa2a70b0b,    0x4b003af3,     0x83d9d354,     0x7aa355ce,
+0x75ec5db9,    0xa4384855,     0x0e8ac979,     0xa55a370e,
+0xbb3af0dd,    0x42153802,     0x32531de8,     0xe57570a8,
+0xe490a98c,    0xa9a910ee,     0x453953a6,     0x1348535e,
+0xb73595c5,    0x89bcd5dd,     0x0c68cc61,     0x5e880831,
+0x65cf0e50,    0xa4ccd3ac,     0xe61f9f5f,     0x01b610b0,
+0x7387c5aa,    0x6458654f,     0x35bbb16c,     0x90e9e91c,
+0xc56957f2,    0xaadb7f70,     0x07732d08,     0xce4ad932,
+0x7fa3e135,    0x31a83cad,     0x43271bcf,     0xa74b4eab,
+0x4f483674,    0x9cc84d3c,     0x7562feb5,     0x0b445b18,
+0xc1b1b769,    0xcfd31f23,     0xdf6f0843,     0x56789e7b,
+0x0ed7daf8,    0xe28e3610,     0x0b516cac,     0x5d805128,
+0xe430861d,    0x993bc596,     0xd85434cb,     0x740f7d13,
+0xe91e0d47,    0xe518a80f,     0xf729e13a,     0xd7fde910,
+0x838697c0,    0xf25c49b6,     0x7b9a6956,     0x70c8cb88,
+0xe5befc43,    0x84e0cd72,     0x2799a866,     0x62f8241e,
+0xa13dd267,    0x675404c0,     0x107995e6,     0xd5a44abb,
+0xe8b14bc2,    0x299705c4,     0xe691d679,     0x2a72edfa,
+0x353adfa6,    0x89aa4a58,     0x22247d90,     0x5a97fc14,
+0x09843de7,    0x4537f188,     0x7cd7cb9c,     0x7395900f,
+0xa178c352,    0x96fff660,     0x3b1d36a9,     0x7872cd2c,
+0x4e8e86ac,    0x6d0d129e,     0x366d1810,     0x84e4869f,
+0x9d73317d,    0xfc92685c,     0x6b3ba9cf,     0x573d9a1f,
+0xa5e5a1bd,    0x29620cbd,     0xd7a53209,     0x156f5151,
+0x58a48a3b,    0x91e00b57,     0xf68f1270,     0xb0911b95,
+0xf33c953b,    0x7402498a,     0x7cd9d9b5,     0x7f306060,
+0x08de3b88,    0x4e1b3dfa,     0xb7f0044f,     0x1e215ef7,
+0xaa6a9016,    0xdc45a3f7,     0x6a5266f9,     0x44f25fa1,
+0x64d10347,    0xf518fca6,     0x0043e846,     0x9f768875,
+0x2338de08,    0xecb485e7,     0xe53abf19,     0xdb887ab5,
+0xb61c7a2e,    0x33ff900b,     0xf8323567,     0x34eaf959,
+0x861b3ee3,    0xb416d9a8,     0x38073e63,     0x2f05c10f,
+0x84159c49,    0xaeb0462f,     0x82c74fd4,     0x471c5d20,
+0x6c6b77b9,    0xd9e07c77,     0xe49a020b,     0x9b15469b,
+0x53a1dd1d,    0xf372f68c,     0xc42b3729,     0xee64f017,
+0x06969bc7,    0xbc538ee3,     0xec79f4dd,     0xa948e000,
+0x77e45852,    0xeba3a61e,     0x21d74dc6,     0x62c47642,
+0xa12854b5,    0x10359530,     0x181703f1,     0xae4b7bf7,
+0x567633f7,    0x585012e9,     0x74e8837e,     0xf6750d5c,
+0x31edb0be,    0xa1fbe771,     0x1414bb70,     0x5f451222,
+0x56b71fa1,    0x42fe4e54,     0xaafb543f,     0x8e861547,
+0x8281a64c,    0x9f316107,     0x156bd5db,     0xd6b8e0e9,
+0x419fe658,    0x6897a516,     0x98d60208,     0xbbf31e8a,
+0x82e78e6f,    0xbb08b49a,     0x5b5fdeb5,     0xb3a9e8da,
+0xbfc6b353,    0xfbcdcf56,     0x20732e73,     0x8026f595,
+0x99cabead,    0xa831e2aa,     0x6a70356d,     0xa1566f0c,
+0x2340d50a,    0xd9e99b6f,     0xddd31fec,     0x79479c00,
+0x66c993e9,    0x3e5a6bbb,     0xc973c063,     0xcaf97f9a,
+0x94726d54,    0x367a657d,     0x084244e0,     0xea281246,
+0x8deca641,    0xca9812de,     0x9e6c0227,     0x6572f207,
+0x3d9282ad,    0x9a5888f8,     0x437fb2f2,     0xa59fd791,
+0xf46fad2f,    0x91b04878,     0xdbe527b9,     0xddf11081,
+0xfe7aab5d,    0x535d00d2,     0x6281997a,     0xbdf3a7fb,
+0x2b00033a,    0xfa6eee8c,     0xdf2ddf1c,     0x67a47291,
+0x5fcc2258,    0x9718099f,     0xb667495e,     0x154f12da,
+0xcade895c,    0x3c5a8529,     0x06727bf8,     0x28ece4f9,
+0x881481f3,    0xa5299ac6,     0x7602f0ed,     0x9cc90020,
+0x0e6e42bc,    0x749c85a6,     0x8fff0e9f,     0x75e4e9a4,
+0xd7d1b424,    0xec83f7d6,     0x229a883e,     0x35790b38,
+0x7f973e98,    0x1198edd9,     0x15349ffa,     0x3a5224ad,
+0x135f46e2,    0xa62b3da4,     0x3924c952,     0xcf193aed,
+0x1de1ce38,    0x57d72478,     0x605c1961,     0x45f76230,
+0x55f8d7b8,    0xe26499d8,     0xd214b4b8,     0xa9939f45,
+0x36610bd1,    0x65a3d400,     0xce82c54b,     0x2e4d3e01,
+0x07fdb9ec,    0xda246930,     0x6dcf119a,     0x80904d6c,
+0xe4950422,    0xe5e8bee8,     0x19e9d0d5,     0xacecf91b,
+0x0f4edefe,    0xc1d98382,     0x7e22975d,     0x3cc17318,
+0x036df2e6,    0x8811ba2d,     0xf9a75154,     0xeb65faa4,
+0xad7b4294,    0xae8be741,     0x23009705,     0xc3ec4131,
+0xf1257f3a,    0x7472f715,     0x6e6a9a61,     0x4f54f585,
+0xdc200841,    0x05164b24,     0x633b0c72,     0x7abd83a7,
+0xc32b4865,    0x7fafd317,     0x835395a1,     0xa1989b58,
+0x3638fae8,    0xcfcb3e12,     0x8370e894,     0x39ff005a,
+0xb61a1923,    0x047e0336,     0x5a7e61bb,     0x79bf462e,
+0xb978d8e2,    0x61036c49,     0xc4590141,     0x6a1b3cc8,
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+0x6a2fe3ec,    0x294c2bde,     0x12861212,     0xddff6bfb,
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+0x1ce7be10,    0x55d7acf8,     0x015c32a7,     0x5a3d7795,
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+0x483048d2,    0xe3ee2145,     0x029eba71,     0x2a6efdb8,
+0x7e629d7c,    0xe7458f31,     0xd2edd71b,     0xa265588c,
+0xee3a7a3d,    0xc3f6a74d,     0xb55fbbb2,     0xac3dc469,
+0x350e24ac,    0xfdfb094c,     0xc6760d93,     0x014aad92,
+0x4bf74e51,    0x9ab932af,     0xc600d00f,     0x5dd0c96d,
+0x6b081fbe,    0xecba3e1c,     0x19abcf55,     0x46905ea0,
+0x41ff2a8f,    0x9305e1c0,     0xdbfa1df1,     0x8100370e,
+0x0df9b3df,    0x09763efc,     0x60447b79,     0xb64eb88a,
+0xe4c706de,    0x2dadc973,     0xf6bc6357,     0x7395486a,
+0xf15aae31,    0x1daca268,     0xa5b8395f,     0x127bcb11,
+0xe84c9715,    0xe0417152,     0xc3d8520e,     0x0bdcbb00,
+0xf3daba82,    0xe1925ffb,     0x3526a2e8,     0xda189c78,
+0xa32bf2fc,    0xe7de02ab,     0x2f344593,     0x07b916dd,
+0xe2d46b57,    0x83921885,     0x6f066626,     0x7ce5ab67,
+0xebcaf5de,    0xbb0f6b00,     0x6d1faffb,     0x1eff0018,
+0x2debe6bc,    0x57d003b3,     0x3a3f5f80,     0xec6b7c0e,
+0x9f1dd663,    0xbebdbf56,     0x98e5774e,     0xb7a29504,
+0x5166a8c5,    0xaf7ce332,     0xca5e70c5,     0xfe235309,
+0x9c23f707,    0x99b08cc4,     0x2fe1edd1,     0xba36918f,
+0x262dd395,    0x423edc8c,     0x801e8f1f,     0x5b4cc6c5,
+0x3fcdf7f4,    0x5a490992,     0xd4006978,     0x977e2f86,
+0x6311af7b,    0x06bb2412,     0x2be72eb1,     0x5706b252,
+0xa000c75b,    0xe3ea5cff,     0xc9208730,     0xd9e369fb,
+0x1aed50e2,    0x8916d70d,     0x87f01eb6,     0x663b8f67,
+0x3dc68ee3,    0x5197b72b,     0xddb19fb8,     0x6839be2a,
+0x99fcfc25,    0x5542f267,     0xa922eea9,     0xc9ae9d93,
+0xcf8a9d64,    0x76bfeec4,     0xacbcd4c6,     0x81960ab0,
+0x7b24eb81,    0x8e8cad81,     0xfb2c1362,     0x9ccf1224,
+0x16d2c962,    0x18f7d553,     0x2a7f9c1e,     0x3678f775,
+0x1210588a,    0xe1644769,     0x3dd29db7,     0xbe9daa2c,
+0xe9c4e13a,    0x8d9de528,     0x19c3075e,     0x68a336d4,
+0x0ba157f3,    0xe3780ca6,     0x69c54c28,     0x9f96bb00,
+0xa78204e9,    0x1c8627cf,     0x2fd52aa9,     0x957b15ed,
+0xd3d61e03,    0x658cea71,     0x42d77750,     0x0c0755bc,
+0xde372a0d,    0x0d3687d7,     0xc04c56f6,     0xc3882257,
+0x98fd462c,    0xb65fac1e,     0x01b5ecab,     0xd554413d,
+0xb4beec40,    0xb4caab5e,     0xdeee4085,     0xd1b0500c,
+0x6845de70,    0x5a06e889,     0xfc89a4a7,     0xedbfd435,
+0xac039058,    0x9c1acd2f,     0x876fbfac,     0x9d8b83f3,
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+0x0ee62d27,    0x5d93a3f4,     0x7f13dc77,     0xd4ec7c79,
+0xd72a35c8,    0xb84ba058,     0x21e1d1ad,     0xbcf9c0fe,
+0x106fb166,    0x84ff4a86,     0x3b2d960f,     0x4cf3ab0e,
+0x65d25f76,    0xdcda7e29,     0xc444ddc8,     0xe97096dc,
+0xbfe1815c,    0x25b9dec5,     0x7aed80de,     0x6cbb6f7a,
+0x2daf76b7,    0x249ee47f,     0xdc6e770d,     0xa5a02e7d,
+0xd019d0d7,    0x17feead1,     0xbf80c1f6,     0x83644ac0,
+0x412f1ce4,    0x59c1de41,     0x1a47db26,     0x8848ab89,
+0xc2c17745,    0x31183c80,     0x9bb13cc3,     0x6da9c349,
+0x414b378d,    0xd58df4ba,     0x41f5ca37,     0x02a5162f,
+0x2843bb24,    0xbd2bb85a,     0x0b2c6e81,     0x2d50fe1d,
+0xc67b2c07,    0x630ce2b3,     0x73274d84,     0x3b4ba900,
+0x5e672d3c,    0x7ef23846,     0x81036625,     0x380b3d3b,
+0x391470b1,    0x5b3dcbed,     0x63038751,     0xa0c7aed8,
+0xc185b677,    0x516b8170,     0xbf79f025,     0x2b4c9edb,
+0x29354139,    0x9deabe33,     0x2838f581,     0x0574281f,
+0xc1267da2,    0x0c070755,     0x6832a8b9,     0x57436eed,
+0xe604c645,    0x4f13172a,     0x3227ac12,     0xf6b78267,
+0xbbd5d003,    0x5f8ae7ed,     0x74b6682c,     0x356b9e81,
+0x82703c20,    0x8ccf1f78,     0xa6b79197,     0x434d5316,
+0x1ba0853a,    0xe6ae4829,     0x1193ed0a,     0xa2d171f0,
+0x4f565a15,    0xf78ea4af,     0xa9a27e39,     0x30a45316,
+0xc005a8f6,    0x79a23d86,     0x07edcbe3,     0x3b76806b,
+0x3df6268a,    0xb0f33186,     0x2fd51855,     0xb34efefe,
+0xa24ce423,    0x6c62d711,     0x335c7252,     0x0d2ddcff,
+0x64485539,    0x00c8a89e,     0x4827ad2d,     0x01de50f4,
+0x593a9a38,    0xee90b919,     0xf523cd40,     0x97ed7009,
+0x1038e6b0,    0x95931966,     0xaaac22b9,     0xef1b9915,
+0x23f6d33c,    0xe417a460,     0x4e9b59c2,     0x3fd38b75,
+0x7ceabd08,    0x8279d672,     0xf24936e8,     0x668630f8,
+0x3cb0ddc0,    0x56c56418,     0x91221ef8,     0xc8926c65,
+0x4d7436b6,    0xc06b5b1e,     0xdea496b1,     0x4fa4c971,
+0xeea15028,    0x7aead456,     0x1329b826,     0xcf9a4d4f,
+0xabd69aba,    0x9dd78c2e,     0x5e9782ff,     0x563f3cb0,
+0xfc2db55c,    0xb2d5f64b,     0x9478caeb,     0x7409ae76,
+0xc4690516,    0xb12bb352,     0xad5283c7,     0x608e7a23,
+0xc8b4b59a,    0x0da06391,     0x9a6ccd78,     0xe4af91ad,
+0xb156f74a,    0x790b21dd,     0x6ce9970b,     0x46e89ac1,
+0x07815d28,    0x1f2fc3ac,     0x690cd168,     0x6ae48bb4,
+0x1ed48c84,    0xe5f121a3,     0x49a762cf,     0xc5e8fd6a,
+0x75d45162,    0xf49c2c5e,     0xd161eb4a,     0xb6351b73,
+0xc2605562,    0xb097aa9d,     0x114421ee,     0xf93baf78,
+0x82b9b2ab,    0x0374be4d,     0xd715656b,     0x3524549f,
+0xb37dc283,    0xfa8308d0,     0x3f69f2be,     0x238bc31e,
+0x839f3f68,    0x0639b8d7,     0xa8cdbe8e,     0xd15c7cb3,
+0x0a31ec87,    0x39a57286,     0x7c3ffef5,     0x461d70b2,
+0x7d1e8a90,    0x629b803f,     0x351b6cb8,     0x255391c2,
+0x07215420,    0x5e1aef8c,     0xa3b48e74,     0x8fa78c73,
+0xb6fab65c,    0xb13cb77f,     0x5bd44236,     0x31cbeab2,
+0x9f68d29a,    0x207a2b05,     0x668ac8a7,     0xb6de6033,
+0x3d2a4173,    0x04a2543a,     0x559b1b7c,     0x5e9116d4,
+0x5cb3ee57,    0x4a47f644,     0x90be9381,     0xbccc9cd2,
+0x3160e0d5,    0xed791f87,     0xdd9da7a8,     0x3e6d398b,
+0x6a68ad78,    0x418974ef,     0xfd010940,     0x8bed7055,
+0xf21e4d13,    0xac8160b9,     0x85f10ecb,     0xd637b0e2,
+0x987dd54e,    0x9835f225,     0xdbee940c,     0x9a34e16d,
+0x15fcfb54,    0x6720e48c,     0x9a42e266,     0x31eb0270,
+0x714dee04,    0xbcd417d8,     0xedf7757e,     0x099c4e89,
+0xee3e6c2e,    0x6246d530,     0xfbdad1d6,     0xbbe301a3,
+0xe08f829c,    0xa3c7d9c4,     0xe753a1dd,     0xf1466da1,
+0xa1e353a7,    0x33828150,     0x267d4059,     0x458bd806,
+0xac0ed307,    0x2079bf7c,     0xb25200db,     0x9dfd338c,
+0x0b94573e,    0x8188fa16,     0x9e641b63,     0xafa2a60c,
+0x61e5f820,    0x63a38983,     0x172d3a6f,     0xc98a34b2,
+0x532b56f5,    0x1883cb1a,     0x93ba9692,     0x7d85d109,
+0xd20ffd1a,    0xcc6e9937,     0xb3813eb1,     0xea7e1b45,
+0xf1e09c71,    0x35aa1ab9,     0xbd2d43d7,     0xc53a07ef,
+0xf3fa3fd6,    0xf3cd1e20,     0x5e620481,     0xd7bec1b0,
+0xc7d3caf6,    0xe9eae29f,     0x19c5b2c1,     0x940e3186,
+0x200f0a30,    0xbaf511b1,     0x103cb39c,     0x3f46b067,
+0xba6c5e9a,    0xc32b5592,     0x393e8503,     0x7ea29847,
+0x04d4a493,    0x18fc67d5,     0xea4ff94e,     0xc0281d5e,
+0xaeeaae85,    0x13be6b70,     0xa1bc8be4,     0xa1edbe06,
+0x572b8b35,    0x3baca7c5,     0x06ac9591,     0x8309b11d,
+0x7f381b05,    0xb16dd9b2,     0xf9b5d898,     0xb2e04c3a,
+0xed89b7dd,    0xd30e7e33,     0x4ac6cb61,     0xd2c50800,
+0x6554ae61,    0xa263efe2,     0x666244c3,     0xb6aaa480,
+0xcb4344ee,    0x31cf3efa,     0x14a4a476,     0xf6804765,
+0xaca47c23,    0x7e15ae69,     0xaffade7d,     0x693a6ff9,
+0x3f0f22c0,    0xe6135bcb,     0xf0632009,     0x06fa2abb,
+0xad0c1085,    0x3ce130b3,     0x70001594,     0xd80c452b,
+0x486c9d1f,    0x93b94966,     0x81612f95,     0x7573faea,
+0x1568ddb9,    0x3c1d26e5,     0x0a5d7b45,     0x5ea78077,
+0x1c5491f9,    0x24363c4b,     0x54b8e62a,     0xb86697e6,
+0x18750c76,    0xa355cee8,     0x9c09de46,     0xb022ec2b,
+0xfa142272,    0xd1e1dcce,     0xc7c2f6c9,     0xd8e72fc1,

diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
new file mode 100644 (file)
index 0000000..3343d11
--- /dev/null
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CPU_INTEL_MODEL_206AX_H
+#define _CPU_INTEL_MODEL_206AX_H
+
+/* SandyBridge bus clock is fixed at 100MHz */
+#define SANDYBRIDGE_BCLK               100
+
+#define IA32_FEATURE_CONTROL           0x3a
+#define  CPUID_VMX                     (1 << 5)
+#define  CPUID_SMX                     (1 << 6)
+#define MSR_FEATURE_CONFIG             0x13c
+#define IA32_PLATFORM_DCA_CAP          0x1f8
+#define IA32_MISC_ENABLE               0x1a0
+#define IA32_PERF_CTL                  0x199
+#define IA32_THERM_INTERRUPT           0x19b
+#define IA32_ENERGY_PERFORMANCE_BIAS   0x1b0
+#define  ENERGY_POLICY_PERFORMANCE     0
+#define  ENERGY_POLICY_NORMAL          6
+#define  ENERGY_POLICY_POWERSAVE       15
+#define IA32_PACKAGE_THERM_INTERRUPT   0x1b2
+#define MSR_LT_LOCK_MEMORY             0x2e7
+#define IA32_MC0_STATUS                0x401
+
+#define MSR_PIC_MSG_CONTROL            0x2e
+#define MSR_PLATFORM_INFO              0xce
+#define  PLATFORM_INFO_SET_TDP         (1 << 29)
+#define MSR_PMG_CST_CONFIG_CONTROL     0xe2
+#define MSR_PMG_IO_CAPTURE_BASE                0xe4
+
+#define MSR_MISC_PWR_MGMT              0x1aa
+#define  MISC_PWR_MGMT_EIST_HW_DIS     (1 << 0)
+#define MSR_TURBO_RATIO_LIMIT          0x1ad
+#define MSR_POWER_CTL                  0x1fc
+
+#define MSR_PKGC3_IRTL                 0x60a
+#define MSR_PKGC6_IRTL                 0x60b
+#define MSR_PKGC7_IRTL                 0x60c
+#define  IRTL_VALID                    (1 << 15)
+#define  IRTL_1_NS                     (0 << 10)
+#define  IRTL_32_NS                    (1 << 10)
+#define  IRTL_1024_NS                  (2 << 10)
+#define  IRTL_32768_NS                 (3 << 10)
+#define  IRTL_1048576_NS               (4 << 10)
+#define  IRTL_33554432_NS              (5 << 10)
+#define  IRTL_RESPONSE_MASK            (0x3ff)
+
+/* long duration in low dword, short duration in high dword */
+#define MSR_PKG_POWER_LIMIT            0x610
+#define  PKG_POWER_LIMIT_MASK          0x7fff
+#define  PKG_POWER_LIMIT_EN            (1 << 15)
+#define  PKG_POWER_LIMIT_CLAMP         (1 << 16)
+#define  PKG_POWER_LIMIT_TIME_SHIFT    17
+#define  PKG_POWER_LIMIT_TIME_MASK     0x7f
+
+#define MSR_PP0_CURRENT_CONFIG         0x601
+#define  PP0_CURRENT_LIMIT             (112 << 3) /* 112 A */
+#define MSR_PP1_CURRENT_CONFIG         0x602
+#define  PP1_CURRENT_LIMIT             (35 << 3) /* 35 A */
+#define MSR_PKG_POWER_SKU_UNIT         0x606
+#define MSR_PKG_POWER_SKU              0x614
+#define MSR_PP0_POWER_LIMIT            0x638
+#define MSR_PP1_POWER_LIMIT            0x640
+
+/* P-state configuration */
+#define PSS_MAX_ENTRIES                        8
+#define PSS_RATIO_STEP                 2
+#define PSS_LATENCY_TRANSITION         10
+#define PSS_LATENCY_BUSMASTER          10
+
+#ifdef __SMM__
+/* Lock MSRs */
+void intel_model_206ax_finalize_smm(void);
+#else
+/* Configure power limits for turbo mode */
+void set_power_limits(u8 power_limit_1_time);
+#endif
+
+#endif

diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
new file mode 100644 (file)
index 0000000..874ce4d
--- /dev/null
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -0,0 +1,558 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/turbo.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/name.h>
+#include <pc80/mc146818rtc.h>
+#include <usbdebug.h>
+#include "model_206ax.h"
+
+/*
+ * List of suported C-states in this processor
+ *
+ * Latencies are typical worst-case package exit time in uS
+ * taken from the SandyBridge BIOS specification.
+ */
+static acpi_cstate_t cstate_map[] = {
+       {       /* 0: C0 */
+       },{     /* 1: C1 */
+               .latency = 1,
+               .power = 1000,
+               .resource = {
+                       .addrl = 0x00,  /* MWAIT State 0 */
+                       .space_id = ACPI_ADDRESS_SPACE_FIXED,
+                       .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+                       .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+                       .resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+               }
+       },
+       {       /* 2: C1E */
+               .latency = 1,
+               .power = 1000,
+               .resource = {
+                       .addrl = 0x01,  /* MWAIT State 0 Sub-state 1 */
+                       .space_id = ACPI_ADDRESS_SPACE_FIXED,
+                       .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+                       .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+                       .resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+               }
+       },
+       {       /* 3: C3 */
+               .latency = 63,
+               .power = 500,
+               .resource = {
+                       .addrl = 0x10,  /* MWAIT State 1 */
+                       .space_id = ACPI_ADDRESS_SPACE_FIXED,
+                       .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+                       .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+                       .resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+               }
+       },
+       {       /* 4: C6 */
+               .latency = 87,
+               .power = 350,
+               .resource = {
+                       .addrl = 0x20,  /* MWAIT State 2 */
+                       .space_id = ACPI_ADDRESS_SPACE_FIXED,
+                       .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+                       .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+                       .resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+               }
+       },
+       {       /* 5: C7 */
+               .latency = 90,
+               .power = 200,
+               .resource = {
+                       .addrl = 0x30,  /* MWAIT State 3 */
+                       .space_id = ACPI_ADDRESS_SPACE_FIXED,
+                       .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+                       .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+                       .resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+               }
+       },
+       {       /* 6: C7S */
+               .latency = 90,
+               .power = 200,
+               .resource = {
+                       .addrl = 0x31,  /* MWAIT State 3 Sub-state 1 */
+                       .space_id = ACPI_ADDRESS_SPACE_FIXED,
+                       .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+                       .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+                       .resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+               }
+       },
+       { 0 }
+};
+
+static const uint32_t microcode_updates[] = {
+       #include "x06_microcode.h"
+};
+
+static void enable_vmx(void)
+{
+       struct cpuid_result regs;
+       msr_t msr;
+       int enable = CONFIG_ENABLE_VMX;
+
+       msr = rdmsr(IA32_FEATURE_CONTROL);
+
+       if (msr.lo & (1 << 0)) {
+               printk(BIOS_ERR, "VMX is locked, so enable_vmx will do nothing\n");
+               /* VMX locked. If we set it again we get an illegal
+                * instruction
+                */
+               return;
+       }
+
+       regs = cpuid(1);
+       printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling");
+       if (regs.ecx & CPUID_VMX) {
+               if (enable)
+                       msr.lo |= (1 << 2);
+               else
+                       msr.lo &= ~(1 << 2);
+
+               if (regs.ecx & CPUID_SMX) {
+                       if (enable)
+                               msr.lo |= (1 << 1);
+                       else
+                               msr.lo &= ~(1 << 1);
+               }
+       }
+
+       wrmsr(IA32_FEATURE_CONTROL, msr);
+}
+
+/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
+static const u8 power_limit_time_sec_to_msr[] = {
+       [0]   = 0x00,
+       [1]   = 0x0a,
+       [2]   = 0x0b,
+       [3]   = 0x4b,
+       [4]   = 0x0c,
+       [5]   = 0x2c,
+       [6]   = 0x4c,
+       [7]   = 0x6c,
+       [8]   = 0x0d,
+       [10]  = 0x2d,
+       [12]  = 0x4d,
+       [14]  = 0x6d,
+       [16]  = 0x0e,
+       [20]  = 0x2e,
+       [24]  = 0x4e,
+       [28]  = 0x6e,
+       [32]  = 0x0f,
+       [40]  = 0x2f,
+       [48]  = 0x4f,
+       [56]  = 0x6f,
+       [64]  = 0x10,
+       [80]  = 0x30,
+       [96]  = 0x50,
+       [112] = 0x70,
+       [128] = 0x11,
+};
+
+/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
+static const u8 power_limit_time_msr_to_sec[] = {
+       [0x00] = 0,
+       [0x0a] = 1,
+       [0x0b] = 2,
+       [0x4b] = 3,
+       [0x0c] = 4,
+       [0x2c] = 5,
+       [0x4c] = 6,
+       [0x6c] = 7,
+       [0x0d] = 8,
+       [0x2d] = 10,
+       [0x4d] = 12,
+       [0x6d] = 14,
+       [0x0e] = 16,
+       [0x2e] = 20,
+       [0x4e] = 24,
+       [0x6e] = 28,
+       [0x0f] = 32,
+       [0x2f] = 40,
+       [0x4f] = 48,
+       [0x6f] = 56,
+       [0x10] = 64,
+       [0x30] = 80,
+       [0x50] = 96,
+       [0x70] = 112,
+       [0x11] = 128,
+};
+
+/*
+ * Configure processor power limits if possible
+ * This must be done AFTER set of BIOS_RESET_CPL
+ */
+void set_power_limits(u8 power_limit_1_time)
+{
+       msr_t msr = rdmsr(MSR_PLATFORM_INFO);
+       msr_t limit;
+       unsigned power_unit;
+       unsigned tdp, min_power, max_power, max_time;
+       u8 power_limit_1_val;
+
+       if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
+               return;
+
+       if (!(msr.lo & PLATFORM_INFO_SET_TDP))
+               return;
+
+       /* Get units */
+       msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
+       power_unit = 2 << ((msr.lo & 0xf) - 1);
+
+       /* Get power defaults for this SKU */
+       msr = rdmsr(MSR_PKG_POWER_SKU);
+       tdp = msr.lo & 0x7fff;
+       min_power = (msr.lo >> 16) & 0x7fff;
+       max_power = msr.hi & 0x7fff;
+       max_time = (msr.hi >> 16) & 0x7f;
+
+       printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit);
+
+       if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
+               power_limit_1_time = power_limit_time_msr_to_sec[max_time];
+
+       if (min_power > 0 && tdp < min_power)
+               tdp = min_power;
+
+       if (max_power > 0 && tdp > max_power)
+               tdp = max_power;
+
+       power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
+
+       /* Set long term power limit to TDP */
+       limit.lo = 0;
+       limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
+       limit.lo |= PKG_POWER_LIMIT_EN;
+       limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
+               PKG_POWER_LIMIT_TIME_SHIFT;
+
+       /* Set short term power limit to 1.25 * TDP */
+       limit.hi = 0;
+       limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
+       limit.hi |= PKG_POWER_LIMIT_EN;
+       /* Power limit 2 time is only programmable on SNB EP/EX */
+
+       wrmsr(MSR_PKG_POWER_LIMIT, limit);
+}
+
+static void configure_c_states(void)
+{
+       msr_t msr;
+
+       msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+       msr.lo |= (1 << 28);    // C1 Auto Undemotion Enable
+       msr.lo |= (1 << 27);    // C3 Auto Undemotion Enable
+       msr.lo |= (1 << 26);    // C1 Auto Demotion Enable
+       msr.lo |= (1 << 25);    // C3 Auto Demotion Enable
+       msr.lo &= ~(1 << 10);   // Disable IO MWAIT redirection
+       msr.lo |= 7;            // No package C-state limit
+       wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+
+       msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);
+       msr.lo &= ~0x7ffff;
+       msr.lo |= (PMB0_BASE + 4);      // LVL_2 base address
+       msr.lo |= (2 << 16);            // CST Range: C7 is max C-state
+       wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr);
+
+       msr = rdmsr(MSR_MISC_PWR_MGMT);
+       msr.lo &= ~(1 << 0);    // Enable P-state HW_ALL coordination
+       wrmsr(MSR_MISC_PWR_MGMT, msr);
+
+       msr = rdmsr(MSR_POWER_CTL);
+       msr.lo |= (1 << 18);    // Enable Energy Perf Bias MSR 0x1b0
+       msr.lo |= (1 << 1);     // C1E Enable
+       msr.lo |= (1 << 0);     // Bi-directional PROCHOT#
+       wrmsr(MSR_POWER_CTL, msr);
+
+       /* C3 Interrupt Response Time Limit */
+       msr.hi = 0;
+       msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
+       wrmsr(MSR_PKGC3_IRTL, msr);
+
+       /* C6 Interrupt Response Time Limit */
+       msr.hi = 0;
+       msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
+       wrmsr(MSR_PKGC6_IRTL, msr);
+
+       /* C7 Interrupt Response Time Limit */
+       msr.hi = 0;
+       msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
+       wrmsr(MSR_PKGC7_IRTL, msr);
+
+       /* Primary Plane Current Limit */
+       msr = rdmsr(MSR_PP0_CURRENT_CONFIG);
+       msr.lo &= ~0x1fff;
+       msr.lo |= PP0_CURRENT_LIMIT;
+       wrmsr(MSR_PP0_CURRENT_CONFIG, msr);
+
+       /* Secondary Plane Current Limit */
+       msr = rdmsr(MSR_PP1_CURRENT_CONFIG);
+       msr.lo &= ~0x1fff;
+       msr.lo |= PP1_CURRENT_LIMIT;
+       wrmsr(MSR_PP1_CURRENT_CONFIG, msr);
+}
+
+static void configure_misc(void)
+{
+       msr_t msr;
+
+       msr = rdmsr(IA32_MISC_ENABLE);
+       msr.lo |= (1 << 0);       /* Fast String enable */
+       msr.lo |= (1 << 3);       /* TM1/TM2/EMTTM enable */
+       msr.lo |= (1 << 16);      /* Enhanced SpeedStep Enable */
+       wrmsr(IA32_MISC_ENABLE, msr);
+
+       /* Disable Thermal interrupts */
+       msr.lo = 0;
+       msr.hi = 0;
+       wrmsr(IA32_THERM_INTERRUPT, msr);
+
+       /* Enable package critical interrupt only */
+       msr.lo = 1 << 4;
+       msr.hi = 0;
+       wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
+}
+
+static void enable_lapic_tpr(void)
+{
+       msr_t msr;
+
+       msr = rdmsr(MSR_PIC_MSG_CONTROL);
+       msr.lo &= ~(1 << 10);   /* Enable APIC TPR updates */
+       wrmsr(MSR_PIC_MSG_CONTROL, msr);
+}
+
+static void configure_dca_cap(void)
+{
+       struct cpuid_result cpuid_regs;
+       msr_t msr;
+
+       /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
+       cpuid_regs = cpuid(1);
+       if (cpuid_regs.ecx & (1 << 18)) {
+               msr = rdmsr(IA32_PLATFORM_DCA_CAP);
+               msr.lo |= 1;
+               wrmsr(IA32_PLATFORM_DCA_CAP, msr);
+       }
+}
+
+static void set_max_ratio(void)
+{
+       msr_t msr;
+
+       /* Platform Info bits 15:8 give max ratio */
+       msr = rdmsr(MSR_PLATFORM_INFO);
+       msr.hi = 0;
+       msr.lo &= 0xff00;
+       wrmsr(IA32_PERF_CTL, msr);
+
+       printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n",
+              ((msr.lo >> 8) & 0xff) * 100);
+}
+
+static void set_energy_perf_bias(u8 policy)
+{
+       msr_t msr;
+
+       /* Energy Policy is bits 3:0 */
+       msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);
+       msr.lo &= ~0xf;
+       msr.lo |= policy & 0xf;
+       wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
+
+       printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n",
+              policy);
+}
+
+static void configure_mca(void)
+{
+       msr_t msr;
+       int i;
+
+       msr.lo = msr.hi = 0;
+       /* This should only be done on a cold boot */
+       for (i = 0; i < 7; i++)
+               wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+}
+
+#if CONFIG_USBDEBUG
+static unsigned ehci_debug_addr;
+#endif
+
+/*
+ * Initialize any extra cores/threads in this package.
+ */
+static void intel_cores_init(device_t cpu)
+{
+       struct cpuid_result result;
+       unsigned cores, threads, i;
+
+       result = cpuid_ext(0xb, 0); /* Threads per core */
+       threads = result.ebx & 0xff;
+
+       result = cpuid_ext(0xb, 1); /* Cores per package */
+       cores = result.ebx & 0xff;
+
+       /* Only initialize extra cores from BSP */
+       if (cpu->path.apic.apic_id)
+               return;
+
+       printk(BIOS_DEBUG, "CPU: %u has %u cores %u threads\n",
+              cpu->path.apic.apic_id, cores, threads);
+
+       for (i = 1; i < cores; ++i) {
+               struct device_path cpu_path;
+               device_t new;
+
+               /* Build the cpu device path */
+               cpu_path.type = DEVICE_PATH_APIC;
+               cpu_path.apic.apic_id =
+                       cpu->path.apic.apic_id + i;
+
+               /* Update APIC ID if no hyperthreading */
+               if (threads == 1)
+                       cpu_path.apic.apic_id <<= 1;
+
+               /* Allocate the new cpu device structure */
+               new = alloc_dev(cpu->bus, &cpu_path);
+               if (!new)
+                       continue;
+
+               printk(BIOS_DEBUG, "CPU: %u has core %u\n",
+                      cpu->path.apic.apic_id,
+                      new->path.apic.apic_id);
+
+               /* Start the new cpu */
+               if (!start_cpu(new)) {
+                       /* Record the error in cpu? */
+                       printk(BIOS_ERR, "CPU %u would not start!\n",
+                              new->path.apic.apic_id);
+               }
+       }
+}
+
+static void model_206ax_init(device_t cpu)
+{
+       char processor_name[49];
+       struct cpuid_result cpuid_regs;
+
+       /* Turn on caching if we haven't already */
+       x86_enable_cache();
+
+       /* Update the microcode */
+       intel_update_microcode(microcode_updates);
+
+       /* Clear out pending MCEs */
+       configure_mca();
+
+       /* Print processor name */
+       fill_processor_name(processor_name);
+       printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+
+#if CONFIG_USBDEBUG
+       // Is this caution really needed?
+       if(!ehci_debug_addr)
+               ehci_debug_addr = get_ehci_debug();
+       set_ehci_debug(0);
+#endif
+
+       /* Setup MTRRs based on physical address size */
+       cpuid_regs = cpuid(0x80000008);
+       x86_setup_fixed_mtrrs();
+       x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2);
+       x86_mtrr_check();
+
+       /* Setup Page Attribute Tables (PAT) */
+       // TODO set up PAT
+
+#if CONFIG_USBDEBUG
+       set_ehci_debug(ehci_debug_addr);
+#endif
+
+       /* Enable the local cpu apics */
+       enable_lapic_tpr();
+       setup_lapic();
+
+       /* Enable virtualization if enabled in CMOS */
+       enable_vmx();
+
+       /* Configure C States */
+       configure_c_states();
+
+       /* Configure Enhanced SpeedStep and Thermal Sensors */
+       configure_misc();
+
+       /* Enable Direct Cache Access */
+       configure_dca_cap();
+
+       /* Set energy policy */
+       set_energy_perf_bias(ENERGY_POLICY_NORMAL);
+
+       /* Set Max Ratio */
+       set_max_ratio();
+
+       /* Enable Turbo */
+       enable_turbo();
+
+       /* Start up extra cores */
+       intel_cores_init(cpu);
+}
+
+static struct device_operations cpu_dev_ops = {
+       .init     = model_206ax_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+       { X86_VENDOR_INTEL, 0x206a0 }, /* Intel Sandybridge */
+       { X86_VENDOR_INTEL, 0x206a6 }, /* Intel Sandybridge D1 */
+       { X86_VENDOR_INTEL, 0x206a7 }, /* Intel Sandybridge D2/J1 */
+       { X86_VENDOR_INTEL, 0x306a2 }, /* Intel IvyBridge */
+       { X86_VENDOR_INTEL, 0x306a4 }, /* Intel IvyBridge */
+       { X86_VENDOR_INTEL, 0x306a5 }, /* Intel IvyBridge */
+       { X86_VENDOR_INTEL, 0x306a6 }, /* Intel IvyBridge */
+       { X86_VENDOR_INTEL, 0x306a8 }, /* Intel IvyBridge */
+       { X86_VENDOR_INTEL, 0x306a9 }, /* Intel IvyBridge */
+       { 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+       .ops      = &cpu_dev_ops,
+       .id_table = cpu_table,
+       .cstates  = cstate_map,
+};
+

diff --git a/src/cpu/intel/model_206ax/x06_microcode.h b/src/cpu/intel/model_206ax/x06_microcode.h
new file mode 100644 (file)
index 0000000..d055b2e
--- /dev/null
+++ b/src/cpu/intel/model_206ax/x06_microcode.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE
+       #include "microcode-m12206a7_00000025.h"
+#elif CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
+#else
+#error "Which microcode to use?"
+#endif
+       /*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,

diff --git a/src/cpu/intel/socket_rPGA989/Kconfig b/src/cpu/intel/socket_rPGA989/Kconfig
new file mode 100644 (file)
index 0000000..11ac25f
--- /dev/null
+++ b/src/cpu/intel/socket_rPGA989/Kconfig
@@ -0,0 +1,16 @@
+config CPU_INTEL_SOCKET_RPGA989
+       bool
+
+if CPU_INTEL_SOCKET_RPGA989
+
+config SOCKET_SPECIFIC_OPTIONS # dummy
+       def_bool y
+       select MMX
+       select SSE
+       select CACHE_AS_RAM
+
+config CACHE_MRC_BIN
+       bool
+       default n
+
+endif

diff --git a/src/cpu/intel/socket_rPGA989/Makefile.inc b/src/cpu/intel/socket_rPGA989/Makefile.inc
new file mode 100644 (file)
index 0000000..b5d679a
--- /dev/null
+++ b/src/cpu/intel/socket_rPGA989/Makefile.inc
@@ -0,0 +1,8 @@
+ramstage-y += socket_rPGA989.c
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../turbo

diff --git a/src/cpu/intel/socket_rPGA989/chip.h b/src/cpu/intel/socket_rPGA989/chip.h
new file mode 100644 (file)
index 0000000..f843e74
--- /dev/null
+++ b/src/cpu/intel/socket_rPGA989/chip.h
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_rPGA989_ops;
+
+struct cpu_intel_socket_rPGA989_config {
+};

diff --git a/src/cpu/intel/socket_rPGA989/socket_rPGA989.c b/src/cpu/intel/socket_rPGA989/socket_rPGA989.c
new file mode 100644 (file)
index 0000000..2484571
--- /dev/null
+++ b/src/cpu/intel/socket_rPGA989/socket_rPGA989.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations cpu_intel_socket_rPGA989_ops = {
+       CHIP_NAME("Socket rPGA989 CPU")
+};