1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
10 #include "northbridge.h"
12 static void ram_resource(device_t dev, unsigned long index,
13 unsigned long basek, unsigned long sizek)
15 struct resource *resource;
20 resource = new_resource(dev, index);
21 resource->base = ((resource_t)basek) << 10;
22 resource->size = ((resource_t)sizek) << 10;
23 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
24 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
27 static void tolm_test(void *gp, struct device *dev, struct resource *new)
29 struct resource **best_p = gp;
30 struct resource *best;
32 if (!best || (best->base > new->base)) {
38 static uint32_t find_pci_tolm(struct bus *bus)
43 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
45 if (min && tolm > min->base) {
51 #if CONFIG_HAVE_HIGH_TABLES==1
52 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
53 extern uint64_t high_tables_base, high_tables_size;
56 static void cpu_pci_domain_set_resources(device_t dev)
58 static const uint8_t ramregs[] = {
59 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
64 pci_tolm = find_pci_tolm(&dev->link[0]);
65 mc_dev = dev->link[0].children;
67 unsigned long tomk, tolmk;
68 unsigned char rambits;
71 for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
73 reg = pci_read_config8(mc_dev, ramregs[i]);
74 /* these are ENDING addresses, not sizes.
75 * if there is memory in this slot, then reg will be > rambits.
76 * So we just take the max, that gives us total.
77 * We take the highest one to cover for once and future coreboot
78 * bugs. We warn about bugs.
83 printk_err("ERROR! register 0x%x is not set!\n",
87 printk_err("RAM size config registers are empty; defaulting to 64 MBytes\n");
90 printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
91 tomk = rambits*8*1024;
92 /* Compute the top of Low memory */
93 tolmk = pci_tolm >> 10;
95 /* The PCI hole does not overlap the memory. */
99 /* Report the memory regions. */
101 ram_resource(dev, idx++, 0, 640);
102 ram_resource(dev, idx++, 768, tolmk - 768);
104 #if CONFIG_HAVE_HIGH_TABLES==1
105 /* Leave some space for ACPI, PIRQ and MP tables */
106 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
107 high_tables_size = HIGH_TABLES_SIZE * 1024;
110 assign_resources(&dev->link[0]);
113 static void cpu_pci_domain_read_resources(struct device *dev)
115 struct resource *res;
117 pci_domain_read_resources(dev);
119 /* Reserve space for the IOAPIC. This should be in the Southbridge,
120 * but I couldn't tell which device to put it in. */
121 res = new_resource(dev, 2);
122 res->base = 0xfec00000UL;
123 res->size = 0x100000UL;
124 res->limit = 0xffffffffUL;
125 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
128 /* Reserve space for the LAPIC. There's one in every processor, but
129 * the space only needs to be reserved once, so we do it here. */
130 res = new_resource(dev, 3);
131 res->base = 0xfee00000UL;
132 res->size = 0x10000UL;
133 res->limit = 0xffffffffUL;
134 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
138 static struct device_operations pci_domain_ops = {
139 .read_resources = cpu_pci_domain_read_resources,
140 .set_resources = cpu_pci_domain_set_resources,
141 .enable_resources = enable_childrens_resources,
143 .scan_bus = pci_domain_scan_bus,
146 static void enable_dev(struct device *dev)
148 /* Set the operations if it is a special bus type */
149 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
150 dev->ops = &pci_domain_ops;
155 struct chip_operations cpu_emulation_qemu_x86_ops = {
156 CHIP_NAME("QEMU Northbridge")
157 .enable_dev = enable_dev,
160 void udelay(int usecs)
163 for(i = 0; i < usecs; i++)