2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <northbridge/amd/amdmct/amddefs.h>
21 #include <cpu/amd/mtrr.h>
24 * Default MSR and errata settings.
34 } fam10_msr_default[] = {
35 { TOP_MEM2, AMD_FAM10_ALL, AMD_PTYPE_ALL,
36 0x00000000, 0x00000000,
37 0xFFFFFFFF, 0xFFFFFFFF },
39 { SYSCFG, AMD_FAM10_ALL, AMD_PTYPE_ALL,
41 3 << 21, 0x00000000 }, /* [MtrrTom2En]=1,[TOM2EnWB] = 1*/
43 { HWCR, AMD_FAM10_ALL, AMD_PTYPE_ALL,
45 1 << 4, 0x00000000 }, /* [INVD_WBINVD]=1 */
47 { MC4_CTL_MASK, AMD_FAM10_ALL, AMD_PTYPE_ALL,
48 0xF << 19, 0x00000000,
49 0xF << 19, 0x00000000 }, /* [RtryHt[0..3]]=1 */
51 { DC_CFG, AMD_FAM10_ALL, AMD_PTYPE_SVR,
52 0x00000000, 0x00000004,
53 0x00000000, 0x0000000C }, /* [REQ_CTR] = 1 for Server */
55 { DC_CFG, AMD_DR_Bx, AMD_PTYPE_SVR,
56 0x00000000, 0x00000000,
57 0x00000000, 0x00000C00 }, /* Errata 326 */
59 { NB_CFG, AMD_FAM10_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC,
61 0x00000000, 1 << 22 }, /* [ApicInitIDLo]=1 */
63 { BU_CFG2, AMD_DR_Bx, AMD_PTYPE_ALL,
65 1 << 29, 0x00000000 }, /* For Bx Smash1GPages=1 */
67 { DC_CFG, AMD_FAM10_ALL, AMD_PTYPE_ALL,
69 1 << 24, 0x00000000 }, /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */
71 { LS_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL,
73 1 << 1, 0x00000000 }, /* IDX_MATCH_ALL=0 */
75 { BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL,
77 1 << 21, 0x00000000 }, /* Erratum #254 DR B1 BU_CFG[21]=1 */
79 { BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL,
81 1 << 23, 0x00000000 }, /* Erratum #309 BU_CFG[23]=1 */
83 /* CPUID_EXT_FEATURES */
84 { CPUIDFEATURES, AMD_FAM10_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC,
86 1 << 28, 0x00000000 }, /* [HyperThreadFeatEn]=1 */
88 { CPUIDFEATURES, AMD_FAM10_ALL, AMD_PTYPE_DC,
89 0x00000000, 1 << (33-32),
90 0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */
92 { BU_CFG2, AMD_DRBH_Cx, AMD_PTYPE_ALL,
93 0x00000000, 1 << (35-32),
94 0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() ) */
96 { OSVW_ID_Length, AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL,
97 0x00000004, 0x00000000,
98 0x00000004, 0x00000000}, /* B0 or Above, OSVW_ID_Length is 0004h */
100 { OSVW_Status, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_MC,
101 0x0000000C, 0x00000000,
102 0x0000000C, 0x00000000}, /* Cx and Dx multiple-link processor */
104 { BU_CFG2, AMD_DR_Dx, AMD_PTYPE_ALL,
105 0x00000000, 1 << (50-32),
106 0x00000000, 1 << (50-32)}, /* D0 or Above, RdMmExtCfgQwEn*/
108 { CPU_ID_EXT_FEATURES_MSR, AMD_DR_Dx, AMD_PTYPE_ALL,
109 0x00000000, 1 << (51 - 32),
110 0x00000000, 1 << (51 - 32)}, /* G34_PKG | C32_PKG | S1G4_PKG | ASB2_PKG */
115 * Default PCI and errata settings.
117 static const struct {
124 } fam10_pci_default[] = {
126 /* Function 0 - HT Config */
128 { 0, 0x68, AMD_FAM10_ALL, AMD_PTYPE_ALL,
129 0x004E4800, 0x006E6800 }, /* [19:17] for 8bit APIC config,
130 [14:13] BufPriRel = 2h [11] RspPassPW set,
131 [22:21] DsNpReqLmt = 10b */
133 /* Errata 281 Workaround */
134 { 0, 0x68, (AMD_DR_B0 | AMD_DR_B1),
135 AMD_PTYPE_SVR, 0x00200000, 0x00600000 }, /* [22:21] DsNpReqLmt0 = 01b */
137 { 0, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL,
138 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
140 { 0, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
141 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
143 { 0, 0xC4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
144 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
146 { 0, 0xE4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
147 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
149 /* Link Global Retry Control Register */
150 { 0, 0x150, AMD_FAM10_ALL, AMD_PTYPE_ALL,
151 0x00073900, 0x00073F00 },
154 * System software should program the Link Extended Control Registers[LS2En]
155 * (F0x[18C:170][8]) to 0b for all links. System software should also
156 * program Link Global Extended Control Register[ForceFullT0]
157 * (F0x16C[15:13]) to 000b */
159 { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */
160 0x00000000, 0x00000100 },
161 { 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL,
162 0x00000000, 0x00000100 },
163 { 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL,
164 0x00000000, 0x00000100 },
165 { 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
166 0x00000000, 0x00000100 },
167 { 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL,
168 0x00000000, 0x00000100 },
169 { 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL,
170 0x00000000, 0x00000100 },
171 { 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL,
172 0x00000000, 0x00000100 },
173 { 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
174 0x00000000, 0x00000100 },
175 { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL,
176 0x00000000, 0x00000100 },
178 /* Link Global Extended Control Register */
179 { 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
180 0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 0b,
181 * Set T0Time 14h per BKDG */
184 /* Function 1 - Map Init */
186 /* Before reading F1x114_x2 or F1x114_x3 software must
187 * initialize the registers or NB Array MCA errors may
188 * occur. BIOS should initialize index 0h of F1x114_x2 and
189 * F1x114_x3 to prevent reads from F1x114 from generating NB
190 * Array MCA errors. BKDG Doc #3116 Rev 1.07
193 { 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL,
194 0x20000000, 0xFFFFFFFF }, /* Select extended MMIO Base */
196 { 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL,
197 0x00000000, 0xFFFFFFFF }, /* Clear map */
199 { 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL,
200 0x30000000, 0xFFFFFFFF }, /* Select extended MMIO Base */
202 { 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL,
203 0x00000000, 0xFFFFFFFF }, /* Clear map */
205 /* Function 2 - DRAM Controller */
207 /* Function 3 - Misc. Control */
208 { 3, 0x40, AMD_FAM10_ALL, AMD_PTYPE_ALL,
209 0x00000100, 0x00000100 }, /* [8] MstrAbrtEn */
211 { 3, 0x44, AMD_FAM10_ALL, AMD_PTYPE_ALL,
212 0x4A30005C, 0x4A30005C }, /* [30] SyncOnDramAdrParErrEn = 1,
213 [27] NbMcaToMstCpuEn = 1,
214 [25] DisPciCfgCpuErrRsp = 1,
215 [21] SyncOnAnyErrEn = 1,
216 [20] SyncOnWDTEn = 1,
218 [4] SyncPktPropDis = 1,
219 [3] SyncPktGenDis = 1,
220 [2] SyncOnUcEccEn = 1 */
222 /* XBAR buffer settings */
223 { 3, 0x6C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
224 0x00018052, 0x700780F7 },
226 /* Errata 281 Workaround */
227 { 3, 0x6C, ( AMD_DR_B0 | AMD_DR_B1),
228 AMD_PTYPE_SVR, 0x00010094, 0x700780F7 },
230 { 3, 0x6C, AMD_FAM10_ALL, AMD_PTYPE_UMA,
231 0x60018051, 0x700780F7 },
233 { 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_ALL,
234 0x00041153, 0x777777F7 },
236 { 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_UMA,
237 0x61221151, 0x777777F7 },
239 { 3, 0x74, AMD_FAM10_ALL, AMD_PTYPE_UMA,
240 0x00080101, 0x000F7777 },
242 { 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
243 0x00090914, 0x707FFF1F },
245 /* Errata 281 Workaround */
246 { 3, 0x7C, ( AMD_DR_B0 | AMD_DR_B1),
247 AMD_PTYPE_SVR, 0x00144514, 0x707FFF1F },
249 { 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_UMA,
250 0x00070814, 0x007FFF1F },
252 { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_ALL,
253 0x00800756, 0x00F3FFFF },
255 { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_UMA,
256 0x00C37756, 0x00F3FFFF },
258 { 3, 0x144, AMD_FAM10_ALL, AMD_PTYPE_UMA,
259 0x00000036, 0x000000FF },
261 /* Errata 281 Workaround */
262 { 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1),
263 AMD_PTYPE_SVR, 0x00000001, 0x0000000F },
264 /* [3:0] RspTok = 0001b */
266 { 3, 0x148, AMD_FAM10_ALL, AMD_PTYPE_UMA,
267 0x8000052A, 0xD5FFFFFF },
269 /* ACPI Power State Control Reg1 */
270 { 3, 0x80, AMD_FAM10_ALL, AMD_PTYPE_ALL,
271 0xE6002200, 0xFFFFFFFF },
273 /* ACPI Power State Control Reg2 */
274 { 3, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL,
275 0xA0E641E6, 0xFFFFFFFF },
277 { 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK,
278 0x00000080, 0x00000080 }, /* [7] PSIVidEnable */
280 { 3, 0xA0, AMD_DR_Bx, AMD_PTYPE_ALL,
281 0x00002800, 0x000003800 }, /* [13:11] PllLockTime = 5 */
283 { 3, 0xA0, (AMD_FAM10_ALL & ~(AMD_DR_Bx)), AMD_PTYPE_ALL,
284 0x00000800, 0x000003800 }, /* [13:11] PllLockTime = 1 */
286 /* Reported Temp Control Register */
287 { 3, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
288 0x00000080, 0x00000080 }, /* [7] TempSlewDnEn = 1 */
290 /* Clock Power/Timing Control 0 Register */
291 { 3, 0xD4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
292 0xC0000F00, 0xF0000F00 }, /* [31] NbClkDivApplyAll = 1,
293 [30:28] NbClkDiv = 100b,[11:8] ClkRampHystSel = 1111b */
295 /* Clock Power/Timing Control 1 Register */
296 { 3, 0xD8, AMD_FAM10_ALL, AMD_PTYPE_ALL,
297 0x03000016, 0x0F000077 }, /* [6:4] VSRampTime = 1,
298 [2:0] VSSlamTime = 6, [27:24] ReConDel = 3 */
301 /* Clock Power/Timing Control 2 Register */
302 { 3, 0xDC, AMD_FAM10_ALL, AMD_PTYPE_ALL,
303 0x00005000, 0x00007000 }, /* [14:12] NbsynPtrAdj = 5 */
306 /* Extended NB MCA Config Register */
307 { 3, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL,
308 0x007003E2, 0x007003E2 }, /* [22:20] = SyncFloodOn_Err = 7,
309 [9] SyncOnUncNbAryEn = 1 ,
310 [8] SyncOnProtEn = 1,
311 [7] SyncFloodOnTgtAbtErr = 1,
312 [6] SyncFloodOnDatErr = 1,
313 [5] DisPciCfgCpuMstAbtRsp = 1,
314 [1] SyncFloodOnUsPwDataErr = 1 */
316 /* errata 346 - Fam10 C2, C3
317 * System software should set F3x188[22] to 1b. */
318 { 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL,
319 0x00400000, 0x00400000 },
321 /* L3 Control Register */
322 { 3, 0x1B8, AMD_FAM10_ALL, AMD_PTYPE_ALL,
323 0x00001000, 0x00001000 }, /* [12] = L3PrivReplEn */
325 /* IBS Control Register */
326 { 3, 0x1CC, AMD_FAM10_ALL, AMD_PTYPE_ALL,
327 0x00000100, 0x00000100 }, /* [8] = LvtOffsetVal */
332 * Default HyperTransport Phy and errata settings.
334 static const struct {
335 u16 htreg; /* HT Phy Register index */
341 } fam10_htphy_default[] = {
343 /* Errata 344 - Fam10 C2/C3, D0/D1
344 * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */
345 { 0x60, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
346 0x00000040, 0x00000040 },
347 { 0x61, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
348 0x00000040, 0x00000040 },
349 { 0x62, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
350 0x00000040, 0x00000040 },
351 { 0x63, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
352 0x00000040, 0x00000040 },
353 { 0x64, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
354 0x00000040, 0x00000040 },
355 { 0x65, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
356 0x00000040, 0x00000040 },
357 { 0x66, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
358 0x00000040, 0x00000040 },
359 { 0x67, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
360 0x00000040, 0x00000040 },
361 { 0x68, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
362 0x00000040, 0x00000040 },
364 { 0x70, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
365 0x00000040, 0x00000040 },
366 { 0x71, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
367 0x00000040, 0x00000040 },
368 { 0x72, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
369 0x00000040, 0x00000040 },
370 { 0x73, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
371 0x00000040, 0x00000040 },
372 { 0x74, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
373 0x00000040, 0x00000040 },
374 { 0x75, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
375 0x00000040, 0x00000040 },
376 { 0x76, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
377 0x00000040, 0x00000040 },
378 { 0x77, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
379 0x00000040, 0x00000040 },
380 { 0x78, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
381 0x00000040, 0x00000040 },
383 /* Errata 354 - Fam10 C2, C3
384 * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */
385 { 0x40, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
386 0x00000040, 0x00000040 },
387 { 0x41, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
388 0x00000040, 0x00000040 },
389 { 0x42, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
390 0x00000040, 0x00000040 },
391 { 0x43, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
392 0x00000040, 0x00000040 },
393 { 0x44, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
394 0x00000040, 0x00000040 },
395 { 0x45, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
396 0x00000040, 0x00000040 },
397 { 0x46, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
398 0x00000040, 0x00000040 },
399 { 0x47, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
400 0x00000040, 0x00000040 },
401 { 0x48, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
402 0x00000040, 0x00000040 },
404 { 0x50, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
405 0x00000040, 0x00000040 },
406 { 0x51, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
407 0x00000040, 0x00000040 },
408 { 0x52, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
409 0x00000040, 0x00000040 },
410 { 0x53, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
411 0x00000040, 0x00000040 },
412 { 0x54, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
413 0x00000040, 0x00000040 },
414 { 0x55, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
415 0x00000040, 0x00000040 },
416 { 0x56, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
417 0x00000040, 0x00000040 },
418 { 0x57, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
419 0x00000040, 0x00000040 },
420 { 0x58, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
421 0x00000040, 0x00000040 },
423 /* Errata 327 - Fam10 C2/C3, D0/D1
424 * BIOS should set the Link Phy Impedance Register[RttCtl]
425 * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and
426 * Link Phy Impedance Register[RttIndex]
427 * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */
428 { 0xC0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
429 0x40040000, 0xe01F0000 },
430 { 0xD0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
431 0x40040000, 0xe01F0000 },
433 { 0x520A,AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
434 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */
436 { 0x530A, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
437 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */
439 { 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
440 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */
442 { 0x530A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
443 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */
445 { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
446 0x00000000, 0x000000FF }, /* Provide clear setting for logical
449 { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
450 0x00000000, 0x000000FF }, /* Provide clear setting for logical
453 { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
454 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
456 { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
457 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
459 /* Link Phy Receiver Loop Filter Registers */
460 { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
461 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h,
462 [21:14] LfcMin = 10h */
464 { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
465 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h,
466 [21:14] LfcMin = 10h */
468 { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
469 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h,
470 [21:14] LfcMin = 08h */
472 { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
473 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h,
474 [21:14] LfcMin = 08h */
476 { 0xC0, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
477 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h,
478 [20:16] RttIndex = 04h */