2 * This file is part of the coreboot project.
4 * Copyright (C) 2005-2007 Advanced Micro Devices, Inc.
5 * Copyright (C) 2008 Carl-Daniel Hailfinger
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #define CacheSize CONFIG_DCACHE_RAM_SIZE
22 #define CacheBase (0xd0000 - CacheSize)
24 /* leave some space for global variable to pass to RAM stage */
25 #define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
27 /* for CONFIG_CAR_FAM10 */
28 #define CacheSizeAPStack 0x400 /* 1K */
30 #define MSR_FAM10 0xC001102A
32 #define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x
34 #define CPUID_MASK 0x0ff00f00
35 #define CPUID_VAL_FAM10_ROTATED 0x0f000010
37 #include <cpu/x86/mtrr.h>
38 #include <cpu/amd/mtrr.h>
42 xmm2: fam10 comparison value
46 /* Save the BIST result */
49 /*for normal part %ebx already contain cpu_init_detected from fallback call */
61 /* figure out cpu family */
65 /* base family is bits 8..11, extended family is bits 20..27 */
66 andl $CPUID_MASK, %eax
67 /* reorder bits for easier comparison by value */
70 movl $CPUID_VAL_FAM10_ROTATED, %eax
74 /* hope we can skip the double set for normal part */
75 #if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
77 /* check if cpu_init_detected */
78 movl $MTRRdefType_MSR, %ecx
81 movl %eax, %ebx /* We store the status */
83 jmp_if_k8(CAR_FAM10_out_post_errata)
85 /* for GH, CAR need to set DRAM Base/Limit Registers to direct that to node0 */
87 /* Only BSP needed, for other nodes set during HT/memory init. */
88 /* So we need to check if it is BSP */
94 /* Enable RT tables on BSP */
95 movl $0x8000c06c, %eax
103 /* Setup temporary DRAM map: [0,16M) bit 0-23 */
104 movl $0x8000c144, %eax
111 movl $0x8000c140, %eax
120 /* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
121 Re-enable it in after RAM is initialized and before CAR is disabled */
122 movl $0xc001102a, %ecx
127 /* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */
129 /* read-address has to be stored in the ecx register */
130 movl $MSR_FAM10, %ecx
132 /* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */
135 /* Set bit 35 to 1 in EAX */
138 /* write back the modified register EDX:EAX to the MSR specified in ECX */
141 /* Erratum 343 end */
143 CAR_FAM10_out_post_errata:
145 /* Set MtrrFixDramModEn for clear fixed mtrr */
146 enable_fixed_mtrr_dram_modify:
147 movl $SYSCFG_MSR, %ecx
149 andl $(~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn)), %eax
150 orl $SYSCFG_MSR_MtrrFixDramModEn, %eax
153 /* Clear all MTRRs */
155 movl $fixed_mtrr_msr, %esi
157 clear_fixed_var_mtrr:
160 jz clear_fixed_var_mtrr_out
166 jmp clear_fixed_var_mtrr
167 clear_fixed_var_mtrr_out:
169 /* 0x06 is the WB IO type for a given 4k segment.
170 * 0x1e is the MEM IO type for a given 4k segment (K10 and above).
171 * segs is the number of 4k segments in the area of the particular
172 * register we want to use for CAR.
173 * reg is the register where the IO type should be stored.
175 .macro extractmask segs, reg
177 /* The xorl here is superfluous because at the point of first execution
178 * of this macro, %eax and %edx are cleared. Later invocations of this
179 * macro will have a monotonically increasing segs parameter.
186 movl $0x1e000000, \reg /* WB MEM type */
188 movl $0x1e1e0000, \reg /* WB MEM type */
190 movl $0x1e1e1e00, \reg /* WB MEM type */
192 movl $0x1e1e1e1e, \reg /* WB MEM type */
197 movl $0x06000000, \reg /* WB IO type */
199 movl $0x06060000, \reg /* WB IO type */
201 movl $0x06060600, \reg /* WB IO type */
203 movl $0x06060606, \reg /* WB IO type */
206 .endif /* if \segs <= 0 */
209 /* size is the cache size in bytes we want to use for CAR.
210 * windowoffset is the 32k-aligned window into CAR size
212 .macro simplemask carsize, windowoffset
213 .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
214 extractmask gas_bug_workaround, %eax
215 .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
216 extractmask gas_bug_workaround, %edx
217 /* Without the gas bug workaround, the entire macro would consist only of the
219 extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
220 extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
224 #if CacheSize > 0x10000
225 #error Invalid CAR size, must be at most 64k.
227 #if CacheSize < 0x1000
228 #error Invalid CAR size, must be at least 4k. This is a processor limitation.
230 #if (CacheSize & (0x1000 - 1))
231 #error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
234 #if CacheSize > 0x8000
235 /* enable caching for 32K-64K using fixed mtrr */
236 movl $0x268, %ecx /* fix4k_c0000*/
237 simplemask CacheSize, 0x8000
241 /* enable caching for 0-32K using fixed mtrr */
242 movl $0x269, %ecx /* fix4k_c8000*/
243 simplemask CacheSize, 0
246 /* enable memory access for first MBs using top_mem */
249 movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
251 #endif /* CONFIG_USE_FAILOVER_IMAGE == 1*/
253 #if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0))
261 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
262 /* enable write base caching so we can do execute in place
267 movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
271 movl $0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
272 jmp_if_k8(wbcache_post_fam10_setup)
273 movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
274 wbcache_post_fam10_setup:
275 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
277 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
279 #if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
280 /* Set the default memory type and enable fixed and variable MTRRs */
281 movl $MTRRdefType_MSR, %ecx
283 /* Enable Variable and Fixed MTRRs */
284 movl $0x00000c00, %eax
287 /* Enable the MTRRs and IORRs in SYSCFG */
288 movl $SYSCFG_MSR, %ecx
290 orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
299 andl $0x9fffffff, %eax
302 jmp_if_k8(fam10_end_part1)
304 /* So we need to check if it is BSP */
314 #if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
315 /* Read the range with lodsl*/
317 movl $CacheBase, %esi
318 movl $(CacheSize >> 2), %ecx
320 /* Clear the range */
321 movl $CacheBase, %edi
322 movl $(CacheSize >> 2), %ecx
326 #endif /*CONFIG_USE_FAILOVER_IMAGE == 1*/
328 /* set up the stack pointer */
329 movl $(CacheBase + CacheSize - GlobalVarSize), %eax
337 /* need to set stack pointer for AP */
338 /* it will be from CacheBase + (CacheSize - GlobalVarSize)/2 - (NodeID<<CoreIDbits + CoreID) * CacheSizeAPStack*/
339 /* So need to get the NodeID and CoreID at first */
340 /* If NB_CFG bit 54 is set just use initial apicid, otherwise need to reverse it */
342 /* store our init detected */
345 /* get the coreid bits at first */
346 movl $0x80000008, %eax
352 /* get the initial apic id */
357 /* get the nb cfg bit 54 */
358 movl $0xc001001f, %ecx /* NB_CFG_MSR */
360 movl %edi, %ecx /* CoreID bits */
366 /* calculate stack pointer */
367 movl $CacheSizeAPStack, %eax
369 movl $(CacheBase + (CacheSize - GlobalVarSize)/2), %esp
372 /* retrive init detected */
388 /* Restore the BIST result */
391 /* We need to set ebp ? No need */
393 pushl %ebx /* init detected */
394 pushl %eax /* bist */
395 call cache_as_ram_main
396 /* We will not go back */
398 movb $0xAF, %al /* Should never see this postcode */
402 .long 0x250, 0x258, 0x259
403 .long 0x268, 0x269, 0x26A
404 .long 0x26B, 0x26C, 0x26D
407 .long 0x200, 0x201, 0x202, 0x203
408 .long 0x204, 0x205, 0x206, 0x207
409 .long 0x208, 0x209, 0x20A, 0x20B
410 .long 0x20C, 0x20D, 0x20E, 0x20F
412 .long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019
414 .long 0xC001001A, 0xC001001D
415 .long 0x000 /* NULL, end of table */
417 cache_as_ram_setup_out: