2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 entity beh_uart_rx_tb is
7 end entity beh_uart_rx_tb;
9 architecture sim of beh_uart_rx_tb is
11 constant clk_period : time := 2ns;
12 signal clock : std_logic;
13 signal reset : std_logic;
14 signal done : std_logic;
15 signal newsig : std_logic;
16 signal data : std_logic_vector(7 downto 0);
17 signal serial_in: std_logic;
19 inst : entity work.uart_rx(beh)
38 assert false report "Test finished" severity failure;
52 wait for clk_period/2;
54 wait for clk_period/2;
55 end process clock_gen;