1 // Support for generating ACPI tables (on emulators)
3 // Copyright (C) 2008,2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "acpi.h" // struct rsdp_descriptor
9 #include "util.h" // memcpy
10 #include "pci.h" // pci_find_device
11 #include "biosvar.h" // GET_EBDA
12 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
13 #include "pci_regs.h" // PCI_INTERRUPT_LINE
16 /****************************************************/
17 /* ACPI tables init */
19 /* Table structure from Linux kernel (the ACPI tables are under the
22 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
23 u32 signature; /* ACPI signature (4 ASCII characters) */ \
24 u32 length; /* Length of table, in bytes, including header */ \
25 u8 revision; /* ACPI Specification minor version # */ \
26 u8 checksum; /* To make sum of entire table == 0 */ \
27 u8 oem_id [6]; /* OEM identification */ \
28 u8 oem_table_id [8]; /* OEM table identification */ \
29 u32 oem_revision; /* OEM revision number */ \
30 u8 asl_compiler_id [4]; /* ASL compiler vendor ID */ \
31 u32 asl_compiler_revision; /* ASL compiler revision number */
34 struct acpi_table_header /* ACPI common table header */
40 * ACPI 1.0 Root System Description Table (RSDT)
42 #define RSDT_SIGNATURE 0x54445352 // RSDT
43 struct rsdt_descriptor_rev1
45 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
46 u32 table_offset_entry[0]; /* Array of pointers to other */
51 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
53 #define FACS_SIGNATURE 0x53434146 // FACS
54 struct facs_descriptor_rev1
56 u32 signature; /* ACPI Signature */
57 u32 length; /* Length of structure, in bytes */
58 u32 hardware_signature; /* Hardware configuration signature */
59 u32 firmware_waking_vector; /* ACPI OS waking vector */
60 u32 global_lock; /* Global Lock */
61 u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
62 u32 reserved1 : 31; /* Must be 0 */
63 u8 resverved3 [40]; /* Reserved - must be zero */
68 * ACPI 1.0 Fixed ACPI Description Table (FADT)
70 #define FACP_SIGNATURE 0x50434146 // FACP
71 struct fadt_descriptor_rev1
73 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
74 u32 firmware_ctrl; /* Physical address of FACS */
75 u32 dsdt; /* Physical address of DSDT */
76 u8 model; /* System Interrupt Model */
77 u8 reserved1; /* Reserved */
78 u16 sci_int; /* System vector of SCI interrupt */
79 u32 smi_cmd; /* Port address of SMI command port */
80 u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */
81 u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */
82 u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
83 u8 reserved2; /* Reserved - must be zero */
84 u32 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
85 u32 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
86 u32 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
87 u32 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
88 u32 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
89 u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
90 u32 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
91 u32 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
92 u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
93 u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
94 u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
95 u8 pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
96 u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
97 u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
98 u8 gpe1_base; /* Offset in gpe model where gpe1 events start */
99 u8 reserved3; /* Reserved */
100 u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
101 u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
102 u16 flush_size; /* Size of area read to flush caches */
103 u16 flush_stride; /* Stride used in flushing caches */
104 u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */
105 u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */
106 u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
107 u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
108 u8 century; /* Index to century in RTC CMOS RAM */
109 u8 reserved4; /* Reserved */
110 u8 reserved4a; /* Reserved */
111 u8 reserved4b; /* Reserved */
113 u32 wb_invd : 1; /* The wbinvd instruction works properly */
114 u32 wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
115 u32 proc_c1 : 1; /* All processors support C1 state */
116 u32 plvl2_up : 1; /* C2 state works on MP system */
117 u32 pwr_button : 1; /* Power button is handled as a generic feature */
118 u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
119 u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
120 u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
121 u32 tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
122 u32 reserved5 : 23; /* Reserved - must be zero */
129 * MADT values and structures
132 /* Values for MADT PCATCompat */
135 #define MULTIPLE_APIC 1
140 #define APIC_SIGNATURE 0x43495041 // APIC
141 struct multiple_apic_table
143 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
144 u32 local_apic_address; /* Physical address of local APIC */
146 u32 PCATcompat : 1; /* A one indicates system also has dual 8259s */
154 /* Values for Type in APIC sub-headers */
156 #define APIC_PROCESSOR 0
158 #define APIC_XRUPT_OVERRIDE 2
160 #define APIC_LOCAL_NMI 4
161 #define APIC_ADDRESS_OVERRIDE 5
162 #define APIC_IO_SAPIC 6
163 #define APIC_LOCAL_SAPIC 7
164 #define APIC_XRUPT_SOURCE 8
165 #define APIC_RESERVED 9 /* 9 and greater are reserved */
168 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
170 #define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
174 /* Sub-structures for MADT */
176 struct madt_processor_apic
179 u8 processor_id; /* ACPI processor id */
180 u8 local_apic_id; /* Processor's local APIC id */
182 u32 processor_enabled: 1; /* Processor is usable if set */
183 u32 reserved2 : 31; /* Reserved, must be zero */
192 u8 io_apic_id; /* I/O APIC ID */
193 u8 reserved; /* Reserved - must be zero */
194 u32 address; /* APIC physical address */
195 u32 interrupt; /* Global system interrupt where INTI
200 #define PCI_ISA_IRQ_MASK 0x0e20
202 struct madt_intsrcovr {
211 * ACPI 2.0 Generic Address Space definition.
213 struct acpi_20_generic_address {
215 u8 register_bit_width;
216 u8 register_bit_offset;
222 * HPET Description Table
224 struct acpi_20_hpet {
225 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
227 struct acpi_20_generic_address addr;
232 #define ACPI_HPET_ADDRESS 0xFED00000UL
235 * SRAT (NUMA topology description) table
238 #define SRAT_PROCESSOR 0
239 #define SRAT_MEMORY 1
241 struct system_resource_affinity_table
243 ACPI_TABLE_HEADER_DEF
248 struct srat_processor_affinity
259 struct srat_memory_affinity
264 u32 base_addr_low,base_addr_high;
265 u32 length_low,length_high;
271 #include "acpi-dsdt.hex"
273 static inline u16 cpu_to_le16(u16 x)
278 static inline u32 cpu_to_le32(u32 x)
284 build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev)
287 h->length = cpu_to_le32(len);
289 memcpy(h->oem_id, CONFIG_APPNAME6, 6);
290 memcpy(h->oem_table_id, CONFIG_APPNAME4, 4);
291 memcpy(h->asl_compiler_id, CONFIG_APPNAME4, 4);
292 memcpy(h->oem_table_id + 4, (void*)&sig, 4);
293 h->oem_revision = cpu_to_le32(1);
294 h->asl_compiler_revision = cpu_to_le32(1);
295 h->checksum -= checksum(h, len);
301 struct fadt_descriptor_rev1 *fadt = malloc_high(sizeof(*fadt));
302 struct facs_descriptor_rev1 *facs = memalign_high(64, sizeof(*facs));
303 void *dsdt = malloc_high(sizeof(AmlCode));
305 if (!fadt || !facs || !dsdt) {
306 dprintf(1, "Not enough memory for fadt!\n");
311 memset(facs, 0, sizeof(*facs));
312 facs->signature = FACS_SIGNATURE;
313 facs->length = cpu_to_le32(sizeof(*facs));
316 memcpy(dsdt, AmlCode, sizeof(AmlCode));
319 memset(fadt, 0, sizeof(*fadt));
320 fadt->firmware_ctrl = cpu_to_le32((u32)facs);
321 fadt->dsdt = cpu_to_le32((u32)dsdt);
324 int pm_sci_int = pci_config_readb(bdf, PCI_INTERRUPT_LINE);
325 fadt->sci_int = cpu_to_le16(pm_sci_int);
326 fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
327 fadt->acpi_enable = 0xf1;
328 fadt->acpi_disable = 0xf0;
329 fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
330 fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
331 fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
332 fadt->pm1_evt_len = 4;
333 fadt->pm1_cnt_len = 2;
334 fadt->pm_tmr_len = 4;
335 fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
336 fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
337 fadt->gpe0_blk = cpu_to_le32(0xafe0);
338 fadt->gpe0_blk_len = 4;
339 /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC */
340 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6));
342 build_header((void*)fadt, FACP_SIGNATURE, sizeof(*fadt), 1);
350 int madt_size = (sizeof(struct multiple_apic_table)
351 + sizeof(struct madt_processor_apic) * MaxCountCPUs
352 + sizeof(struct madt_io_apic)
353 + sizeof(struct madt_intsrcovr) * 16);
354 struct multiple_apic_table *madt = malloc_high(madt_size);
356 dprintf(1, "Not enough memory for madt!\n");
359 memset(madt, 0, madt_size);
360 madt->local_apic_address = cpu_to_le32(BUILD_APIC_ADDR);
361 madt->flags = cpu_to_le32(1);
362 struct madt_processor_apic *apic = (void*)&madt[1];
364 for (i=0; i<MaxCountCPUs; i++) {
365 apic->type = APIC_PROCESSOR;
366 apic->length = sizeof(*apic);
367 apic->processor_id = i;
368 apic->local_apic_id = i;
370 apic->flags = cpu_to_le32(1);
372 apic->flags = cpu_to_le32(0);
375 struct madt_io_apic *io_apic = (void*)apic;
376 io_apic->type = APIC_IO;
377 io_apic->length = sizeof(*io_apic);
378 io_apic->io_apic_id = CountCPUs;
379 io_apic->address = cpu_to_le32(BUILD_IOAPIC_ADDR);
380 io_apic->interrupt = cpu_to_le32(0);
382 struct madt_intsrcovr *intsrcovr = (void*)&io_apic[1];
383 if (qemu_cfg_irq0_override()) {
384 memset(intsrcovr, 0, sizeof(*intsrcovr));
385 intsrcovr->type = APIC_XRUPT_OVERRIDE;
386 intsrcovr->length = sizeof(*intsrcovr);
387 intsrcovr->source = 0;
389 intsrcovr->flags = 0; /* conforms to bus specifications */
392 for (i = 1; i < 16; i++) {
393 if (!(PCI_ISA_IRQ_MASK & (1 << i)))
394 /* No need for a INT source override structure. */
396 memset(intsrcovr, 0, sizeof(*intsrcovr));
397 intsrcovr->type = APIC_XRUPT_OVERRIDE;
398 intsrcovr->length = sizeof(*intsrcovr);
399 intsrcovr->source = i;
401 intsrcovr->flags = 0xd; /* active high, level triggered */
405 build_header((void*)madt, APIC_SIGNATURE, (void*)intsrcovr - (void*)madt, 1);
409 #define SSDT_SIGNATURE 0x54445353 // SSDT
413 int acpi_cpus = MaxCountCPUs > 0xff ? 0xff : MaxCountCPUs;
414 // calculate the length of processor block and scope block
415 // excluding PkgLength
416 int cpu_length = 13 * acpi_cpus + 4;
418 int length = sizeof(struct acpi_table_header) + 3 + cpu_length;
419 u8 *ssdt = malloc_high(length);
421 dprintf(1, "No space for ssdt!\n");
426 ssdt_ptr[9] = 0; // checksum;
427 ssdt_ptr += sizeof(struct acpi_table_header);
429 // build processor scope header
430 *(ssdt_ptr++) = 0x10; // ScopeOp
431 if (cpu_length <= 0x3e) {
432 *(ssdt_ptr++) = cpu_length + 1;
434 *(ssdt_ptr++) = 0x7F;
435 *(ssdt_ptr++) = (cpu_length + 2) >> 6;
437 *(ssdt_ptr++) = '_'; // Name
442 // build object for each processor
444 for (i=0; i<acpi_cpus; i++) {
445 *(ssdt_ptr++) = 0x5B; // ProcessorOp
446 *(ssdt_ptr++) = 0x83;
447 *(ssdt_ptr++) = 0x0B; // Length
448 *(ssdt_ptr++) = 'C'; // Name (CPUxx)
451 *(ssdt_ptr++) = (i >> 4) < 0xa ? (i >> 4) + '0' : (i >> 4) + 'A' - 0xa;
454 *(ssdt_ptr++) = (i & 0xf) < 0xa ? (i & 0xf) + '0' : (i & 0xf) + 'A' - 0xa;
456 *(ssdt_ptr++) = 0x10; // Processor block address
457 *(ssdt_ptr++) = 0xb0;
460 *(ssdt_ptr++) = 6; // Processor block length
463 build_header((void*)ssdt, SSDT_SIGNATURE, ssdt_ptr - ssdt, 1);
468 #define HPET_SIGNATURE 0x54455048 //HPET
472 struct acpi_20_hpet *hpet = malloc_high(sizeof(*hpet));
474 dprintf(1, "Not enough memory for hpet!\n");
478 memset(hpet, 0, sizeof(*hpet));
479 /* Note timer_block_id value must be kept in sync with value advertised by
482 hpet->timer_block_id = cpu_to_le32(0x8086a201);
483 hpet->addr.address = cpu_to_le32(ACPI_HPET_ADDRESS);
484 build_header((void*)hpet, HPET_SIGNATURE, sizeof(*hpet), 1);
490 acpi_build_srat_memory(struct srat_memory_affinity *numamem,
491 u64 base, u64 len, int node, int enabled)
493 numamem->type = SRAT_MEMORY;
494 numamem->length = sizeof(*numamem);
495 memset (numamem->proximity, 0 ,4);
496 numamem->proximity[0] = node;
497 numamem->flags = cpu_to_le32(!!enabled);
498 numamem->base_addr_low = base & 0xFFFFFFFF;
499 numamem->base_addr_high = base >> 32;
500 numamem->length_low = len & 0xFFFFFFFF;
501 numamem->length_high = len >> 32;
504 #define SRAT_SIGNATURE 0x54415253 //HPET
508 int nb_numa_nodes = qemu_cfg_get_numa_nodes();
510 if (nb_numa_nodes == 0)
513 u64 *numadata = malloc_tmphigh(sizeof(u64) * (MaxCountCPUs + nb_numa_nodes));
515 dprintf(1, "Not enough memory for read numa data from VM!\n");
519 qemu_cfg_get_numa_data(numadata, MaxCountCPUs + nb_numa_nodes);
521 struct system_resource_affinity_table *srat;
522 int srat_size = sizeof(*srat) +
523 sizeof(struct srat_processor_affinity) * MaxCountCPUs +
524 sizeof(struct srat_memory_affinity) * (nb_numa_nodes + 2);
526 srat = malloc_high(srat_size);
528 dprintf(1, "Not enough memory for srat table!\n");
532 memset(srat, 0, srat_size);
534 struct srat_processor_affinity *core = (void*)(srat + 1);
538 for (i = 0; i < MaxCountCPUs; ++i) {
539 core->type = SRAT_PROCESSOR;
540 core->length = sizeof(*core);
541 core->local_apic_id = i;
542 curnode = *numadata++;
543 core->proximity_lo = curnode;
544 memset(core->proximity_hi, 0, 3);
545 core->local_sapic_eid = 0;
547 core->flags = cpu_to_le32(1);
554 /* the memory map is a bit tricky, it contains at least one hole
555 * from 640k-1M and possibly another one from 3.5G-4G.
557 struct srat_memory_affinity *numamem = (void*)core;
559 u64 mem_len, mem_base, next_base = 0;
561 acpi_build_srat_memory(numamem, 0, 640*1024, 0, 1);
562 next_base = 1024 * 1024;
565 for (i = 1; i < nb_numa_nodes + 1; ++i) {
566 mem_base = next_base;
567 mem_len = *numadata++;
569 mem_len -= 1024 * 1024;
570 next_base = mem_base + mem_len;
572 /* Cut out the PCI hole */
573 if (mem_base <= RamSize && next_base > RamSize) {
574 mem_len -= next_base - RamSize;
576 acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
580 mem_base = 1ULL << 32;
581 mem_len = next_base - RamSize;
582 next_base += (1ULL << 32) - RamSize;
584 acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
588 for (; slots < nb_numa_nodes + 2; slots++) {
589 acpi_build_srat_memory(numamem, 0, 0, 0, 0);
593 build_header((void*)srat, SRAT_SIGNATURE, srat_size, 1);
598 struct rsdp_descriptor *RsdpAddr;
600 #define MAX_ACPI_TABLES 20
607 dprintf(3, "init ACPI tables\n");
609 // This code is hardcoded for PIIX4 Power Management device.
610 int bdf = pci_find_device(PCI_VENDOR_ID_INTEL
611 , PCI_DEVICE_ID_INTEL_82371AB_3);
616 // Create initial rsdt table
617 struct rsdp_descriptor *rsdp = malloc_fseg(sizeof(*rsdp));
619 dprintf(1, "Not enough memory for acpi rsdp table!\n");
623 u32 tables[MAX_ACPI_TABLES], tbl_idx = 0;
625 #define ACPI_INIT_TABLE(X) \
627 tables[tbl_idx] = (u32)(X); \
628 if (tables[tbl_idx]) \
633 ACPI_INIT_TABLE(build_fadt(bdf));
634 ACPI_INIT_TABLE(build_ssdt());
635 ACPI_INIT_TABLE(build_madt());
636 ACPI_INIT_TABLE(build_hpet());
637 ACPI_INIT_TABLE(build_srat());
639 u16 i, external_tables = qemu_cfg_acpi_additional_tables();
641 for(i = 0; i < external_tables; i++) {
642 u16 len = qemu_cfg_next_acpi_table_len();
643 void *addr = malloc_high(len);
645 dprintf(1, "Not enough memory for ext acpi table of size %d!\n"
649 ACPI_INIT_TABLE(qemu_cfg_next_acpi_table_load(addr, len));
650 if (tbl_idx == MAX_ACPI_TABLES) {
651 dprintf(1, "Too many external tables!\n");
656 struct rsdt_descriptor_rev1 *rsdt;
657 size_t rsdt_len = sizeof(*rsdt) + sizeof(u32) * tbl_idx;
658 rsdt = malloc_high(rsdt_len);
661 dprintf(1, "Not enough memory for acpi rsdt table!\n");
664 memset(rsdt, 0, rsdt_len);
665 memcpy(rsdt->table_offset_entry, tables, sizeof(u32) * tbl_idx);
667 build_header((void*)rsdt, RSDT_SIGNATURE, rsdt_len, 1);
669 // Build rsdp pointer table
670 memset(rsdp, 0, sizeof(*rsdp));
671 rsdp->signature = RSDP_SIGNATURE;
672 memcpy(rsdp->oem_id, CONFIG_APPNAME6, 6);
673 rsdp->rsdt_physical_address = cpu_to_le32((u32)rsdt);
674 rsdp->checksum -= checksum(rsdp, 20);
676 dprintf(1, "ACPI tables: RSDP=%p RSDT=%p\n", rsdp, rsdt);
680 find_resume_vector(void)
682 dprintf(4, "rsdp=%p\n", RsdpAddr);
683 if (!RsdpAddr || RsdpAddr->signature != RSDP_SIGNATURE)
685 struct rsdt_descriptor_rev1 *rsdt = (void*)RsdpAddr->rsdt_physical_address;
686 dprintf(4, "rsdt=%p\n", rsdt);
687 if (!rsdt || rsdt->signature != RSDT_SIGNATURE)
689 void *end = (void*)rsdt + rsdt->length;
691 for (i=0; (void*)&rsdt->table_offset_entry[i] < end; i++) {
692 struct fadt_descriptor_rev1 *fadt = (void*)rsdt->table_offset_entry[i];
693 if (!fadt || fadt->signature != FACP_SIGNATURE)
695 dprintf(4, "fadt=%p\n", fadt);
696 struct facs_descriptor_rev1 *facs = (void*)fadt->firmware_ctrl;
697 dprintf(4, "facs=%p\n", facs);
698 if (! facs || facs->signature != FACS_SIGNATURE)
701 dprintf(4, "resume addr=%d\n", facs->firmware_waking_vector);
702 return facs->firmware_waking_vector;