2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
83 config SCONFIG_GENPARSER
84 bool "Generate SCONFIG parser using flex and bison"
88 Enable this option if you are working on the sconfig
89 device tree parser and made changes to sconfig.l and
93 config USE_OPTION_TABLE
94 bool "Use CMOS for configuration values"
96 depends on HAVE_OPTION_TABLE
98 Enable this option if coreboot shall read options from the "CMOS"
99 NVRAM instead of using hard coded values.
103 source src/mainboard/Kconfig
105 # This option is used to set the architecture of a mainboard to X86.
106 # It is usually set in mainboard/*/Kconfig.
112 source src/arch/x86/Kconfig
118 source src/cpu/Kconfig
119 comment "Northbridge"
120 source src/northbridge/Kconfig
121 comment "Southbridge"
122 source src/southbridge/Kconfig
124 source src/superio/Kconfig
126 source src/devices/Kconfig
127 comment "Embedded Controllers"
128 source src/ec/Kconfig
132 menu "Generic Drivers"
133 source src/drivers/Kconfig
136 config PCI_BUS_SEGN_BITS
152 config MMCONF_SUPPORT_DEFAULT
156 config MMCONF_SUPPORT
163 source src/console/Kconfig
165 config HAVE_ACPI_RESUME
169 config HAVE_ACPI_SLIC
173 config ACPI_SSDTX_NUM
177 config HAVE_HARD_RESET
179 default y if BOARD_HAS_HARD_RESET
182 This variable specifies whether a given board has a hard_reset
183 function, no matter if it's provided by board code or chipset code.
185 config HAVE_INIT_TIMER
187 default n if UDELAY_IO
190 config HAVE_MAINBOARD_RESOURCES
194 config USE_OPTION_TABLE
198 config HAVE_OPTION_TABLE
202 This variable specifies whether a given board has a cmos.layout
203 file containing NVRAM/CMOS bit definitions.
204 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
210 config HAVE_SMI_HANDLER
214 config PCI_IO_CFG_EXT
222 # TODO: Can probably be removed once all chipsets have kconfig options for it.
227 config USE_WATCHDOG_ON_BOOT
235 Build board-specific VGA code.
241 Enable Unified Memory Architecture for graphics.
248 config HAVE_ACPI_TABLES
251 This variable specifies whether a given board has ACPI table support.
252 It is usually set in mainboard/*/Kconfig.
253 Whether or not the ACPI tables are actually generated by coreboot
254 is configurable by the user via GENERATE_ACPI_TABLES.
259 This variable specifies whether a given board has MP table support.
260 It is usually set in mainboard/*/Kconfig.
261 Whether or not the MP table is actually generated by coreboot
262 is configurable by the user via GENERATE_MP_TABLE.
264 config HAVE_PIRQ_TABLE
267 This variable specifies whether a given board has PIRQ table support.
268 It is usually set in mainboard/*/Kconfig.
269 Whether or not the PIRQ table is actually generated by coreboot
270 is configurable by the user via GENERATE_PIRQ_TABLE.
272 #These Options are here to avoid "undefined" warnings.
273 #The actual selection and help texts are in the following menu.
275 config GENERATE_ACPI_TABLES
277 default HAVE_ACPI_TABLES
279 config GENERATE_MP_TABLE
281 default HAVE_MP_TABLE
283 config GENERATE_PIRQ_TABLE
285 default HAVE_PIRQ_TABLE
289 config WRITE_HIGH_TABLES
290 bool "Write 'high' tables to avoid being overwritten in F segment"
294 bool "Generate Multiboot tables (for GRUB2)"
297 config GENERATE_ACPI_TABLES
298 depends on HAVE_ACPI_TABLES
299 bool "Generate ACPI tables"
302 Generate ACPI tables for this board.
306 config GENERATE_MP_TABLE
307 depends on HAVE_MP_TABLE
308 bool "Generate an MP table"
311 Generate an MP table (conforming to the Intel MultiProcessor
312 specification 1.4) for this board.
316 config GENERATE_PIRQ_TABLE
317 depends on HAVE_PIRQ_TABLE
318 bool "Generate a PIRQ table"
321 Generate a PIRQ table for this board.
330 prompt "Add a payload"
331 default PAYLOAD_NONE if !ARCH_X86
332 default PAYLOAD_SEABIOS if ARCH_X86
337 Select this option if you want to create an "empty" coreboot
338 ROM image for a certain mainboard, i.e. a coreboot ROM image
339 which does not yet contain a payload.
341 For such an image to be useful, you have to use 'cbfstool'
342 to add a payload to the ROM image later.
345 bool "An ELF executable payload"
347 Select this option if you have a payload image (an ELF file)
348 which coreboot should run as soon as the basic hardware
349 initialization is completed.
351 You will be able to specify the location and file name of the
354 config PAYLOAD_SEABIOS
358 Select this option if you want to build a coreboot image
359 with a SeaBIOS payload. If you don't know what this is
360 about, just leave it enabled.
362 See http://coreboot.org/Payloads for more information.
367 prompt "SeaBIOS version"
368 default SEABIOS_STABLE
369 depends on PAYLOAD_SEABIOS
371 config SEABIOS_STABLE
374 Stable SeaBIOS version
375 config SEABIOS_MASTER
378 Newest SeaBIOS version
382 string "Payload path and filename"
383 depends on PAYLOAD_ELF
384 default "payload.elf"
386 The path and filename of the ELF executable file to use as payload.
389 depends on PAYLOAD_SEABIOS
390 default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
392 # TODO: Defined if no payload? Breaks build?
393 config COMPRESSED_PAYLOAD_LZMA
394 bool "Use LZMA compression for payloads"
396 depends on PAYLOAD_ELF || PAYLOAD_SEABIOS
398 In order to reduce the size payloads take up in the ROM chip
399 coreboot can compress them using the LZMA algorithm.
401 config COMPRESSED_PAYLOAD_NRV2B
410 bool "Add a VGA BIOS image"
412 Select this option if you have a VGA BIOS image that you would
413 like to add to your ROM.
415 You will be able to specify the location and file name of the
419 string "VGA BIOS path and filename"
421 default "vgabios.bin"
423 The path and filename of the file to use as VGA BIOS.
426 string "VGA device PCI IDs"
430 The comma-separated PCI vendor and device ID that would associate
431 your VGA BIOS to your video card.
435 In the above example 1106 is the PCI vendor ID (in hex, but without
436 the "0x" prefix) and 3230 specifies the PCI device ID of the
437 video card (also in hex, without "0x" prefix).
440 bool "Add an MBI image"
441 depends on NORTHBRIDGE_INTEL_I82830
443 Select this option if you have an Intel MBI image that you would
444 like to add to your ROM.
446 You will be able to specify the location and file name of the
450 string "Intel MBI path and filename"
454 The path and filename of the file to use as VGA BIOS.
459 depends on PCI_OPTION_ROM_RUN_YABEL
462 prompt "Show graphical bootsplash"
464 depends on PCI_OPTION_ROM_RUN_YABEL
466 This option shows a graphical bootsplash screen. The grapics are
467 loaded from the CBFS file bootsplash.jpg.
469 config BOOTSPLASH_FILE
470 string "Bootsplash path and filename"
471 depends on BOOTSPLASH
472 default "bootsplash.jpg"
474 The path and filename of the file to use as graphical bootsplash
475 screen. The file format has to be jpg.
477 # TODO: Turn this into a "choice".
478 config FRAMEBUFFER_VESA_MODE
479 prompt "VESA framebuffer video mode"
482 depends on BOOTSPLASH
484 This option sets the resolution used for the coreboot framebuffer and
485 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
486 some day make this a "choice".
488 config COREBOOT_KEEP_FRAMEBUFFER
489 prompt "Keep VESA framebuffer"
491 depends on BOOTSPLASH
493 This option keeps the framebuffer mode set after coreboot finishes
494 execution. If this option is enabled, coreboot will pass a
495 framebuffer entry in its coreboot table and the payload will need a
496 framebuffer driver. If this option is disabled, coreboot will switch
497 back to text mode before handing control to a payload.
503 # TODO: Better help text and detailed instructions.
505 bool "GDB debugging support"
508 If enabled, you will be able to set breakpoints for gdb debugging.
509 See src/arch/x86/lib/c_start.S for details.
511 config HAVE_DEBUG_RAM_SETUP
514 config DEBUG_RAM_SETUP
515 bool "Output verbose RAM init debug messages"
517 depends on HAVE_DEBUG_RAM_SETUP
519 This option enables additional RAM init related debug messages.
520 It is recommended to enable this when debugging issues on your
521 board which might be RAM init related.
523 Note: This option will increase the size of the coreboot image.
527 config HAVE_DEBUG_CAR
532 depends on HAVE_DEBUG_CAR
534 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
535 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
536 # printk(BIOS_DEBUG, ...) calls.
538 bool "Output verbose Cache-as-RAM debug messages"
540 depends on HAVE_DEBUG_CAR
542 This option enables additional CAR related debug messages.
546 bool "Check PIRQ table consistency"
548 depends on GENERATE_PIRQ_TABLE
552 config HAVE_DEBUG_SMBUS
556 bool "Output verbose SMBus debug messages"
558 depends on HAVE_DEBUG_SMBUS
560 This option enables additional SMBus (and SPD) debug messages.
562 Note: This option will increase the size of the coreboot image.
567 bool "Output verbose SMI debug messages"
569 depends on HAVE_SMI_HANDLER
571 This option enables additional SMI related debug messages.
573 Note: This option will increase the size of the coreboot image.
577 config DEBUG_SMM_RELOCATION
578 bool "Debug SMM relocation code"
580 depends on HAVE_SMI_HANDLER
582 This option enables additional SMM handler relocation related
585 Note: This option will increase the size of the coreboot image.
592 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
593 # printk(BIOS_DEBUG, ...) calls.
594 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
596 bool "Output verbose malloc debug messages"
599 This option enables additional malloc related debug messages.
601 Note: This option will increase the size of the coreboot image.
606 config REALMODE_DEBUG
608 depends on PCI_OPTION_ROM_RUN_REALMODE
610 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
611 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
612 # printk(BIOS_DEBUG, ...) calls.
613 config REALMODE_DEBUG
614 bool "Enable debug messages for option ROM execution"
616 depends on PCI_OPTION_ROM_RUN_REALMODE
618 This option enables additional x86emu related debug messages.
620 Note: This option will increase the time to emulate a ROM.
626 bool "Output verbose x86emu debug messages"
628 depends on PCI_OPTION_ROM_RUN_YABEL
630 This option enables additional x86emu related debug messages.
632 Note: This option will increase the size of the coreboot image.
636 config X86EMU_DEBUG_JMP
637 bool "Trace JMP/RETF"
639 depends on X86EMU_DEBUG
641 Print information about JMP and RETF opcodes from x86emu.
643 Note: This option will increase the size of the coreboot image.
647 config X86EMU_DEBUG_TRACE
648 bool "Trace all opcodes"
650 depends on X86EMU_DEBUG
652 Print _all_ opcodes that are executed by x86emu.
654 WARNING: This will produce a LOT of output and take a long time.
656 Note: This option will increase the size of the coreboot image.
660 config X86EMU_DEBUG_PNP
661 bool "Log Plug&Play accesses"
663 depends on X86EMU_DEBUG
665 Print Plug And Play accesses made by option ROMs.
667 Note: This option will increase the size of the coreboot image.
671 config X86EMU_DEBUG_DISK
674 depends on X86EMU_DEBUG
676 Print Disk I/O related messages.
678 Note: This option will increase the size of the coreboot image.
682 config X86EMU_DEBUG_PMM
685 depends on X86EMU_DEBUG
687 Print messages related to POST Memory Manager (PMM).
689 Note: This option will increase the size of the coreboot image.
694 config X86EMU_DEBUG_VBE
695 bool "Debug VESA BIOS Extensions"
697 depends on X86EMU_DEBUG
699 Print messages related to VESA BIOS Extension (VBE) functions.
701 Note: This option will increase the size of the coreboot image.
705 config X86EMU_DEBUG_INT10
706 bool "Redirect INT10 output to console"
708 depends on X86EMU_DEBUG
710 Let INT10 (i.e. character output) calls print messages to debug output.
712 Note: This option will increase the size of the coreboot image.
716 config X86EMU_DEBUG_INTERRUPTS
717 bool "Log intXX calls"
719 depends on X86EMU_DEBUG
721 Print messages related to interrupt handling.
723 Note: This option will increase the size of the coreboot image.
727 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
728 bool "Log special memory accesses"
730 depends on X86EMU_DEBUG
732 Print messages related to accesses to certain areas of the virtual
733 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
735 Note: This option will increase the size of the coreboot image.
739 config X86EMU_DEBUG_MEM
740 bool "Log all memory accesses"
742 depends on X86EMU_DEBUG
744 Print memory accesses made by option ROM.
745 Note: This also includes accesses to fetch instructions.
747 Note: This option will increase the size of the coreboot image.
751 config X86EMU_DEBUG_IO
752 bool "Log IO accesses"
754 depends on X86EMU_DEBUG
756 Print I/O accesses made by option ROM.
758 Note: This option will increase the size of the coreboot image.
763 bool "Built-in low-level shell"
766 If enabled, you will have a low level shell to examine your machine.
767 Put llshell() in your (romstage) code to start the shell.
768 See src/arch/x86/llshell/llshell.inc for details.
772 config LIFT_BSP_APIC_ID
776 # These probably belong somewhere else, but they are needed somewhere.
777 config AP_CODE_IN_CAR
781 config RAMINIT_SYSINFO
785 config ENABLE_APIC_EXT_ID
789 config WARNINGS_ARE_ERRORS
793 config ID_SECTION_OFFSET
797 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
798 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
799 # mutually exclusive. One of these options must be selected in the
800 # mainboard Kconfig if the chipset supports enabling and disabling of
801 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
802 # in mainboard/Kconfig to know if the button should be enabled or not.
804 config POWER_BUTTON_DEFAULT_ENABLE
807 Select when the board has a power button which can optionally be
808 disabled by the user.
810 config POWER_BUTTON_DEFAULT_DISABLE
813 Select when the board has a power button which can optionally be
814 enabled by the user, e.g. when the board ships with a jumper over
815 the power switch contacts.
817 config POWER_BUTTON_FORCE_ENABLE
820 Select when the board requires that the power button is always
823 config POWER_BUTTON_FORCE_DISABLE
826 Select when the board requires that the power button is always
827 disabled, e.g. when it has been hardwired to ground.
829 config POWER_BUTTON_IS_OPTIONAL
831 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
832 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
834 Internal option that controls ENABLE_POWER_BUTTON visibility.
836 source src/Kconfig.deprecated_options