2 * mini-arm64.c: ARM64 backend for the Mono code generator
4 * Copyright 2013 Xamarin, Inc (http://www.xamarin.com)
9 * Paolo Molaro (lupus@ximian.com)
10 * Dietmar Maurer (dietmar@ximian.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
15 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
19 #include "cpu-arm64.h"
22 #include <mono/arch/arm64/arm64-codegen.h>
23 #include <mono/utils/mono-mmap.h>
24 #include <mono/utils/mono-memory-model.h>
25 #include <mono/metadata/abi-details.h>
30 * - ARM(R) Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile (DDI0487A_a_armv8_arm.pdf)
31 * - Procedure Call Standard for the ARM 64-bit Architecture (AArch64) (IHI0055B_aapcs64.pdf)
32 * - ELF for the ARM 64-bit Architecture (IHI0056B_aaelf64.pdf)
35 * - ip0/ip1/lr are used as temporary registers
36 * - r27 is used as the rgctx/imt register
37 * - r28 is used to access arguments passed on the stack
38 * - d15/d16 are used as fp temporary registers
41 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
43 #define FP_TEMP_REG ARMREG_D16
44 #define FP_TEMP_REG2 ARMREG_D17
46 #define THUNK_SIZE (4 * 4)
48 /* The single step trampoline */
49 static gpointer ss_trampoline;
51 /* The breakpoint trampoline */
52 static gpointer bp_trampoline;
54 static gboolean ios_abi;
56 static __attribute__((warn_unused_result)) guint8* emit_load_regset (guint8 *code, guint64 regs, int basereg, int offset);
59 mono_arch_regname (int reg)
61 static const char * rnames[] = {
62 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
63 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
64 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "fp",
67 if (reg >= 0 && reg < 32)
73 mono_arch_fregname (int reg)
75 static const char * rnames[] = {
76 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9",
77 "d10", "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19",
78 "d20", "d21", "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29",
81 if (reg >= 0 && reg < 32)
87 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
93 #define MAX_ARCH_DELEGATE_PARAMS 7
96 get_delegate_invoke_impl (gboolean has_target, gboolean param_count, guint32 *code_size)
101 start = code = mono_global_codeman_reserve (12);
103 /* Replace the this argument with the target */
104 arm_ldrx (code, ARMREG_IP0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
105 arm_ldrx (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
106 arm_brx (code, ARMREG_IP0);
108 g_assert ((code - start) <= 12);
110 mono_arch_flush_icache (start, 12);
114 size = 8 + param_count * 4;
115 start = code = mono_global_codeman_reserve (size);
117 arm_ldrx (code, ARMREG_IP0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
118 /* slide down the arguments */
119 for (i = 0; i < param_count; ++i)
120 arm_movx (code, i, i + 1);
121 arm_brx (code, ARMREG_IP0);
123 g_assert ((code - start) <= size);
125 mono_arch_flush_icache (start, size);
129 *code_size = code - start;
135 * mono_arch_get_delegate_invoke_impls:
137 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
141 mono_arch_get_delegate_invoke_impls (void)
149 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
150 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
152 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
153 code = get_delegate_invoke_impl (FALSE, i, &code_len);
154 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
155 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
163 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
165 guint8 *code, *start;
168 * vtypes are returned in registers, or using the dedicated r8 register, so
169 * they can be supported by delegate invokes.
173 static guint8* cached = NULL;
179 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
181 start = get_delegate_invoke_impl (TRUE, 0, NULL);
182 mono_memory_barrier ();
186 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
189 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
191 for (i = 0; i < sig->param_count; ++i)
192 if (!mono_is_regsize_var (sig->params [i]))
195 code = cache [sig->param_count];
200 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
201 start = mono_aot_get_trampoline (name);
204 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
206 mono_memory_barrier ();
207 cache [sig->param_count] = start;
215 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
221 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
223 return (gpointer)regs [ARMREG_R0];
227 mono_arch_cpu_init (void)
232 mono_arch_init (void)
234 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
235 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
238 bp_trampoline = mini_get_breakpoint_trampoline ();
240 mono_arm_gsharedvt_init ();
242 #if defined(TARGET_IOS)
248 mono_arch_cleanup (void)
253 mono_arch_cpu_optimizations (guint32 *exclude_mask)
260 mono_arch_cpu_enumerate_simd_versions (void)
266 mono_arch_register_lowlevel_calls (void)
271 mono_arch_finish_init (void)
275 /* The maximum length is 2 instructions */
277 emit_imm (guint8 *code, int dreg, int imm)
279 // FIXME: Optimize this
282 arm_movnx (code, dreg, (~limm) & 0xffff, 0);
283 arm_movkx (code, dreg, (limm >> 16) & 0xffff, 16);
285 arm_movzx (code, dreg, imm & 0xffff, 0);
287 arm_movkx (code, dreg, (imm >> 16) & 0xffff, 16);
293 /* The maximum length is 4 instructions */
295 emit_imm64 (guint8 *code, int dreg, guint64 imm)
297 // FIXME: Optimize this
298 arm_movzx (code, dreg, imm & 0xffff, 0);
299 if ((imm >> 16) & 0xffff)
300 arm_movkx (code, dreg, (imm >> 16) & 0xffff, 16);
301 if ((imm >> 32) & 0xffff)
302 arm_movkx (code, dreg, (imm >> 32) & 0xffff, 32);
303 if ((imm >> 48) & 0xffff)
304 arm_movkx (code, dreg, (imm >> 48) & 0xffff, 48);
310 mono_arm_emit_imm64 (guint8 *code, int dreg, gint64 imm)
312 return emit_imm64 (code, dreg, imm);
318 * Emit a patchable code sequence for constructing a 64 bit immediate.
321 emit_imm64_template (guint8 *code, int dreg)
323 arm_movzx (code, dreg, 0, 0);
324 arm_movkx (code, dreg, 0, 16);
325 arm_movkx (code, dreg, 0, 32);
326 arm_movkx (code, dreg, 0, 48);
331 static inline __attribute__((warn_unused_result)) guint8*
332 emit_addw_imm (guint8 *code, int dreg, int sreg, int imm)
334 if (!arm_is_arith_imm (imm)) {
335 code = emit_imm (code, ARMREG_LR, imm);
336 arm_addw (code, dreg, sreg, ARMREG_LR);
338 arm_addw_imm (code, dreg, sreg, imm);
343 static inline __attribute__((warn_unused_result)) guint8*
344 emit_addx_imm (guint8 *code, int dreg, int sreg, int imm)
346 if (!arm_is_arith_imm (imm)) {
347 code = emit_imm (code, ARMREG_LR, imm);
348 arm_addx (code, dreg, sreg, ARMREG_LR);
350 arm_addx_imm (code, dreg, sreg, imm);
355 static inline __attribute__((warn_unused_result)) guint8*
356 emit_subw_imm (guint8 *code, int dreg, int sreg, int imm)
358 if (!arm_is_arith_imm (imm)) {
359 code = emit_imm (code, ARMREG_LR, imm);
360 arm_subw (code, dreg, sreg, ARMREG_LR);
362 arm_subw_imm (code, dreg, sreg, imm);
367 static inline __attribute__((warn_unused_result)) guint8*
368 emit_subx_imm (guint8 *code, int dreg, int sreg, int imm)
370 if (!arm_is_arith_imm (imm)) {
371 code = emit_imm (code, ARMREG_LR, imm);
372 arm_subx (code, dreg, sreg, ARMREG_LR);
374 arm_subx_imm (code, dreg, sreg, imm);
379 /* Emit sp+=imm. Clobbers ip0/ip1 */
380 static inline __attribute__((warn_unused_result)) guint8*
381 emit_addx_sp_imm (guint8 *code, int imm)
383 code = emit_imm (code, ARMREG_IP0, imm);
384 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
385 arm_addx (code, ARMREG_IP1, ARMREG_IP1, ARMREG_IP0);
386 arm_movspx (code, ARMREG_SP, ARMREG_IP1);
390 /* Emit sp-=imm. Clobbers ip0/ip1 */
391 static inline __attribute__((warn_unused_result)) guint8*
392 emit_subx_sp_imm (guint8 *code, int imm)
394 code = emit_imm (code, ARMREG_IP0, imm);
395 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
396 arm_subx (code, ARMREG_IP1, ARMREG_IP1, ARMREG_IP0);
397 arm_movspx (code, ARMREG_SP, ARMREG_IP1);
401 static inline __attribute__((warn_unused_result)) guint8*
402 emit_andw_imm (guint8 *code, int dreg, int sreg, int imm)
405 code = emit_imm (code, ARMREG_LR, imm);
406 arm_andw (code, dreg, sreg, ARMREG_LR);
411 static inline __attribute__((warn_unused_result)) guint8*
412 emit_andx_imm (guint8 *code, int dreg, int sreg, int imm)
415 code = emit_imm (code, ARMREG_LR, imm);
416 arm_andx (code, dreg, sreg, ARMREG_LR);
421 static inline __attribute__((warn_unused_result)) guint8*
422 emit_orrw_imm (guint8 *code, int dreg, int sreg, int imm)
425 code = emit_imm (code, ARMREG_LR, imm);
426 arm_orrw (code, dreg, sreg, ARMREG_LR);
431 static inline __attribute__((warn_unused_result)) guint8*
432 emit_orrx_imm (guint8 *code, int dreg, int sreg, int imm)
435 code = emit_imm (code, ARMREG_LR, imm);
436 arm_orrx (code, dreg, sreg, ARMREG_LR);
441 static inline __attribute__((warn_unused_result)) guint8*
442 emit_eorw_imm (guint8 *code, int dreg, int sreg, int imm)
445 code = emit_imm (code, ARMREG_LR, imm);
446 arm_eorw (code, dreg, sreg, ARMREG_LR);
451 static inline __attribute__((warn_unused_result)) guint8*
452 emit_eorx_imm (guint8 *code, int dreg, int sreg, int imm)
455 code = emit_imm (code, ARMREG_LR, imm);
456 arm_eorx (code, dreg, sreg, ARMREG_LR);
461 static inline __attribute__((warn_unused_result)) guint8*
462 emit_cmpw_imm (guint8 *code, int sreg, int imm)
465 arm_cmpw (code, sreg, ARMREG_RZR);
468 code = emit_imm (code, ARMREG_LR, imm);
469 arm_cmpw (code, sreg, ARMREG_LR);
475 static inline __attribute__((warn_unused_result)) guint8*
476 emit_cmpx_imm (guint8 *code, int sreg, int imm)
479 arm_cmpx (code, sreg, ARMREG_RZR);
482 code = emit_imm (code, ARMREG_LR, imm);
483 arm_cmpx (code, sreg, ARMREG_LR);
489 static inline __attribute__((warn_unused_result)) guint8*
490 emit_strb (guint8 *code, int rt, int rn, int imm)
492 if (arm_is_strb_imm (imm)) {
493 arm_strb (code, rt, rn, imm);
495 g_assert (rt != ARMREG_IP0);
496 g_assert (rn != ARMREG_IP0);
497 code = emit_imm (code, ARMREG_IP0, imm);
498 arm_strb_reg (code, rt, rn, ARMREG_IP0);
503 static inline __attribute__((warn_unused_result)) guint8*
504 emit_strh (guint8 *code, int rt, int rn, int imm)
506 if (arm_is_strh_imm (imm)) {
507 arm_strh (code, rt, rn, imm);
509 g_assert (rt != ARMREG_IP0);
510 g_assert (rn != ARMREG_IP0);
511 code = emit_imm (code, ARMREG_IP0, imm);
512 arm_strh_reg (code, rt, rn, ARMREG_IP0);
517 static inline __attribute__((warn_unused_result)) guint8*
518 emit_strw (guint8 *code, int rt, int rn, int imm)
520 if (arm_is_strw_imm (imm)) {
521 arm_strw (code, rt, rn, imm);
523 g_assert (rt != ARMREG_IP0);
524 g_assert (rn != ARMREG_IP0);
525 code = emit_imm (code, ARMREG_IP0, imm);
526 arm_strw_reg (code, rt, rn, ARMREG_IP0);
531 static inline __attribute__((warn_unused_result)) guint8*
532 emit_strfpw (guint8 *code, int rt, int rn, int imm)
534 if (arm_is_strw_imm (imm)) {
535 arm_strfpw (code, rt, rn, imm);
537 g_assert (rn != ARMREG_IP0);
538 code = emit_imm (code, ARMREG_IP0, imm);
539 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
540 arm_strfpw (code, rt, ARMREG_IP0, 0);
545 static inline __attribute__((warn_unused_result)) guint8*
546 emit_strfpx (guint8 *code, int rt, int rn, int imm)
548 if (arm_is_strx_imm (imm)) {
549 arm_strfpx (code, rt, rn, imm);
551 g_assert (rn != ARMREG_IP0);
552 code = emit_imm (code, ARMREG_IP0, imm);
553 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
554 arm_strfpx (code, rt, ARMREG_IP0, 0);
559 static inline __attribute__((warn_unused_result)) guint8*
560 emit_strx (guint8 *code, int rt, int rn, int imm)
562 if (arm_is_strx_imm (imm)) {
563 arm_strx (code, rt, rn, imm);
565 g_assert (rt != ARMREG_IP0);
566 g_assert (rn != ARMREG_IP0);
567 code = emit_imm (code, ARMREG_IP0, imm);
568 arm_strx_reg (code, rt, rn, ARMREG_IP0);
573 static inline __attribute__((warn_unused_result)) guint8*
574 emit_ldrb (guint8 *code, int rt, int rn, int imm)
576 if (arm_is_pimm12_scaled (imm, 1)) {
577 arm_ldrb (code, rt, rn, imm);
579 g_assert (rt != ARMREG_IP0);
580 g_assert (rn != ARMREG_IP0);
581 code = emit_imm (code, ARMREG_IP0, imm);
582 arm_ldrb_reg (code, rt, rn, ARMREG_IP0);
587 static inline __attribute__((warn_unused_result)) guint8*
588 emit_ldrsbx (guint8 *code, int rt, int rn, int imm)
590 if (arm_is_pimm12_scaled (imm, 1)) {
591 arm_ldrsbx (code, rt, rn, imm);
593 g_assert (rt != ARMREG_IP0);
594 g_assert (rn != ARMREG_IP0);
595 code = emit_imm (code, ARMREG_IP0, imm);
596 arm_ldrsbx_reg (code, rt, rn, ARMREG_IP0);
601 static inline __attribute__((warn_unused_result)) guint8*
602 emit_ldrh (guint8 *code, int rt, int rn, int imm)
604 if (arm_is_pimm12_scaled (imm, 2)) {
605 arm_ldrh (code, rt, rn, imm);
607 g_assert (rt != ARMREG_IP0);
608 g_assert (rn != ARMREG_IP0);
609 code = emit_imm (code, ARMREG_IP0, imm);
610 arm_ldrh_reg (code, rt, rn, ARMREG_IP0);
615 static inline __attribute__((warn_unused_result)) guint8*
616 emit_ldrshx (guint8 *code, int rt, int rn, int imm)
618 if (arm_is_pimm12_scaled (imm, 2)) {
619 arm_ldrshx (code, rt, rn, imm);
621 g_assert (rt != ARMREG_IP0);
622 g_assert (rn != ARMREG_IP0);
623 code = emit_imm (code, ARMREG_IP0, imm);
624 arm_ldrshx_reg (code, rt, rn, ARMREG_IP0);
629 static inline __attribute__((warn_unused_result)) guint8*
630 emit_ldrswx (guint8 *code, int rt, int rn, int imm)
632 if (arm_is_pimm12_scaled (imm, 4)) {
633 arm_ldrswx (code, rt, rn, imm);
635 g_assert (rt != ARMREG_IP0);
636 g_assert (rn != ARMREG_IP0);
637 code = emit_imm (code, ARMREG_IP0, imm);
638 arm_ldrswx_reg (code, rt, rn, ARMREG_IP0);
643 static inline __attribute__((warn_unused_result)) guint8*
644 emit_ldrw (guint8 *code, int rt, int rn, int imm)
646 if (arm_is_pimm12_scaled (imm, 4)) {
647 arm_ldrw (code, rt, rn, imm);
649 g_assert (rn != ARMREG_IP0);
650 code = emit_imm (code, ARMREG_IP0, imm);
651 arm_ldrw_reg (code, rt, rn, ARMREG_IP0);
656 static inline __attribute__((warn_unused_result)) guint8*
657 emit_ldrx (guint8 *code, int rt, int rn, int imm)
659 if (arm_is_pimm12_scaled (imm, 8)) {
660 arm_ldrx (code, rt, rn, imm);
662 g_assert (rn != ARMREG_IP0);
663 code = emit_imm (code, ARMREG_IP0, imm);
664 arm_ldrx_reg (code, rt, rn, ARMREG_IP0);
669 static inline __attribute__((warn_unused_result)) guint8*
670 emit_ldrfpw (guint8 *code, int rt, int rn, int imm)
672 if (arm_is_pimm12_scaled (imm, 4)) {
673 arm_ldrfpw (code, rt, rn, imm);
675 g_assert (rn != ARMREG_IP0);
676 code = emit_imm (code, ARMREG_IP0, imm);
677 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
678 arm_ldrfpw (code, rt, ARMREG_IP0, 0);
683 static inline __attribute__((warn_unused_result)) guint8*
684 emit_ldrfpx (guint8 *code, int rt, int rn, int imm)
686 if (arm_is_pimm12_scaled (imm, 8)) {
687 arm_ldrfpx (code, rt, rn, imm);
689 g_assert (rn != ARMREG_IP0);
690 code = emit_imm (code, ARMREG_IP0, imm);
691 arm_addx (code, ARMREG_IP0, rn, ARMREG_IP0);
692 arm_ldrfpx (code, rt, ARMREG_IP0, 0);
698 mono_arm_emit_ldrx (guint8 *code, int rt, int rn, int imm)
700 return emit_ldrx (code, rt, rn, imm);
704 emit_call (MonoCompile *cfg, guint8* code, guint32 patch_type, gconstpointer data)
707 mono_add_patch_info_rel (cfg, code - cfg->native_code, patch_type, data, MONO_R_ARM64_IMM);
708 code = emit_imm64_template (code, ARMREG_LR);
709 arm_blrx (code, ARMREG_LR);
711 mono_add_patch_info_rel (cfg, code - cfg->native_code, patch_type, data, MONO_R_ARM64_BL);
713 cfg->thunk_area += THUNK_SIZE;
718 emit_aotconst_full (MonoCompile *cfg, MonoJumpInfo **ji, guint8 *code, guint8 *start, int dreg, guint32 patch_type, gconstpointer data)
721 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
723 *ji = mono_patch_info_list_prepend (*ji, code - start, patch_type, data);
724 /* See arch_emit_got_access () in aot-compiler.c */
725 arm_ldrx_lit (code, dreg, 0);
732 emit_aotconst (MonoCompile *cfg, guint8 *code, int dreg, guint32 patch_type, gconstpointer data)
734 return emit_aotconst_full (cfg, NULL, code, NULL, dreg, patch_type, data);
738 * mono_arm_emit_aotconst:
740 * Emit code to load an AOT constant into DREG. Usable from trampolines.
743 mono_arm_emit_aotconst (gpointer ji, guint8 *code, guint8 *code_start, int dreg, guint32 patch_type, gconstpointer data)
745 return emit_aotconst_full (NULL, (MonoJumpInfo**)ji, code, code_start, dreg, patch_type, data);
749 emit_tls_get (guint8 *code, int dreg, int tls_offset)
751 arm_mrs (code, dreg, ARM_MRS_REG_TPIDR_EL0);
752 if (tls_offset < 256) {
753 arm_ldrx (code, dreg, dreg, tls_offset);
755 code = emit_addx_imm (code, dreg, dreg, tls_offset);
756 arm_ldrx (code, dreg, dreg, 0);
762 emit_tls_get_reg (guint8 *code, int dreg, int offset_reg)
764 g_assert (offset_reg != ARMREG_IP0);
765 arm_mrs (code, ARMREG_IP0, ARM_MRS_REG_TPIDR_EL0);
766 arm_ldrx_reg (code, dreg, ARMREG_IP0, offset_reg);
771 emit_tls_set (guint8 *code, int sreg, int tls_offset)
773 int tmpreg = ARMREG_IP0;
775 g_assert (sreg != tmpreg);
776 arm_mrs (code, tmpreg, ARM_MRS_REG_TPIDR_EL0);
777 if (tls_offset < 256) {
778 arm_strx (code, sreg, tmpreg, tls_offset);
780 code = emit_addx_imm (code, tmpreg, tmpreg, tls_offset);
781 arm_strx (code, sreg, tmpreg, 0);
788 emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
790 int tmpreg = ARMREG_IP0;
792 g_assert (sreg != tmpreg);
793 arm_mrs (code, tmpreg, ARM_MRS_REG_TPIDR_EL0);
794 arm_strx_reg (code, sreg, tmpreg, offset_reg);
801 * - ldrp [fp, lr], [sp], !stack_offfset
802 * Clobbers TEMP_REGS.
804 __attribute__((warn_unused_result)) guint8*
805 mono_arm_emit_destroy_frame (guint8 *code, int stack_offset, guint64 temp_regs)
807 arm_movspx (code, ARMREG_SP, ARMREG_FP);
809 if (arm_is_ldpx_imm (stack_offset)) {
810 arm_ldpx_post (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, stack_offset);
812 arm_ldpx (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, 0);
813 /* sp += stack_offset */
814 g_assert (temp_regs & (1 << ARMREG_IP0));
815 if (temp_regs & (1 << ARMREG_IP1)) {
816 code = emit_addx_sp_imm (code, stack_offset);
818 int imm = stack_offset;
820 /* Can't use addx_sp_imm () since we can't clobber ip0/ip1 */
821 arm_addx_imm (code, ARMREG_IP0, ARMREG_SP, 0);
823 arm_addx_imm (code, ARMREG_IP0, ARMREG_IP0, 256);
826 arm_addx_imm (code, ARMREG_SP, ARMREG_IP0, imm);
832 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
835 emit_thunk (guint8 *code, gconstpointer target)
839 arm_ldrx_lit (code, ARMREG_IP0, code + 8);
840 arm_brx (code, ARMREG_IP0);
841 *(guint64*)code = (guint64)target;
843 mono_arch_flush_icache (p, code - p);
848 create_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
851 MonoThunkJitInfo *info;
855 guint8 *target_thunk;
858 domain = mono_domain_get ();
862 * This can be called multiple times during JITting,
863 * save the current position in cfg->arch to avoid
864 * doing a O(n^2) search.
866 if (!cfg->arch.thunks) {
867 cfg->arch.thunks = cfg->thunks;
868 cfg->arch.thunks_size = cfg->thunk_area;
870 thunks = cfg->arch.thunks;
871 thunks_size = cfg->arch.thunks_size;
873 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
874 g_assert_not_reached ();
877 g_assert (*(guint32*)thunks == 0);
878 emit_thunk (thunks, target);
880 cfg->arch.thunks += THUNK_SIZE;
881 cfg->arch.thunks_size -= THUNK_SIZE;
885 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
887 info = mono_jit_info_get_thunk_info (ji);
890 thunks = (guint8*)ji->code_start + info->thunks_offset;
891 thunks_size = info->thunks_size;
893 orig_target = mono_arch_get_call_target (code + 4);
895 mono_domain_lock (domain);
898 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
899 /* The call already points to a thunk, because of trampolines etc. */
900 target_thunk = orig_target;
902 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
903 if (((guint32*)p) [0] == 0) {
907 } else if (((guint64*)p) [1] == (guint64)target) {
908 /* Thunk already points to target */
915 //printf ("THUNK: %p %p %p\n", code, target, target_thunk);
918 mono_domain_unlock (domain);
919 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
920 g_assert_not_reached ();
923 emit_thunk (target_thunk, target);
925 mono_domain_unlock (domain);
932 arm_patch_full (MonoCompile *cfg, MonoDomain *domain, guint8 *code, guint8 *target, int relocation)
934 switch (relocation) {
936 arm_b (code, target);
938 case MONO_R_ARM64_BCC: {
941 cond = arm_get_bcc_cond (code);
942 arm_bcc (code, cond, target);
945 case MONO_R_ARM64_CBZ:
946 arm_set_cbz_target (code, target);
948 case MONO_R_ARM64_IMM: {
949 guint64 imm = (guint64)target;
952 /* emit_imm64_template () */
953 dreg = arm_get_movzx_rd (code);
954 arm_movzx (code, dreg, imm & 0xffff, 0);
955 arm_movkx (code, dreg, (imm >> 16) & 0xffff, 16);
956 arm_movkx (code, dreg, (imm >> 32) & 0xffff, 32);
957 arm_movkx (code, dreg, (imm >> 48) & 0xffff, 48);
960 case MONO_R_ARM64_BL:
961 if (arm_is_bl_disp (code, target)) {
962 arm_bl (code, target);
966 thunk = create_thunk (cfg, domain, code, target);
967 g_assert (arm_is_bl_disp (code, thunk));
968 arm_bl (code, thunk);
972 g_assert_not_reached ();
977 arm_patch_rel (guint8 *code, guint8 *target, int relocation)
979 arm_patch_full (NULL, NULL, code, target, relocation);
983 mono_arm_patch (guint8 *code, guint8 *target, int relocation)
985 arm_patch_rel (code, target, relocation);
989 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
993 ip = ji->ip.i + code;
996 case MONO_PATCH_INFO_METHOD_JUMP:
997 /* ji->relocation is not set by the caller */
998 arm_patch_rel (ip, (guint8*)target, MONO_R_ARM64_B);
1001 arm_patch_full (cfg, domain, ip, (guint8*)target, ji->relocation);
1007 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
1012 mono_arch_flush_register_windows (void)
1017 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
1019 return (gpointer)regs [MONO_ARCH_RGCTX_REG];
1023 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
1025 return (gpointer)regs [MONO_ARCH_RGCTX_REG];
1029 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
1031 return ctx->regs [reg];
1035 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
1037 ctx->regs [reg] = val;
1041 * mono_arch_set_target:
1043 * Set the target architecture the JIT backend should generate code for, in the form
1044 * of a GNU target triplet. Only used in AOT mode.
1047 mono_arch_set_target (char *mtriple)
1049 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
1055 add_general (CallInfo *cinfo, ArgInfo *ainfo, int size, gboolean sign)
1057 if (cinfo->gr >= PARAM_REGS) {
1058 ainfo->storage = ArgOnStack;
1060 /* Assume size == align */
1061 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, size);
1062 ainfo->offset = cinfo->stack_usage;
1063 ainfo->slot_size = size;
1065 cinfo->stack_usage += size;
1067 ainfo->offset = cinfo->stack_usage;
1068 ainfo->slot_size = 8;
1069 ainfo->sign = FALSE;
1070 /* Put arguments into 8 byte aligned stack slots */
1071 cinfo->stack_usage += 8;
1074 ainfo->storage = ArgInIReg;
1075 ainfo->reg = cinfo->gr;
1081 add_fp (CallInfo *cinfo, ArgInfo *ainfo, gboolean single)
1083 int size = single ? 4 : 8;
1085 if (cinfo->fr >= FP_PARAM_REGS) {
1086 ainfo->storage = single ? ArgOnStackR4 : ArgOnStackR8;
1088 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, size);
1089 ainfo->offset = cinfo->stack_usage;
1090 ainfo->slot_size = size;
1091 cinfo->stack_usage += size;
1093 ainfo->offset = cinfo->stack_usage;
1094 ainfo->slot_size = 8;
1095 /* Put arguments into 8 byte aligned stack slots */
1096 cinfo->stack_usage += 8;
1100 ainfo->storage = ArgInFRegR4;
1102 ainfo->storage = ArgInFReg;
1103 ainfo->reg = cinfo->fr;
1109 is_hfa (MonoType *t, int *out_nfields, int *out_esize, int *field_offsets)
1113 MonoClassField *field;
1114 MonoType *ftype, *prev_ftype = NULL;
1117 klass = mono_class_from_mono_type (t);
1119 while ((field = mono_class_get_fields (klass, &iter))) {
1120 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1122 ftype = mono_field_get_type (field);
1123 ftype = mini_get_underlying_type (ftype);
1125 if (MONO_TYPE_ISSTRUCT (ftype)) {
1126 int nested_nfields, nested_esize;
1127 int nested_field_offsets [16];
1129 if (!is_hfa (ftype, &nested_nfields, &nested_esize, nested_field_offsets))
1131 if (nested_esize == 4)
1132 ftype = &mono_defaults.single_class->byval_arg;
1134 ftype = &mono_defaults.double_class->byval_arg;
1135 if (prev_ftype && prev_ftype->type != ftype->type)
1138 for (i = 0; i < nested_nfields; ++i) {
1139 if (nfields + i < 4)
1140 field_offsets [nfields + i] = field->offset - sizeof (MonoObject) + nested_field_offsets [i];
1142 nfields += nested_nfields;
1144 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1146 if (prev_ftype && prev_ftype->type != ftype->type)
1150 field_offsets [nfields] = field->offset - sizeof (MonoObject);
1154 if (nfields == 0 || nfields > 4)
1156 *out_nfields = nfields;
1157 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1162 add_valuetype (CallInfo *cinfo, ArgInfo *ainfo, MonoType *t)
1164 int i, size, align_size, nregs, nfields, esize;
1165 int field_offsets [16];
1168 size = mini_type_stack_size_full (t, &align, FALSE);
1169 align_size = ALIGN_TO (size, 8);
1172 if (is_hfa (t, &nfields, &esize, field_offsets)) {
1174 * The struct might include nested float structs aligned at 8,
1175 * so need to keep track of the offsets of the individual fields.
1177 if (cinfo->fr + nfields <= FP_PARAM_REGS) {
1178 ainfo->storage = ArgHFA;
1179 ainfo->reg = cinfo->fr;
1180 ainfo->nregs = nfields;
1182 ainfo->esize = esize;
1183 for (i = 0; i < nfields; ++i)
1184 ainfo->foffsets [i] = field_offsets [i];
1185 cinfo->fr += ainfo->nregs;
1187 ainfo->nfregs_to_skip = FP_PARAM_REGS > cinfo->fr ? FP_PARAM_REGS - cinfo->fr : 0;
1188 cinfo->fr = FP_PARAM_REGS;
1189 size = ALIGN_TO (size, 8);
1190 ainfo->storage = ArgVtypeOnStack;
1191 ainfo->offset = cinfo->stack_usage;
1194 ainfo->nregs = nfields;
1195 ainfo->esize = esize;
1196 cinfo->stack_usage += size;
1201 if (align_size > 16) {
1202 ainfo->storage = ArgVtypeByRef;
1207 if (cinfo->gr + nregs > PARAM_REGS) {
1208 size = ALIGN_TO (size, 8);
1209 ainfo->storage = ArgVtypeOnStack;
1210 ainfo->offset = cinfo->stack_usage;
1212 cinfo->stack_usage += size;
1213 cinfo->gr = PARAM_REGS;
1215 ainfo->storage = ArgVtypeInIRegs;
1216 ainfo->reg = cinfo->gr;
1217 ainfo->nregs = nregs;
1224 add_param (CallInfo *cinfo, ArgInfo *ainfo, MonoType *t)
1228 ptype = mini_get_underlying_type (t);
1229 switch (ptype->type) {
1231 add_general (cinfo, ainfo, 1, TRUE);
1233 case MONO_TYPE_BOOLEAN:
1235 add_general (cinfo, ainfo, 1, FALSE);
1238 add_general (cinfo, ainfo, 2, TRUE);
1241 case MONO_TYPE_CHAR:
1242 add_general (cinfo, ainfo, 2, FALSE);
1245 add_general (cinfo, ainfo, 4, TRUE);
1248 add_general (cinfo, ainfo, 4, FALSE);
1253 case MONO_TYPE_FNPTR:
1254 case MONO_TYPE_CLASS:
1255 case MONO_TYPE_OBJECT:
1256 case MONO_TYPE_SZARRAY:
1257 case MONO_TYPE_ARRAY:
1258 case MONO_TYPE_STRING:
1261 add_general (cinfo, ainfo, 8, FALSE);
1264 add_fp (cinfo, ainfo, FALSE);
1267 add_fp (cinfo, ainfo, TRUE);
1269 case MONO_TYPE_VALUETYPE:
1270 case MONO_TYPE_TYPEDBYREF:
1271 add_valuetype (cinfo, ainfo, ptype);
1273 case MONO_TYPE_VOID:
1274 ainfo->storage = ArgNone;
1276 case MONO_TYPE_GENERICINST:
1277 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1278 add_general (cinfo, ainfo, 8, FALSE);
1279 } else if (mini_is_gsharedvt_variable_type (ptype)) {
1281 * Treat gsharedvt arguments as large vtypes
1283 ainfo->storage = ArgVtypeByRef;
1284 ainfo->gsharedvt = TRUE;
1286 add_valuetype (cinfo, ainfo, ptype);
1290 case MONO_TYPE_MVAR:
1291 g_assert (mini_is_gsharedvt_type (ptype));
1292 ainfo->storage = ArgVtypeByRef;
1293 ainfo->gsharedvt = TRUE;
1296 g_assert_not_reached ();
1304 * Obtain information about a call according to the calling convention.
1307 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1311 int n, pstart, pindex;
1313 n = sig->hasthis + sig->param_count;
1316 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1318 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1323 add_param (cinfo, &cinfo->ret, sig->ret);
1324 if (cinfo->ret.storage == ArgVtypeByRef)
1325 cinfo->ret.reg = ARMREG_R8;
1329 cinfo->stack_usage = 0;
1333 add_general (cinfo, cinfo->args + 0, 8, FALSE);
1335 for (pindex = pstart; pindex < sig->param_count; ++pindex) {
1336 ainfo = cinfo->args + sig->hasthis + pindex;
1338 if ((sig->call_convention == MONO_CALL_VARARG) && (pindex == sig->sentinelpos)) {
1339 /* Prevent implicit arguments and sig_cookie from
1340 being passed in registers */
1341 cinfo->gr = PARAM_REGS;
1342 cinfo->fr = FP_PARAM_REGS;
1343 /* Emit the signature cookie just before the implicit arguments */
1344 add_param (cinfo, &cinfo->sig_cookie, &mono_defaults.int_class->byval_arg);
1347 add_param (cinfo, ainfo, sig->params [pindex]);
1348 if (ainfo->storage == ArgVtypeByRef) {
1349 /* Pass the argument address in the next register */
1350 if (cinfo->gr >= PARAM_REGS) {
1351 ainfo->storage = ArgVtypeByRefOnStack;
1352 ainfo->offset = cinfo->stack_usage;
1353 cinfo->stack_usage += 8;
1355 ainfo->reg = cinfo->gr;
1361 /* Handle the case where there are no implicit arguments */
1362 if ((sig->call_convention == MONO_CALL_VARARG) && (pindex == sig->sentinelpos)) {
1363 /* Prevent implicit arguments and sig_cookie from
1364 being passed in registers */
1365 cinfo->gr = PARAM_REGS;
1366 cinfo->fr = FP_PARAM_REGS;
1367 /* Emit the signature cookie just before the implicit arguments */
1368 add_param (cinfo, &cinfo->sig_cookie, &mono_defaults.int_class->byval_arg);
1371 cinfo->stack_usage = ALIGN_TO (cinfo->stack_usage, MONO_ARCH_FRAME_ALIGNMENT);
1377 MonoMethodSignature *sig;
1380 MonoType **param_types;
1381 int n_fpargs, n_fpret;
1385 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
1389 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
1392 // FIXME: Add more cases
1393 switch (cinfo->ret.storage) {
1400 case ArgVtypeInIRegs:
1401 if (cinfo->ret.nregs > 2)
1410 for (i = 0; i < cinfo->nargs; ++i) {
1411 ArgInfo *ainfo = &cinfo->args [i];
1413 switch (ainfo->storage) {
1415 case ArgVtypeInIRegs:
1422 if (ainfo->offset >= DYN_CALL_STACK_ARGS * sizeof (mgreg_t))
1434 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
1436 ArchDynCallInfo *info;
1440 cinfo = get_call_info (NULL, sig);
1442 if (!dyn_call_supported (cinfo, sig)) {
1447 info = g_new0 (ArchDynCallInfo, 1);
1448 // FIXME: Preprocess the info to speed up start_dyn_call ()
1450 info->cinfo = cinfo;
1451 info->rtype = mini_get_underlying_type (sig->ret);
1452 info->param_types = g_new0 (MonoType*, sig->param_count);
1453 for (i = 0; i < sig->param_count; ++i)
1454 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
1456 switch (cinfo->ret.storage) {
1462 info->n_fpret = cinfo->ret.nregs;
1468 return (MonoDynCallInfo*)info;
1472 mono_arch_dyn_call_free (MonoDynCallInfo *info)
1474 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
1476 g_free (ainfo->cinfo);
1477 g_free (ainfo->param_types);
1482 bitcast_r4_to_r8 (float f)
1490 bitcast_r8_to_r4 (double f)
1498 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
1500 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
1501 DynCallArgs *p = (DynCallArgs*)buf;
1502 int aindex, arg_index, greg, i, pindex;
1503 MonoMethodSignature *sig = dinfo->sig;
1504 CallInfo *cinfo = dinfo->cinfo;
1505 int buffer_offset = 0;
1507 g_assert (buf_len >= sizeof (DynCallArgs));
1511 p->n_fpargs = dinfo->n_fpargs;
1512 p->n_fpret = dinfo->n_fpret;
1519 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
1521 if (cinfo->ret.storage == ArgVtypeByRef)
1522 p->regs [ARMREG_R8] = (mgreg_t)ret;
1524 for (aindex = pindex; aindex < sig->param_count; aindex++) {
1525 MonoType *t = dinfo->param_types [aindex];
1526 gpointer *arg = args [arg_index ++];
1527 ArgInfo *ainfo = &cinfo->args [aindex + sig->hasthis];
1530 if (ainfo->storage == ArgOnStack) {
1531 slot = PARAM_REGS + 1 + (ainfo->offset / sizeof (mgreg_t));
1537 p->regs [slot] = (mgreg_t)*arg;
1541 if (ios_abi && ainfo->storage == ArgOnStack) {
1542 guint8 *stack_arg = (guint8*)&(p->regs [PARAM_REGS + 1]) + ainfo->offset;
1543 gboolean handled = TRUE;
1545 /* Special case arguments smaller than 1 machine word */
1547 case MONO_TYPE_BOOLEAN:
1549 *(guint8*)stack_arg = *(guint8*)arg;
1552 *(gint8*)stack_arg = *(gint8*)arg;
1555 case MONO_TYPE_CHAR:
1556 *(guint16*)stack_arg = *(guint16*)arg;
1559 *(gint16*)stack_arg = *(gint16*)arg;
1562 *(gint32*)stack_arg = *(gint32*)arg;
1565 *(guint32*)stack_arg = *(guint32*)arg;
1576 case MONO_TYPE_STRING:
1577 case MONO_TYPE_CLASS:
1578 case MONO_TYPE_ARRAY:
1579 case MONO_TYPE_SZARRAY:
1580 case MONO_TYPE_OBJECT:
1586 p->regs [slot] = (mgreg_t)*arg;
1588 case MONO_TYPE_BOOLEAN:
1590 p->regs [slot] = *(guint8*)arg;
1593 p->regs [slot] = *(gint8*)arg;
1596 p->regs [slot] = *(gint16*)arg;
1599 case MONO_TYPE_CHAR:
1600 p->regs [slot] = *(guint16*)arg;
1603 p->regs [slot] = *(gint32*)arg;
1606 p->regs [slot] = *(guint32*)arg;
1609 p->fpregs [ainfo->reg] = bitcast_r4_to_r8 (*(float*)arg);
1613 p->fpregs [ainfo->reg] = *(double*)arg;
1616 case MONO_TYPE_GENERICINST:
1617 if (MONO_TYPE_IS_REFERENCE (t)) {
1618 p->regs [slot] = (mgreg_t)*arg;
1621 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
1622 MonoClass *klass = mono_class_from_mono_type (t);
1623 guint8 *nullable_buf;
1627 * Use p->buffer as a temporary buffer since the data needs to be available after this call
1628 * if the nullable param is passed by ref.
1630 size = mono_class_value_size (klass, NULL);
1631 nullable_buf = p->buffer + buffer_offset;
1632 buffer_offset += size;
1633 g_assert (buffer_offset <= 256);
1635 /* The argument pointed to by arg is either a boxed vtype or null */
1636 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
1638 arg = (gpointer*)nullable_buf;
1644 case MONO_TYPE_VALUETYPE:
1645 switch (ainfo->storage) {
1646 case ArgVtypeInIRegs:
1647 for (i = 0; i < ainfo->nregs; ++i)
1648 p->regs [slot ++] = ((mgreg_t*)arg) [i];
1651 if (ainfo->esize == 4) {
1652 for (i = 0; i < ainfo->nregs; ++i)
1653 p->fpregs [ainfo->reg + i] = bitcast_r4_to_r8 (((float*)arg) [ainfo->foffsets [i] / 4]);
1655 for (i = 0; i < ainfo->nregs; ++i)
1656 p->fpregs [ainfo->reg + i] = ((double*)arg) [ainfo->foffsets [i] / 8];
1658 p->n_fpargs += ainfo->nregs;
1661 p->regs [slot] = (mgreg_t)arg;
1664 g_assert_not_reached ();
1669 g_assert_not_reached ();
1675 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
1677 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
1678 CallInfo *cinfo = ainfo->cinfo;
1679 DynCallArgs *args = (DynCallArgs*)buf;
1680 MonoType *ptype = ainfo->rtype;
1681 guint8 *ret = args->ret;
1682 mgreg_t res = args->res;
1683 mgreg_t res2 = args->res2;
1686 if (cinfo->ret.storage == ArgVtypeByRef)
1689 switch (ptype->type) {
1690 case MONO_TYPE_VOID:
1691 *(gpointer*)ret = NULL;
1693 case MONO_TYPE_STRING:
1694 case MONO_TYPE_CLASS:
1695 case MONO_TYPE_ARRAY:
1696 case MONO_TYPE_SZARRAY:
1697 case MONO_TYPE_OBJECT:
1701 *(gpointer*)ret = (gpointer)res;
1707 case MONO_TYPE_BOOLEAN:
1708 *(guint8*)ret = res;
1711 *(gint16*)ret = res;
1714 case MONO_TYPE_CHAR:
1715 *(guint16*)ret = res;
1718 *(gint32*)ret = res;
1721 *(guint32*)ret = res;
1725 *(guint64*)ret = res;
1728 *(float*)ret = bitcast_r8_to_r4 (args->fpregs [0]);
1731 *(double*)ret = args->fpregs [0];
1733 case MONO_TYPE_GENERICINST:
1734 if (MONO_TYPE_IS_REFERENCE (ptype)) {
1735 *(gpointer*)ret = (gpointer)res;
1740 case MONO_TYPE_VALUETYPE:
1741 switch (ainfo->cinfo->ret.storage) {
1742 case ArgVtypeInIRegs:
1743 *(mgreg_t*)ret = res;
1744 if (ainfo->cinfo->ret.nregs > 1)
1745 ((mgreg_t*)ret) [1] = res2;
1748 /* Use the same area for returning fp values */
1749 if (cinfo->ret.esize == 4) {
1750 for (i = 0; i < cinfo->ret.nregs; ++i)
1751 ((float*)ret) [cinfo->ret.foffsets [i] / 4] = bitcast_r8_to_r4 (args->fpregs [i]);
1753 for (i = 0; i < cinfo->ret.nregs; ++i)
1754 ((double*)ret) [cinfo->ret.foffsets [i] / 8] = args->fpregs [i];
1758 g_assert_not_reached ();
1763 g_assert_not_reached ();
1768 void sys_icache_invalidate (void *start, size_t len);
1772 mono_arch_flush_icache (guint8 *code, gint size)
1774 #ifndef MONO_CROSS_COMPILE
1776 sys_icache_invalidate (code, size);
1778 __clear_cache (code, code + size);
1786 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
1793 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1798 for (i = 0; i < cfg->num_varinfo; i++) {
1799 MonoInst *ins = cfg->varinfo [i];
1800 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1803 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1806 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1807 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1810 if (mono_is_regsize_var (ins->inst_vtype)) {
1811 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1812 g_assert (i == vmv->idx);
1813 vars = g_list_prepend (vars, vmv);
1817 vars = mono_varlist_sort (cfg, vars, 0);
1823 mono_arch_get_global_int_regs (MonoCompile *cfg)
1828 /* r28 is reserved for cfg->arch.args_reg */
1829 /* r27 is reserved for the imt argument */
1830 for (i = ARMREG_R19; i <= ARMREG_R26; ++i)
1831 regs = g_list_prepend (regs, GUINT_TO_POINTER (i));
1837 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1839 MonoInst *ins = cfg->varinfo [vmv->idx];
1841 if (ins->opcode == OP_ARG)
1848 mono_arch_create_vars (MonoCompile *cfg)
1850 MonoMethodSignature *sig;
1853 sig = mono_method_signature (cfg->method);
1854 if (!cfg->arch.cinfo)
1855 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1856 cinfo = cfg->arch.cinfo;
1858 if (cinfo->ret.storage == ArgVtypeByRef) {
1859 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1860 cfg->vret_addr->flags |= MONO_INST_VOLATILE;
1863 if (cfg->gen_sdb_seq_points) {
1866 if (cfg->compile_aot) {
1867 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1868 ins->flags |= MONO_INST_VOLATILE;
1869 cfg->arch.seq_point_info_var = ins;
1872 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1873 ins->flags |= MONO_INST_VOLATILE;
1874 cfg->arch.ss_tramp_var = ins;
1876 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1877 ins->flags |= MONO_INST_VOLATILE;
1878 cfg->arch.bp_tramp_var = ins;
1881 if (cfg->method->save_lmf) {
1882 cfg->create_lmf_var = TRUE;
1885 cfg->lmf_ir_mono_lmf = TRUE;
1891 mono_arch_allocate_vars (MonoCompile *cfg)
1893 MonoMethodSignature *sig;
1897 int i, offset, size, align;
1898 guint32 locals_stack_size, locals_stack_align;
1902 * Allocate arguments and locals to either register (OP_REGVAR) or to a stack slot (OP_REGOFFSET).
1903 * Compute cfg->stack_offset and update cfg->used_int_regs.
1906 sig = mono_method_signature (cfg->method);
1908 if (!cfg->arch.cinfo)
1909 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1910 cinfo = cfg->arch.cinfo;
1913 * The ARM64 ABI always uses a frame pointer.
1914 * The instruction set prefers positive offsets, so fp points to the bottom of the
1915 * frame, and stack slots are at positive offsets.
1916 * If some arguments are received on the stack, their offsets relative to fp can
1917 * not be computed right now because the stack frame might grow due to spilling
1918 * done by the local register allocator. To solve this, we reserve a register
1919 * which points to them.
1920 * The stack frame looks like this:
1921 * args_reg -> <bottom of parent frame>
1923 * fp -> <saved fp+lr>
1924 * sp -> <localloc/params area>
1926 cfg->frame_reg = ARMREG_FP;
1927 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1933 if (cinfo->stack_usage) {
1934 g_assert (!(cfg->used_int_regs & (1 << ARMREG_R28)));
1935 cfg->arch.args_reg = ARMREG_R28;
1936 cfg->used_int_regs |= 1 << ARMREG_R28;
1939 if (cfg->method->save_lmf) {
1940 /* The LMF var is allocated normally */
1942 /* Callee saved regs */
1943 cfg->arch.saved_gregs_offset = offset;
1944 for (i = 0; i < 32; ++i)
1945 if ((MONO_ARCH_CALLEE_SAVED_REGS & (1 << i)) && (cfg->used_int_regs & (1 << i)))
1950 switch (cinfo->ret.storage) {
1956 cfg->ret->opcode = OP_REGVAR;
1957 cfg->ret->dreg = cinfo->ret.reg;
1959 case ArgVtypeInIRegs:
1961 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1962 cfg->ret->opcode = OP_REGOFFSET;
1963 cfg->ret->inst_basereg = cfg->frame_reg;
1964 cfg->ret->inst_offset = offset;
1965 if (cinfo->ret.storage == ArgHFA)
1972 /* This variable will be initalized in the prolog from R8 */
1973 cfg->vret_addr->opcode = OP_REGOFFSET;
1974 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1975 cfg->vret_addr->inst_offset = offset;
1977 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1978 printf ("vret_addr =");
1979 mono_print_ins (cfg->vret_addr);
1983 g_assert_not_reached ();
1988 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1989 ainfo = cinfo->args + i;
1991 ins = cfg->args [i];
1992 if (ins->opcode == OP_REGVAR)
1995 ins->opcode = OP_REGOFFSET;
1996 ins->inst_basereg = cfg->frame_reg;
1998 switch (ainfo->storage) {
2002 // FIXME: Use nregs/size
2003 /* These will be copied to the stack in the prolog */
2004 ins->inst_offset = offset;
2010 case ArgVtypeOnStack:
2011 /* These are in the parent frame */
2012 g_assert (cfg->arch.args_reg);
2013 ins->inst_basereg = cfg->arch.args_reg;
2014 ins->inst_offset = ainfo->offset;
2016 case ArgVtypeInIRegs:
2018 ins->opcode = OP_REGOFFSET;
2019 ins->inst_basereg = cfg->frame_reg;
2020 /* These arguments are saved to the stack in the prolog */
2021 ins->inst_offset = offset;
2022 if (cfg->verbose_level >= 2)
2023 printf ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2024 if (ainfo->storage == ArgHFA)
2030 case ArgVtypeByRefOnStack: {
2033 if (ainfo->gsharedvt) {
2034 ins->opcode = OP_REGOFFSET;
2035 ins->inst_basereg = cfg->arch.args_reg;
2036 ins->inst_offset = ainfo->offset;
2040 /* The vtype address is in the parent frame */
2041 g_assert (cfg->arch.args_reg);
2042 MONO_INST_NEW (cfg, vtaddr, 0);
2043 vtaddr->opcode = OP_REGOFFSET;
2044 vtaddr->inst_basereg = cfg->arch.args_reg;
2045 vtaddr->inst_offset = ainfo->offset;
2047 /* Need an indirection */
2048 ins->opcode = OP_VTARG_ADDR;
2049 ins->inst_left = vtaddr;
2052 case ArgVtypeByRef: {
2055 if (ainfo->gsharedvt) {
2056 ins->opcode = OP_REGOFFSET;
2057 ins->inst_basereg = cfg->frame_reg;
2058 ins->inst_offset = offset;
2063 /* The vtype address is in a register, will be copied to the stack in the prolog */
2064 MONO_INST_NEW (cfg, vtaddr, 0);
2065 vtaddr->opcode = OP_REGOFFSET;
2066 vtaddr->inst_basereg = cfg->frame_reg;
2067 vtaddr->inst_offset = offset;
2070 /* Need an indirection */
2071 ins->opcode = OP_VTARG_ADDR;
2072 ins->inst_left = vtaddr;
2076 g_assert_not_reached ();
2081 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
2082 // FIXME: Allocate these to registers
2083 ins = cfg->arch.seq_point_info_var;
2087 offset += align - 1;
2088 offset &= ~(align - 1);
2089 ins->opcode = OP_REGOFFSET;
2090 ins->inst_basereg = cfg->frame_reg;
2091 ins->inst_offset = offset;
2094 ins = cfg->arch.ss_tramp_var;
2098 offset += align - 1;
2099 offset &= ~(align - 1);
2100 ins->opcode = OP_REGOFFSET;
2101 ins->inst_basereg = cfg->frame_reg;
2102 ins->inst_offset = offset;
2105 ins = cfg->arch.bp_tramp_var;
2109 offset += align - 1;
2110 offset &= ~(align - 1);
2111 ins->opcode = OP_REGOFFSET;
2112 ins->inst_basereg = cfg->frame_reg;
2113 ins->inst_offset = offset;
2118 offsets = mono_allocate_stack_slots (cfg, FALSE, &locals_stack_size, &locals_stack_align);
2119 if (locals_stack_align)
2120 offset = ALIGN_TO (offset, locals_stack_align);
2122 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
2123 if (offsets [i] != -1) {
2124 ins = cfg->varinfo [i];
2125 ins->opcode = OP_REGOFFSET;
2126 ins->inst_basereg = cfg->frame_reg;
2127 ins->inst_offset = offset + offsets [i];
2128 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
2131 offset += locals_stack_size;
2133 offset = ALIGN_TO (offset, MONO_ARCH_FRAME_ALIGNMENT);
2135 cfg->stack_offset = offset;
2140 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2145 LLVMCallInfo *linfo;
2147 n = sig->param_count + sig->hasthis;
2149 cinfo = get_call_info (cfg->mempool, sig);
2151 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2153 switch (cinfo->ret.storage) {
2160 linfo->ret.storage = LLVMArgVtypeByRef;
2163 // FIXME: This doesn't work yet since the llvm backend represents these types as an i8
2164 // array which is returned in int regs
2167 linfo->ret.storage = LLVMArgFpStruct;
2168 linfo->ret.nslots = cinfo->ret.nregs;
2169 linfo->ret.esize = cinfo->ret.esize;
2171 case ArgVtypeInIRegs:
2172 /* LLVM models this by returning an int */
2173 linfo->ret.storage = LLVMArgVtypeAsScalar;
2174 linfo->ret.nslots = cinfo->ret.nregs;
2175 linfo->ret.esize = cinfo->ret.esize;
2178 g_assert_not_reached ();
2182 for (i = 0; i < n; ++i) {
2183 LLVMArgInfo *lainfo = &linfo->args [i];
2185 ainfo = cinfo->args + i;
2187 lainfo->storage = LLVMArgNone;
2189 switch (ainfo->storage) {
2196 lainfo->storage = LLVMArgNormal;
2199 case ArgVtypeByRefOnStack:
2200 lainfo->storage = LLVMArgVtypeByRef;
2205 lainfo->storage = LLVMArgAsFpArgs;
2206 lainfo->nslots = ainfo->nregs;
2207 lainfo->esize = ainfo->esize;
2208 for (j = 0; j < ainfo->nregs; ++j)
2209 lainfo->pair_storage [j] = LLVMArgInFPReg;
2212 case ArgVtypeInIRegs:
2213 lainfo->storage = LLVMArgAsIArgs;
2214 lainfo->nslots = ainfo->nregs;
2216 case ArgVtypeOnStack:
2220 lainfo->storage = LLVMArgAsFpArgs;
2221 lainfo->nslots = ainfo->nregs;
2222 lainfo->esize = ainfo->esize;
2223 lainfo->ndummy_fpargs = ainfo->nfregs_to_skip;
2224 for (j = 0; j < ainfo->nregs; ++j)
2225 lainfo->pair_storage [j] = LLVMArgInFPReg;
2227 lainfo->storage = LLVMArgAsIArgs;
2228 lainfo->nslots = ainfo->size / 8;
2232 g_assert_not_reached ();
2242 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2248 MONO_INST_NEW (cfg, ins, OP_MOVE);
2249 ins->dreg = mono_alloc_ireg_copy (cfg, arg->dreg);
2250 ins->sreg1 = arg->dreg;
2251 MONO_ADD_INS (cfg->cbb, ins);
2252 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2255 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2256 ins->dreg = mono_alloc_freg (cfg);
2257 ins->sreg1 = arg->dreg;
2258 MONO_ADD_INS (cfg->cbb, ins);
2259 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2262 if (COMPILE_LLVM (cfg))
2263 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2265 MONO_INST_NEW (cfg, ins, OP_RMOVE);
2267 MONO_INST_NEW (cfg, ins, OP_ARM_SETFREG_R4);
2268 ins->dreg = mono_alloc_freg (cfg);
2269 ins->sreg1 = arg->dreg;
2270 MONO_ADD_INS (cfg->cbb, ins);
2271 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2274 g_assert_not_reached ();
2280 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2282 MonoMethodSignature *tmp_sig;
2285 if (call->tail_call)
2288 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2291 * mono_ArgIterator_Setup assumes the signature cookie is
2292 * passed first and all the arguments which were before it are
2293 * passed on the stack after the signature. So compensate by
2294 * passing a different signature.
2296 tmp_sig = mono_metadata_signature_dup (call->signature);
2297 tmp_sig->param_count -= call->signature->sentinelpos;
2298 tmp_sig->sentinelpos = 0;
2299 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2301 sig_reg = mono_alloc_ireg (cfg);
2302 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2304 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2308 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2310 MonoMethodSignature *sig;
2311 MonoInst *arg, *vtarg;
2316 sig = call->signature;
2318 cinfo = get_call_info (cfg->mempool, sig);
2320 switch (cinfo->ret.storage) {
2321 case ArgVtypeInIRegs:
2324 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2325 * the location pointed to by it after call in emit_move_return_value ().
2327 if (!cfg->arch.vret_addr_loc) {
2328 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2329 /* Prevent it from being register allocated or optimized away */
2330 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2333 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2336 /* Pass the vtype return address in R8 */
2337 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2338 vtarg->sreg1 = call->vret_var->dreg;
2339 vtarg->dreg = mono_alloc_preg (cfg);
2340 MONO_ADD_INS (cfg->cbb, vtarg);
2342 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2348 for (i = 0; i < cinfo->nargs; ++i) {
2349 ainfo = cinfo->args + i;
2350 arg = call->args [i];
2352 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2353 /* Emit the signature cookie just before the implicit arguments */
2354 emit_sig_cookie (cfg, call, cinfo);
2357 switch (ainfo->storage) {
2361 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, arg);
2364 switch (ainfo->slot_size) {
2366 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2369 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2372 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI2_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2375 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI1_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2378 g_assert_not_reached ();
2383 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2386 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, arg->dreg);
2388 case ArgVtypeInIRegs:
2390 case ArgVtypeByRefOnStack:
2391 case ArgVtypeOnStack:
2397 size = mono_class_value_size (arg->klass, &align);
2399 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2400 ins->sreg1 = arg->dreg;
2401 ins->klass = arg->klass;
2402 ins->backend.size = size;
2403 ins->inst_p0 = call;
2404 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2405 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2406 MONO_ADD_INS (cfg->cbb, ins);
2410 g_assert_not_reached ();
2415 /* Handle the case where there are no implicit arguments */
2416 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (cinfo->nargs == sig->sentinelpos))
2417 emit_sig_cookie (cfg, call, cinfo);
2419 call->call_info = cinfo;
2420 call->stack_usage = cinfo->stack_usage;
2424 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2426 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2427 ArgInfo *ainfo = ins->inst_p1;
2431 if (ins->backend.size == 0 && !ainfo->gsharedvt)
2434 switch (ainfo->storage) {
2435 case ArgVtypeInIRegs:
2436 for (i = 0; i < ainfo->nregs; ++i) {
2437 // FIXME: Smaller sizes
2438 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
2439 load->dreg = mono_alloc_ireg (cfg);
2440 load->inst_basereg = src->dreg;
2441 load->inst_offset = i * sizeof(mgreg_t);
2442 MONO_ADD_INS (cfg->cbb, load);
2443 add_outarg_reg (cfg, call, ArgInIReg, ainfo->reg + i, load);
2447 for (i = 0; i < ainfo->nregs; ++i) {
2448 if (ainfo->esize == 4)
2449 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2451 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2452 load->dreg = mono_alloc_freg (cfg);
2453 load->inst_basereg = src->dreg;
2454 load->inst_offset = ainfo->foffsets [i];
2455 MONO_ADD_INS (cfg->cbb, load);
2456 add_outarg_reg (cfg, call, ainfo->esize == 4 ? ArgInFRegR4 : ArgInFReg, ainfo->reg + i, load);
2460 case ArgVtypeByRefOnStack: {
2461 MonoInst *vtaddr, *load, *arg;
2463 /* Pass the vtype address in a reg/on the stack */
2464 if (ainfo->gsharedvt) {
2467 /* Make a copy of the argument */
2468 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2470 MONO_INST_NEW (cfg, load, OP_LDADDR);
2471 load->inst_p0 = vtaddr;
2472 vtaddr->flags |= MONO_INST_INDIRECT;
2473 load->type = STACK_MP;
2474 load->klass = vtaddr->klass;
2475 load->dreg = mono_alloc_ireg (cfg);
2476 MONO_ADD_INS (cfg->cbb, load);
2477 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, ainfo->size, 8);
2480 if (ainfo->storage == ArgVtypeByRef) {
2481 MONO_INST_NEW (cfg, arg, OP_MOVE);
2482 arg->dreg = mono_alloc_preg (cfg);
2483 arg->sreg1 = load->dreg;
2484 MONO_ADD_INS (cfg->cbb, arg);
2485 add_outarg_reg (cfg, call, ArgInIReg, ainfo->reg, arg);
2487 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, load->dreg);
2491 case ArgVtypeOnStack:
2492 for (i = 0; i < ainfo->size / 8; ++i) {
2493 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
2494 load->dreg = mono_alloc_ireg (cfg);
2495 load->inst_basereg = src->dreg;
2496 load->inst_offset = i * 8;
2497 MONO_ADD_INS (cfg->cbb, load);
2498 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset + (i * 8), load->dreg);
2502 g_assert_not_reached ();
2508 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2510 MonoMethodSignature *sig;
2513 sig = mono_method_signature (cfg->method);
2514 if (!cfg->arch.cinfo)
2515 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2516 cinfo = cfg->arch.cinfo;
2518 switch (cinfo->ret.storage) {
2522 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2525 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2528 if (COMPILE_LLVM (cfg))
2529 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2531 MONO_EMIT_NEW_UNALU (cfg, OP_RMOVE, cfg->ret->dreg, val->dreg);
2533 MONO_EMIT_NEW_UNALU (cfg, OP_ARM_SETFREG_R4, cfg->ret->dreg, val->dreg);
2536 g_assert_not_reached ();
2542 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
2547 if (cfg->compile_aot && !cfg->full_aot)
2548 /* OP_TAILCALL doesn't work with AOT */
2551 c1 = get_call_info (NULL, caller_sig);
2552 c2 = get_call_info (NULL, callee_sig);
2554 // FIXME: Relax these restrictions
2555 if (c1->stack_usage != 0)
2557 if (c1->stack_usage != c2->stack_usage)
2559 if ((c1->ret.storage != ArgNone && c1->ret.storage != ArgInIReg) || c1->ret.storage != c2->ret.storage)
2569 mono_arch_is_inst_imm (gint64 imm)
2571 return (imm >= -((gint64)1<<31) && imm <= (((gint64)1<<31)-1));
2575 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
2582 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
2589 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2595 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2600 #define ADD_NEW_INS(cfg,dest,op) do { \
2601 MONO_INST_NEW ((cfg), (dest), (op)); \
2602 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2606 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2608 MonoInst *ins, *temp, *last_ins = NULL;
2610 MONO_BB_FOR_EACH_INS (bb, ins) {
2611 switch (ins->opcode) {
2616 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
2617 /* ARM sets the C flag to 1 if there was _no_ overflow */
2618 ins->next->opcode = OP_COND_EXC_NC;
2622 case OP_IDIV_UN_IMM:
2623 case OP_IREM_UN_IMM:
2625 mono_decompose_op_imm (cfg, bb, ins);
2627 case OP_LOCALLOC_IMM:
2628 if (ins->inst_imm > 32) {
2629 ADD_NEW_INS (cfg, temp, OP_ICONST);
2630 temp->inst_c0 = ins->inst_imm;
2631 temp->dreg = mono_alloc_ireg (cfg);
2632 ins->sreg1 = temp->dreg;
2633 ins->opcode = mono_op_imm_to_op (ins->opcode);
2636 case OP_ICOMPARE_IMM:
2637 if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_IBEQ) {
2638 ins->next->opcode = OP_ARM64_CBZW;
2639 ins->next->sreg1 = ins->sreg1;
2641 } else if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_IBNE_UN) {
2642 ins->next->opcode = OP_ARM64_CBNZW;
2643 ins->next->sreg1 = ins->sreg1;
2647 case OP_LCOMPARE_IMM:
2648 case OP_COMPARE_IMM:
2649 if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_LBEQ) {
2650 ins->next->opcode = OP_ARM64_CBZX;
2651 ins->next->sreg1 = ins->sreg1;
2653 } else if (ins->inst_imm == 0 && ins->next && ins->next->opcode == OP_LBNE_UN) {
2654 ins->next->opcode = OP_ARM64_CBNZX;
2655 ins->next->sreg1 = ins->sreg1;
2660 gboolean swap = FALSE;
2664 /* Optimized away */
2670 * FP compares with unordered operands set the flags
2671 * to NZCV=0011, which matches some non-unordered compares
2672 * as well, like LE, so have to swap the operands.
2674 switch (ins->next->opcode) {
2676 ins->next->opcode = OP_FBGT;
2680 ins->next->opcode = OP_FBGE;
2688 ins->sreg1 = ins->sreg2;
2699 bb->last_ins = last_ins;
2700 bb->max_vreg = cfg->next_vreg;
2704 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
2709 opcode_to_armcond (int opcode)
2720 case OP_COND_EXC_IEQ:
2721 case OP_COND_EXC_EQ:
2738 case OP_COND_EXC_IGT:
2739 case OP_COND_EXC_GT:
2754 case OP_COND_EXC_ILT:
2755 case OP_COND_EXC_LT:
2763 case OP_COND_EXC_INE_UN:
2764 case OP_COND_EXC_NE_UN:
2770 case OP_COND_EXC_IGE_UN:
2771 case OP_COND_EXC_GE_UN:
2781 case OP_COND_EXC_IGT_UN:
2782 case OP_COND_EXC_GT_UN:
2788 case OP_COND_EXC_ILE_UN:
2789 case OP_COND_EXC_LE_UN:
2797 case OP_COND_EXC_ILT_UN:
2798 case OP_COND_EXC_LT_UN:
2801 * FCMP sets the NZCV condition bits as follows:
2806 * ARMCOND_LT is N!=V, so it matches unordered too, so
2807 * fclt and fclt_un need to be special cased.
2817 case OP_COND_EXC_IC:
2819 case OP_COND_EXC_OV:
2820 case OP_COND_EXC_IOV:
2822 case OP_COND_EXC_NC:
2823 case OP_COND_EXC_INC:
2825 case OP_COND_EXC_NO:
2826 case OP_COND_EXC_INO:
2829 printf ("%s\n", mono_inst_name (opcode));
2830 g_assert_not_reached ();
2835 /* This clobbers LR */
2836 static inline __attribute__((warn_unused_result)) guint8*
2837 emit_cond_exc (MonoCompile *cfg, guint8 *code, int opcode, const char *exc_name)
2841 cond = opcode_to_armcond (opcode);
2843 arm_adrx (code, ARMREG_IP1, code);
2844 mono_add_patch_info_rel (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, exc_name, MONO_R_ARM64_BCC);
2845 arm_bcc (code, cond, 0);
2850 emit_move_return_value (MonoCompile *cfg, guint8 * code, MonoInst *ins)
2855 call = (MonoCallInst*)ins;
2856 cinfo = call->call_info;
2858 switch (cinfo->ret.storage) {
2862 /* LLVM compiled code might only set the bottom bits */
2863 if (call->signature && mini_get_underlying_type (call->signature->ret)->type == MONO_TYPE_I4)
2864 arm_sxtwx (code, call->inst.dreg, cinfo->ret.reg);
2865 else if (call->inst.dreg != cinfo->ret.reg)
2866 arm_movx (code, call->inst.dreg, cinfo->ret.reg);
2869 if (call->inst.dreg != cinfo->ret.reg)
2870 arm_fmovd (code, call->inst.dreg, cinfo->ret.reg);
2874 arm_fmovs (code, call->inst.dreg, cinfo->ret.reg);
2876 arm_fcvt_sd (code, call->inst.dreg, cinfo->ret.reg);
2878 case ArgVtypeInIRegs: {
2879 MonoInst *loc = cfg->arch.vret_addr_loc;
2882 /* Load the destination address */
2883 g_assert (loc && loc->opcode == OP_REGOFFSET);
2884 code = emit_ldrx (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
2885 for (i = 0; i < cinfo->ret.nregs; ++i)
2886 arm_strx (code, cinfo->ret.reg + i, ARMREG_LR, i * 8);
2890 MonoInst *loc = cfg->arch.vret_addr_loc;
2893 /* Load the destination address */
2894 g_assert (loc && loc->opcode == OP_REGOFFSET);
2895 code = emit_ldrx (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
2896 for (i = 0; i < cinfo->ret.nregs; ++i) {
2897 if (cinfo->ret.esize == 4)
2898 arm_strfpw (code, cinfo->ret.reg + i, ARMREG_LR, cinfo->ret.foffsets [i]);
2900 arm_strfpx (code, cinfo->ret.reg + i, ARMREG_LR, cinfo->ret.foffsets [i]);
2907 g_assert_not_reached ();
2914 * emit_branch_island:
2916 * Emit a branch island for the conditional branches from cfg->native_code + start_offset to code.
2919 emit_branch_island (MonoCompile *cfg, guint8 *code, int start_offset)
2922 int offset, island_size;
2924 /* Iterate over the patch infos added so far by this bb */
2926 for (ji = cfg->patch_info; ji; ji = ji->next) {
2927 if (ji->ip.i < start_offset)
2928 /* The patch infos are in reverse order, so this means the end */
2930 if (ji->relocation == MONO_R_ARM64_BCC || ji->relocation == MONO_R_ARM64_CBZ)
2935 offset = code - cfg->native_code;
2936 if (offset > (cfg->code_size - island_size - 16)) {
2937 cfg->code_size *= 2;
2938 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2939 code = cfg->native_code + offset;
2942 /* Branch over the island */
2943 arm_b (code, code + 4 + island_size);
2945 for (ji = cfg->patch_info; ji; ji = ji->next) {
2946 if (ji->ip.i < start_offset)
2948 if (ji->relocation == MONO_R_ARM64_BCC || ji->relocation == MONO_R_ARM64_CBZ) {
2949 /* Rewrite the cond branch so it branches to an uncoditional branch in the branch island */
2950 arm_patch_rel (cfg->native_code + ji->ip.i, code, ji->relocation);
2951 /* Rewrite the patch so it points to the unconditional branch */
2952 ji->ip.i = code - cfg->native_code;
2953 ji->relocation = MONO_R_ARM64_B;
2962 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2967 guint8 *code = cfg->native_code + cfg->code_len;
2968 int start_offset, max_len, dreg, sreg1, sreg2;
2971 if (cfg->verbose_level > 2)
2972 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2974 start_offset = code - cfg->native_code;
2976 MONO_BB_FOR_EACH_INS (bb, ins) {
2977 offset = code - cfg->native_code;
2979 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2981 if (offset > (cfg->code_size - max_len - 16)) {
2982 cfg->code_size *= 2;
2983 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2984 code = cfg->native_code + offset;
2987 if (G_UNLIKELY (cfg->arch.cond_branch_islands && offset - start_offset > 4 * 0x1ffff)) {
2988 /* Emit a branch island for large basic blocks */
2989 code = emit_branch_island (cfg, code, start_offset);
2990 offset = code - cfg->native_code;
2991 start_offset = offset;
2994 mono_debug_record_line_number (cfg, ins, offset);
2999 imm = ins->inst_imm;
3001 switch (ins->opcode) {
3003 code = emit_imm (code, dreg, ins->inst_c0);
3006 code = emit_imm64 (code, dreg, ins->inst_c0);
3010 arm_movx (code, dreg, sreg1);
3013 case OP_RELAXED_NOP:
3016 mono_add_patch_info_rel (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0, MONO_R_ARM64_IMM);
3017 code = emit_imm64_template (code, dreg);
3021 * gdb does not like encountering the hw breakpoint ins in the debugged code.
3022 * So instead of emitting a trap, we emit a call a C function and place a
3025 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_break");
3030 arm_addx_imm (code, ARMREG_IP0, sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
3031 // FIXME: andx_imm doesn't work yet
3032 code = emit_imm (code, ARMREG_IP1, -MONO_ARCH_FRAME_ALIGNMENT);
3033 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
3034 //arm_andx_imm (code, ARMREG_IP0, sreg1, - MONO_ARCH_FRAME_ALIGNMENT);
3035 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
3036 arm_subx (code, ARMREG_IP1, ARMREG_IP1, ARMREG_IP0);
3037 arm_movspx (code, ARMREG_SP, ARMREG_IP1);
3040 /* ip1 = pointer, ip0 = end */
3041 arm_addx (code, ARMREG_IP0, ARMREG_IP1, ARMREG_IP0);
3043 arm_cmpx (code, ARMREG_IP1, ARMREG_IP0);
3045 arm_bcc (code, ARMCOND_EQ, 0);
3046 arm_stpx (code, ARMREG_RZR, ARMREG_RZR, ARMREG_IP1, 0);
3047 arm_addx_imm (code, ARMREG_IP1, ARMREG_IP1, 16);
3048 arm_b (code, buf [0]);
3049 arm_patch_rel (buf [1], code, MONO_R_ARM64_BCC);
3051 arm_movspx (code, dreg, ARMREG_SP);
3052 if (cfg->param_area)
3053 code = emit_subx_sp_imm (code, cfg->param_area);
3056 case OP_LOCALLOC_IMM: {
3059 imm = ALIGN_TO (ins->inst_imm, MONO_ARCH_FRAME_ALIGNMENT);
3060 g_assert (arm_is_arith_imm (imm));
3061 arm_subx_imm (code, ARMREG_SP, ARMREG_SP, imm);
3064 g_assert (MONO_ARCH_FRAME_ALIGNMENT == 16);
3066 while (offset < imm) {
3067 arm_stpx (code, ARMREG_RZR, ARMREG_RZR, ARMREG_SP, offset);
3070 arm_movspx (code, dreg, ARMREG_SP);
3071 if (cfg->param_area)
3072 code = emit_subx_sp_imm (code, cfg->param_area);
3076 code = emit_aotconst (cfg, code, dreg, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3078 case OP_OBJC_GET_SELECTOR:
3079 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
3080 /* See arch_emit_objc_selector_ref () in aot-compiler.c */
3081 arm_ldrx_lit (code, ins->dreg, 0);
3085 case OP_SEQ_POINT: {
3086 MonoInst *info_var = cfg->arch.seq_point_info_var;
3089 * For AOT, we use one got slot per method, which will point to a
3090 * SeqPointInfo structure, containing all the information required
3091 * by the code below.
3093 if (cfg->compile_aot) {
3094 g_assert (info_var);
3095 g_assert (info_var->opcode == OP_REGOFFSET);
3098 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3099 MonoInst *var = cfg->arch.ss_tramp_var;
3102 g_assert (var->opcode == OP_REGOFFSET);
3103 /* Load ss_tramp_var */
3104 /* This is equal to &ss_trampoline */
3105 arm_ldrx (code, ARMREG_IP1, var->inst_basereg, var->inst_offset);
3106 /* Load the trampoline address */
3107 arm_ldrx (code, ARMREG_IP1, ARMREG_IP1, 0);
3108 /* Call it if it is non-null */
3109 arm_cbzx (code, ARMREG_IP1, code + 8);
3110 arm_blrx (code, ARMREG_IP1);
3113 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3115 if (cfg->compile_aot) {
3116 guint32 offset = code - cfg->native_code;
3119 arm_ldrx (code, ARMREG_IP1, info_var->inst_basereg, info_var->inst_offset);
3120 /* Add the offset */
3121 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
3122 /* Load the info->bp_addrs [offset], which is either 0 or the address of the bp trampoline */
3123 code = emit_ldrx (code, ARMREG_IP1, ARMREG_IP1, val);
3124 /* Skip the load if its 0 */
3125 arm_cbzx (code, ARMREG_IP1, code + 8);
3126 /* Call the breakpoint trampoline */
3127 arm_blrx (code, ARMREG_IP1);
3129 MonoInst *var = cfg->arch.bp_tramp_var;
3132 g_assert (var->opcode == OP_REGOFFSET);
3133 /* Load the address of the bp trampoline into IP0 */
3134 arm_ldrx (code, ARMREG_IP0, var->inst_basereg, var->inst_offset);
3136 * A placeholder for a possible breakpoint inserted by
3137 * mono_arch_set_breakpoint ().
3146 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb, MONO_R_ARM64_B);
3150 arm_brx (code, sreg1);
3182 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3183 cond = opcode_to_armcond (ins->opcode);
3184 arm_bcc (code, cond, 0);
3188 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3189 /* For fp compares, ARMCOND_LT is lt or unordered */
3190 arm_bcc (code, ARMCOND_LT, 0);
3193 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3194 arm_bcc (code, ARMCOND_EQ, 0);
3195 offset = code - cfg->native_code;
3196 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_BCC);
3197 /* For fp compares, ARMCOND_LT is lt or unordered */
3198 arm_bcc (code, ARMCOND_LT, 0);
3201 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3202 arm_cbzw (code, sreg1, 0);
3205 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3206 arm_cbzx (code, sreg1, 0);
3208 case OP_ARM64_CBNZW:
3209 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3210 arm_cbnzw (code, sreg1, 0);
3212 case OP_ARM64_CBNZX:
3213 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_true_bb, MONO_R_ARM64_CBZ);
3214 arm_cbnzx (code, sreg1, 0);
3218 arm_addw (code, dreg, sreg1, sreg2);
3221 arm_addx (code, dreg, sreg1, sreg2);
3224 arm_subw (code, dreg, sreg1, sreg2);
3227 arm_subx (code, dreg, sreg1, sreg2);
3230 arm_andw (code, dreg, sreg1, sreg2);
3233 arm_andx (code, dreg, sreg1, sreg2);
3236 arm_orrw (code, dreg, sreg1, sreg2);
3239 arm_orrx (code, dreg, sreg1, sreg2);
3242 arm_eorw (code, dreg, sreg1, sreg2);
3245 arm_eorx (code, dreg, sreg1, sreg2);
3248 arm_negw (code, dreg, sreg1);
3251 arm_negx (code, dreg, sreg1);
3254 arm_mvnw (code, dreg, sreg1);
3257 arm_mvnx (code, dreg, sreg1);
3260 arm_addsw (code, dreg, sreg1, sreg2);
3264 arm_addsx (code, dreg, sreg1, sreg2);
3267 arm_subsw (code, dreg, sreg1, sreg2);
3271 arm_subsx (code, dreg, sreg1, sreg2);
3274 arm_cmpw (code, sreg1, sreg2);
3278 arm_cmpx (code, sreg1, sreg2);
3281 code = emit_addw_imm (code, dreg, sreg1, imm);
3285 code = emit_addx_imm (code, dreg, sreg1, imm);
3288 code = emit_subw_imm (code, dreg, sreg1, imm);
3291 code = emit_subx_imm (code, dreg, sreg1, imm);
3294 code = emit_andw_imm (code, dreg, sreg1, imm);
3298 code = emit_andx_imm (code, dreg, sreg1, imm);
3301 code = emit_orrw_imm (code, dreg, sreg1, imm);
3304 code = emit_orrx_imm (code, dreg, sreg1, imm);
3307 code = emit_eorw_imm (code, dreg, sreg1, imm);
3310 code = emit_eorx_imm (code, dreg, sreg1, imm);
3312 case OP_ICOMPARE_IMM:
3313 code = emit_cmpw_imm (code, sreg1, imm);
3315 case OP_LCOMPARE_IMM:
3316 case OP_COMPARE_IMM:
3318 arm_cmpx (code, sreg1, ARMREG_RZR);
3320 // FIXME: 32 vs 64 bit issues for 0xffffffff
3321 code = emit_imm64 (code, ARMREG_LR, imm);
3322 arm_cmpx (code, sreg1, ARMREG_LR);
3326 arm_lslvw (code, dreg, sreg1, sreg2);
3329 arm_lslvx (code, dreg, sreg1, sreg2);
3332 arm_asrvw (code, dreg, sreg1, sreg2);
3335 arm_asrvx (code, dreg, sreg1, sreg2);
3338 arm_lsrvw (code, dreg, sreg1, sreg2);
3341 arm_lsrvx (code, dreg, sreg1, sreg2);
3345 arm_movx (code, dreg, sreg1);
3347 arm_lslw (code, dreg, sreg1, imm);
3351 arm_movx (code, dreg, sreg1);
3353 arm_lslx (code, dreg, sreg1, imm);
3357 arm_movx (code, dreg, sreg1);
3359 arm_asrw (code, dreg, sreg1, imm);
3364 arm_movx (code, dreg, sreg1);
3366 arm_asrx (code, dreg, sreg1, imm);
3368 case OP_ISHR_UN_IMM:
3370 arm_movx (code, dreg, sreg1);
3372 arm_lsrw (code, dreg, sreg1, imm);
3375 case OP_LSHR_UN_IMM:
3377 arm_movx (code, dreg, sreg1);
3379 arm_lsrx (code, dreg, sreg1, imm);
3384 arm_sxtwx (code, dreg, sreg1);
3387 /* Clean out the upper word */
3388 arm_movw (code, dreg, sreg1);
3391 arm_lslx (code, dreg, sreg1, imm);
3394 /* MULTIPLY/DIVISION */
3397 // FIXME: Optimize this
3398 /* Check for zero */
3399 arm_cmpx_imm (code, sreg2, 0);
3400 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3401 /* Check for INT_MIN/-1 */
3402 code = emit_imm (code, ARMREG_IP0, 0x80000000);
3403 arm_cmpx (code, sreg1, ARMREG_IP0);
3404 arm_cset (code, ARMCOND_EQ, ARMREG_IP1);
3405 code = emit_imm (code, ARMREG_IP0, 0xffffffff);
3406 arm_cmpx (code, sreg2, ARMREG_IP0);
3407 arm_cset (code, ARMCOND_EQ, ARMREG_IP0);
3408 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
3409 arm_cmpx_imm (code, ARMREG_IP0, 1);
3410 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "OverflowException");
3411 if (ins->opcode == OP_IREM) {
3412 arm_sdivw (code, ARMREG_LR, sreg1, sreg2);
3413 arm_msubw (code, dreg, ARMREG_LR, sreg2, sreg1);
3415 arm_sdivw (code, dreg, sreg1, sreg2);
3419 arm_cmpx_imm (code, sreg2, 0);
3420 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3421 arm_udivw (code, dreg, sreg1, sreg2);
3424 arm_cmpx_imm (code, sreg2, 0);
3425 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3426 arm_udivw (code, ARMREG_LR, sreg1, sreg2);
3427 arm_msubw (code, dreg, ARMREG_LR, sreg2, sreg1);
3431 // FIXME: Optimize this
3432 /* Check for zero */
3433 arm_cmpx_imm (code, sreg2, 0);
3434 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3435 /* Check for INT64_MIN/-1 */
3436 code = emit_imm64 (code, ARMREG_IP0, 0x8000000000000000);
3437 arm_cmpx (code, sreg1, ARMREG_IP0);
3438 arm_cset (code, ARMCOND_EQ, ARMREG_IP1);
3439 code = emit_imm64 (code, ARMREG_IP0, 0xffffffffffffffff);
3440 arm_cmpx (code, sreg2, ARMREG_IP0);
3441 arm_cset (code, ARMCOND_EQ, ARMREG_IP0);
3442 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
3443 arm_cmpx_imm (code, ARMREG_IP0, 1);
3444 /* 64 bit uses ArithmeticException */
3445 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "ArithmeticException");
3446 if (ins->opcode == OP_LREM) {
3447 arm_sdivx (code, ARMREG_LR, sreg1, sreg2);
3448 arm_msubx (code, dreg, ARMREG_LR, sreg2, sreg1);
3450 arm_sdivx (code, dreg, sreg1, sreg2);
3454 arm_cmpx_imm (code, sreg2, 0);
3455 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3456 arm_udivx (code, dreg, sreg1, sreg2);
3459 arm_cmpx_imm (code, sreg2, 0);
3460 code = emit_cond_exc (cfg, code, OP_COND_EXC_IEQ, "DivideByZeroException");
3461 arm_udivx (code, ARMREG_LR, sreg1, sreg2);
3462 arm_msubx (code, dreg, ARMREG_LR, sreg2, sreg1);
3465 arm_mulw (code, dreg, sreg1, sreg2);
3468 arm_mulx (code, dreg, sreg1, sreg2);
3471 code = emit_imm (code, ARMREG_LR, imm);
3472 arm_mulw (code, dreg, sreg1, ARMREG_LR);
3476 code = emit_imm (code, ARMREG_LR, imm);
3477 arm_mulx (code, dreg, sreg1, ARMREG_LR);
3481 case OP_ICONV_TO_I1:
3482 case OP_LCONV_TO_I1:
3483 arm_sxtbx (code, dreg, sreg1);
3485 case OP_ICONV_TO_I2:
3486 case OP_LCONV_TO_I2:
3487 arm_sxthx (code, dreg, sreg1);
3489 case OP_ICONV_TO_U1:
3490 case OP_LCONV_TO_U1:
3491 arm_uxtbw (code, dreg, sreg1);
3493 case OP_ICONV_TO_U2:
3494 case OP_LCONV_TO_U2:
3495 arm_uxthw (code, dreg, sreg1);
3521 cond = opcode_to_armcond (ins->opcode);
3522 arm_cset (code, cond, dreg);
3535 cond = opcode_to_armcond (ins->opcode);
3536 arm_fcmpd (code, sreg1, sreg2);
3537 arm_cset (code, cond, dreg);
3542 case OP_LOADI1_MEMBASE:
3543 code = emit_ldrsbx (code, dreg, ins->inst_basereg, ins->inst_offset);
3545 case OP_LOADU1_MEMBASE:
3546 code = emit_ldrb (code, dreg, ins->inst_basereg, ins->inst_offset);
3548 case OP_LOADI2_MEMBASE:
3549 code = emit_ldrshx (code, dreg, ins->inst_basereg, ins->inst_offset);
3551 case OP_LOADU2_MEMBASE:
3552 code = emit_ldrh (code, dreg, ins->inst_basereg, ins->inst_offset);
3554 case OP_LOADI4_MEMBASE:
3555 code = emit_ldrswx (code, dreg, ins->inst_basereg, ins->inst_offset);
3557 case OP_LOADU4_MEMBASE:
3558 code = emit_ldrw (code, dreg, ins->inst_basereg, ins->inst_offset);
3560 case OP_LOAD_MEMBASE:
3561 case OP_LOADI8_MEMBASE:
3562 code = emit_ldrx (code, dreg, ins->inst_basereg, ins->inst_offset);
3564 case OP_STOREI1_MEMBASE_IMM:
3565 case OP_STOREI2_MEMBASE_IMM:
3566 case OP_STOREI4_MEMBASE_IMM:
3567 case OP_STORE_MEMBASE_IMM:
3568 case OP_STOREI8_MEMBASE_IMM: {
3572 code = emit_imm (code, ARMREG_LR, imm);
3575 immreg = ARMREG_RZR;
3578 switch (ins->opcode) {
3579 case OP_STOREI1_MEMBASE_IMM:
3580 code = emit_strb (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3582 case OP_STOREI2_MEMBASE_IMM:
3583 code = emit_strh (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3585 case OP_STOREI4_MEMBASE_IMM:
3586 code = emit_strw (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3588 case OP_STORE_MEMBASE_IMM:
3589 case OP_STOREI8_MEMBASE_IMM:
3590 code = emit_strx (code, immreg, ins->inst_destbasereg, ins->inst_offset);
3593 g_assert_not_reached ();
3598 case OP_STOREI1_MEMBASE_REG:
3599 code = emit_strb (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3601 case OP_STOREI2_MEMBASE_REG:
3602 code = emit_strh (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3604 case OP_STOREI4_MEMBASE_REG:
3605 code = emit_strw (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3607 case OP_STORE_MEMBASE_REG:
3608 case OP_STOREI8_MEMBASE_REG:
3609 code = emit_strx (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3613 code = emit_tls_get (code, dreg, ins->inst_offset);
3615 case OP_TLS_GET_REG:
3616 code = emit_tls_get_reg (code, dreg, sreg1);
3619 code = emit_tls_set (code, sreg1, ins->inst_offset);
3621 case OP_TLS_SET_REG:
3622 code = emit_tls_set_reg (code, sreg1, sreg2);
3626 case OP_MEMORY_BARRIER:
3629 case OP_ATOMIC_ADD_I4: {
3633 arm_ldaxrw (code, ARMREG_IP0, sreg1);
3634 arm_addx (code, ARMREG_IP0, ARMREG_IP0, sreg2);
3635 arm_stlxrw (code, ARMREG_IP1, ARMREG_IP0, sreg1);
3636 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3638 arm_movx (code, dreg, ARMREG_IP0);
3641 case OP_ATOMIC_ADD_I8: {
3645 arm_ldaxrx (code, ARMREG_IP0, sreg1);
3646 arm_addx (code, ARMREG_IP0, ARMREG_IP0, sreg2);
3647 arm_stlxrx (code, ARMREG_IP1, ARMREG_IP0, sreg1);
3648 arm_cbnzx (code, ARMREG_IP1, buf [0]);
3650 arm_movx (code, dreg, ARMREG_IP0);
3653 case OP_ATOMIC_EXCHANGE_I4: {
3657 arm_ldaxrw (code, ARMREG_IP0, sreg1);
3658 arm_stlxrw (code, ARMREG_IP1, sreg2, sreg1);
3659 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3661 arm_movx (code, dreg, ARMREG_IP0);
3664 case OP_ATOMIC_EXCHANGE_I8: {
3668 arm_ldaxrx (code, ARMREG_IP0, sreg1);
3669 arm_stlxrx (code, ARMREG_IP1, sreg2, sreg1);
3670 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3672 arm_movx (code, dreg, ARMREG_IP0);
3675 case OP_ATOMIC_CAS_I4: {
3678 /* sreg2 is the value, sreg3 is the comparand */
3680 arm_ldaxrw (code, ARMREG_IP0, sreg1);
3681 arm_cmpw (code, ARMREG_IP0, ins->sreg3);
3683 arm_bcc (code, ARMCOND_NE, 0);
3684 arm_stlxrw (code, ARMREG_IP1, sreg2, sreg1);
3685 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3686 arm_patch_rel (buf [1], code, MONO_R_ARM64_BCC);
3688 arm_movx (code, dreg, ARMREG_IP0);
3691 case OP_ATOMIC_CAS_I8: {
3695 arm_ldaxrx (code, ARMREG_IP0, sreg1);
3696 arm_cmpx (code, ARMREG_IP0, ins->sreg3);
3698 arm_bcc (code, ARMCOND_NE, 0);
3699 arm_stlxrx (code, ARMREG_IP1, sreg2, sreg1);
3700 arm_cbnzw (code, ARMREG_IP1, buf [0]);
3701 arm_patch_rel (buf [1], code, MONO_R_ARM64_BCC);
3703 arm_movx (code, dreg, ARMREG_IP0);
3706 case OP_ATOMIC_LOAD_I1: {
3707 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3708 arm_ldarb (code, ins->dreg, ARMREG_LR);
3709 arm_sxtbx (code, ins->dreg, ins->dreg);
3712 case OP_ATOMIC_LOAD_U1: {
3713 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3714 arm_ldarb (code, ins->dreg, ARMREG_LR);
3715 arm_uxtbx (code, ins->dreg, ins->dreg);
3718 case OP_ATOMIC_LOAD_I2: {
3719 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3720 arm_ldarh (code, ins->dreg, ARMREG_LR);
3721 arm_sxthx (code, ins->dreg, ins->dreg);
3724 case OP_ATOMIC_LOAD_U2: {
3725 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3726 arm_ldarh (code, ins->dreg, ARMREG_LR);
3727 arm_uxthx (code, ins->dreg, ins->dreg);
3730 case OP_ATOMIC_LOAD_I4: {
3731 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3732 arm_ldarw (code, ins->dreg, ARMREG_LR);
3733 arm_sxtwx (code, ins->dreg, ins->dreg);
3736 case OP_ATOMIC_LOAD_U4: {
3737 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3738 arm_ldarw (code, ins->dreg, ARMREG_LR);
3739 arm_movw (code, ins->dreg, ins->dreg); /* Clear upper half of the register. */
3742 case OP_ATOMIC_LOAD_I8:
3743 case OP_ATOMIC_LOAD_U8: {
3744 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3745 arm_ldarx (code, ins->dreg, ARMREG_LR);
3748 case OP_ATOMIC_LOAD_R4: {
3749 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3751 arm_ldarw (code, ARMREG_LR, ARMREG_LR);
3752 arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
3754 arm_ldarw (code, ARMREG_LR, ARMREG_LR);
3755 arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
3756 arm_fcvt_sd (code, ins->dreg, FP_TEMP_REG);
3760 case OP_ATOMIC_LOAD_R8: {
3761 code = emit_addx_imm (code, ARMREG_LR, ins->inst_basereg, ins->inst_offset);
3762 arm_ldarx (code, ARMREG_LR, ARMREG_LR);
3763 arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
3766 case OP_ATOMIC_STORE_I1:
3767 case OP_ATOMIC_STORE_U1: {
3768 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3769 arm_stlrb (code, ARMREG_LR, ins->sreg1);
3772 case OP_ATOMIC_STORE_I2:
3773 case OP_ATOMIC_STORE_U2: {
3774 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3775 arm_stlrh (code, ARMREG_LR, ins->sreg1);
3778 case OP_ATOMIC_STORE_I4:
3779 case OP_ATOMIC_STORE_U4: {
3780 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3781 arm_stlrw (code, ARMREG_LR, ins->sreg1);
3784 case OP_ATOMIC_STORE_I8:
3785 case OP_ATOMIC_STORE_U8: {
3786 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3787 arm_stlrx (code, ARMREG_LR, ins->sreg1);
3790 case OP_ATOMIC_STORE_R4: {
3791 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3793 arm_fmov_double_to_rx (code, ARMREG_IP0, ins->sreg1);
3794 arm_stlrw (code, ARMREG_LR, ARMREG_IP0);
3796 arm_fcvt_ds (code, FP_TEMP_REG, ins->sreg1);
3797 arm_fmov_double_to_rx (code, ARMREG_IP0, FP_TEMP_REG);
3798 arm_stlrw (code, ARMREG_LR, ARMREG_IP0);
3802 case OP_ATOMIC_STORE_R8: {
3803 code = emit_addx_imm (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
3804 arm_fmov_double_to_rx (code, ARMREG_IP0, ins->sreg1);
3805 arm_stlrx (code, ARMREG_LR, ARMREG_IP0);
3811 guint64 imm = *(guint64*)ins->inst_p0;
3814 arm_fmov_rx_to_double (code, dreg, ARMREG_RZR);
3816 code = emit_imm64 (code, ARMREG_LR, imm);
3817 arm_fmov_rx_to_double (code, ins->dreg, ARMREG_LR);
3822 guint64 imm = *(guint32*)ins->inst_p0;
3824 code = emit_imm64 (code, ARMREG_LR, imm);
3826 arm_fmov_rx_to_double (code, dreg, ARMREG_LR);
3828 arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
3829 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3833 case OP_LOADR8_MEMBASE:
3834 code = emit_ldrfpx (code, dreg, ins->inst_basereg, ins->inst_offset);
3836 case OP_LOADR4_MEMBASE:
3838 code = emit_ldrfpw (code, dreg, ins->inst_basereg, ins->inst_offset);
3840 code = emit_ldrfpw (code, FP_TEMP_REG, ins->inst_basereg, ins->inst_offset);
3841 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3844 case OP_STORER8_MEMBASE_REG:
3845 code = emit_strfpx (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3847 case OP_STORER4_MEMBASE_REG:
3849 code = emit_strfpw (code, sreg1, ins->inst_destbasereg, ins->inst_offset);
3851 arm_fcvt_ds (code, FP_TEMP_REG, sreg1);
3852 code = emit_strfpw (code, FP_TEMP_REG, ins->inst_destbasereg, ins->inst_offset);
3857 arm_fmovd (code, dreg, sreg1);
3861 arm_fmovs (code, dreg, sreg1);
3863 case OP_MOVE_F_TO_I4:
3865 arm_fmov_double_to_rx (code, ins->dreg, ins->sreg1);
3867 arm_fcvt_ds (code, ins->dreg, ins->sreg1);
3868 arm_fmov_double_to_rx (code, ins->dreg, ins->dreg);
3871 case OP_MOVE_I4_TO_F:
3873 arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
3875 arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
3876 arm_fcvt_sd (code, ins->dreg, ins->dreg);
3879 case OP_MOVE_F_TO_I8:
3880 arm_fmov_double_to_rx (code, ins->dreg, ins->sreg1);
3882 case OP_MOVE_I8_TO_F:
3883 arm_fmov_rx_to_double (code, ins->dreg, ins->sreg1);
3886 arm_fcmpd (code, sreg1, sreg2);
3889 arm_fcmps (code, sreg1, sreg2);
3891 case OP_FCONV_TO_I1:
3892 arm_fcvtzs_dx (code, dreg, sreg1);
3893 arm_sxtbx (code, dreg, dreg);
3895 case OP_FCONV_TO_U1:
3896 arm_fcvtzu_dx (code, dreg, sreg1);
3897 arm_uxtbw (code, dreg, dreg);
3899 case OP_FCONV_TO_I2:
3900 arm_fcvtzs_dx (code, dreg, sreg1);
3901 arm_sxthx (code, dreg, dreg);
3903 case OP_FCONV_TO_U2:
3904 arm_fcvtzu_dx (code, dreg, sreg1);
3905 arm_uxthw (code, dreg, dreg);
3907 case OP_FCONV_TO_I4:
3908 arm_fcvtzs_dx (code, dreg, sreg1);
3909 arm_sxtwx (code, dreg, dreg);
3911 case OP_FCONV_TO_U4:
3912 arm_fcvtzu_dx (code, dreg, sreg1);
3914 case OP_FCONV_TO_I8:
3915 arm_fcvtzs_dx (code, dreg, sreg1);
3917 case OP_FCONV_TO_U8:
3918 arm_fcvtzu_dx (code, dreg, sreg1);
3920 case OP_FCONV_TO_R4:
3922 arm_fcvt_ds (code, dreg, sreg1);
3924 arm_fcvt_ds (code, FP_TEMP_REG, sreg1);
3925 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3928 case OP_ICONV_TO_R4:
3930 arm_scvtf_rw_to_s (code, dreg, sreg1);
3932 arm_scvtf_rw_to_s (code, FP_TEMP_REG, sreg1);
3933 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3936 case OP_LCONV_TO_R4:
3938 arm_scvtf_rx_to_s (code, dreg, sreg1);
3940 arm_scvtf_rx_to_s (code, FP_TEMP_REG, sreg1);
3941 arm_fcvt_sd (code, dreg, FP_TEMP_REG);
3944 case OP_ICONV_TO_R8:
3945 arm_scvtf_rw_to_d (code, dreg, sreg1);
3947 case OP_LCONV_TO_R8:
3948 arm_scvtf_rx_to_d (code, dreg, sreg1);
3950 case OP_ICONV_TO_R_UN:
3951 arm_ucvtf_rw_to_d (code, dreg, sreg1);
3953 case OP_LCONV_TO_R_UN:
3954 arm_ucvtf_rx_to_d (code, dreg, sreg1);
3957 arm_fadd_d (code, dreg, sreg1, sreg2);
3960 arm_fsub_d (code, dreg, sreg1, sreg2);
3963 arm_fmul_d (code, dreg, sreg1, sreg2);
3966 arm_fdiv_d (code, dreg, sreg1, sreg2);
3970 g_assert_not_reached ();
3973 arm_fneg_d (code, dreg, sreg1);
3975 case OP_ARM_SETFREG_R4:
3976 arm_fcvt_ds (code, dreg, sreg1);
3979 /* Check for infinity */
3980 code = emit_imm64 (code, ARMREG_LR, 0x7fefffffffffffffLL);
3981 arm_fmov_rx_to_double (code, FP_TEMP_REG, ARMREG_LR);
3982 arm_fabs_d (code, FP_TEMP_REG2, sreg1);
3983 arm_fcmpd (code, FP_TEMP_REG2, FP_TEMP_REG);
3984 code = emit_cond_exc (cfg, code, OP_COND_EXC_GT, "ArithmeticException");
3985 /* Check for nans */
3986 arm_fcmpd (code, FP_TEMP_REG2, FP_TEMP_REG2);
3987 code = emit_cond_exc (cfg, code, OP_COND_EXC_OV, "ArithmeticException");
3988 arm_fmovd (code, dreg, sreg1);
3993 arm_fadd_s (code, dreg, sreg1, sreg2);
3996 arm_fsub_s (code, dreg, sreg1, sreg2);
3999 arm_fmul_s (code, dreg, sreg1, sreg2);
4002 arm_fdiv_s (code, dreg, sreg1, sreg2);
4005 arm_fneg_s (code, dreg, sreg1);
4007 case OP_RCONV_TO_I1:
4008 arm_fcvtzs_sx (code, dreg, sreg1);
4009 arm_sxtbx (code, dreg, dreg);
4011 case OP_RCONV_TO_U1:
4012 arm_fcvtzu_sx (code, dreg, sreg1);
4013 arm_uxtbw (code, dreg, dreg);
4015 case OP_RCONV_TO_I2:
4016 arm_fcvtzs_sx (code, dreg, sreg1);
4017 arm_sxthx (code, dreg, dreg);
4019 case OP_RCONV_TO_U2:
4020 arm_fcvtzu_sx (code, dreg, sreg1);
4021 arm_uxthw (code, dreg, dreg);
4023 case OP_RCONV_TO_I4:
4024 arm_fcvtzs_sx (code, dreg, sreg1);
4025 arm_sxtwx (code, dreg, dreg);
4027 case OP_RCONV_TO_U4:
4028 arm_fcvtzu_sx (code, dreg, sreg1);
4030 case OP_RCONV_TO_I8:
4031 arm_fcvtzs_sx (code, dreg, sreg1);
4033 case OP_RCONV_TO_U8:
4034 arm_fcvtzu_sx (code, dreg, sreg1);
4036 case OP_RCONV_TO_R8:
4037 arm_fcvt_sd (code, dreg, sreg1);
4039 case OP_RCONV_TO_R4:
4041 arm_fmovs (code, dreg, sreg1);
4053 cond = opcode_to_armcond (ins->opcode);
4054 arm_fcmps (code, sreg1, sreg2);
4055 arm_cset (code, cond, dreg);
4066 call = (MonoCallInst*)ins;
4067 if (ins->flags & MONO_INST_HAS_METHOD)
4068 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
4070 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
4071 code = emit_move_return_value (cfg, code, ins);
4073 case OP_VOIDCALL_REG:
4079 arm_blrx (code, sreg1);
4080 code = emit_move_return_value (cfg, code, ins);
4082 case OP_VOIDCALL_MEMBASE:
4083 case OP_CALL_MEMBASE:
4084 case OP_LCALL_MEMBASE:
4085 case OP_FCALL_MEMBASE:
4086 case OP_RCALL_MEMBASE:
4087 case OP_VCALL2_MEMBASE:
4088 code = emit_ldrx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4089 arm_blrx (code, ARMREG_IP0);
4090 code = emit_move_return_value (cfg, code, ins);
4093 MonoCallInst *call = (MonoCallInst*)ins;
4095 g_assert (!cfg->method->save_lmf);
4097 // FIXME: Copy stack arguments
4099 /* Restore registers */
4100 code = emit_load_regset (code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->arch.saved_gregs_offset);
4103 code = mono_arm_emit_destroy_frame (code, cfg->stack_offset, ((1 << ARMREG_IP0) | (1 << ARMREG_IP1)));
4105 if (cfg->compile_aot) {
4106 /* This is not a PLT patch */
4107 code = emit_aotconst (cfg, code, ARMREG_IP0, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4108 arm_brx (code, ARMREG_IP0);
4110 mono_add_patch_info_rel (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method, MONO_R_ARM64_B);
4113 ins->flags |= MONO_INST_GC_CALLSITE;
4114 ins->backend.pc_offset = code - cfg->native_code;
4118 g_assert (cfg->arch.cinfo);
4119 code = emit_addx_imm (code, ARMREG_IP0, cfg->arch.args_reg, ((CallInfo*)cfg->arch.cinfo)->sig_cookie.offset);
4120 arm_strx (code, ARMREG_IP0, sreg1, 0);
4123 MonoInst *var = cfg->dyn_call_var;
4124 guint8 *labels [16];
4128 * sreg1 points to a DynCallArgs structure initialized by mono_arch_start_dyn_call ().
4129 * sreg2 is the function to call.
4132 g_assert (var->opcode == OP_REGOFFSET);
4134 arm_movx (code, ARMREG_LR, sreg1);
4135 arm_movx (code, ARMREG_IP1, sreg2);
4137 /* Save args buffer */
4138 code = emit_strx (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4140 /* Set fp argument regs */
4141 code = emit_ldrw (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, n_fpargs));
4142 arm_cmpw (code, ARMREG_R0, ARMREG_RZR);
4144 arm_bcc (code, ARMCOND_EQ, 0);
4145 for (i = 0; i < 8; ++i)
4146 code = emit_ldrfpx (code, ARMREG_D0 + i, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * 8));
4147 arm_patch_rel (labels [0], code, MONO_R_ARM64_BCC);
4149 /* Set stack args */
4150 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4151 code = emit_ldrx (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + 1 + i) * sizeof (mgreg_t)));
4152 code = emit_strx (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
4155 /* Set argument registers + r8 */
4156 code = mono_arm_emit_load_regarray (code, 0x1ff, ARMREG_LR, 0);
4159 arm_blrx (code, ARMREG_IP1);
4162 code = emit_ldrx (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
4163 arm_strx (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, res));
4164 arm_strx (code, ARMREG_R1, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, res2));
4165 /* Save fp result */
4166 code = emit_ldrw (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, n_fpret));
4167 arm_cmpw (code, ARMREG_R0, ARMREG_RZR);
4169 arm_bcc (code, ARMCOND_EQ, 0);
4170 for (i = 0; i < 8; ++i)
4171 code = emit_strfpx (code, ARMREG_D0 + i, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * 8));
4172 arm_patch_rel (labels [1], code, MONO_R_ARM64_BCC);
4176 case OP_GENERIC_CLASS_INIT: {
4177 static int byte_offset = -1;
4178 static guint8 bitmask;
4181 if (byte_offset < 0)
4182 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4184 /* Load vtable->initialized */
4185 arm_ldrsbx (code, ARMREG_IP0, sreg1, byte_offset);
4186 // FIXME: No andx_imm yet */
4187 code = mono_arm_emit_imm64 (code, ARMREG_IP1, bitmask);
4188 arm_andx (code, ARMREG_IP0, ARMREG_IP0, ARMREG_IP1);
4190 arm_cbnzx (code, ARMREG_IP0, 0);
4193 g_assert (sreg1 == ARMREG_R0);
4194 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4195 (gpointer)"mono_generic_class_init");
4197 mono_arm_patch (jump, code, MONO_R_ARM64_CBZ);
4202 arm_ldrx (code, ARMREG_LR, sreg1, 0);
4205 case OP_NOT_REACHED:
4208 case OP_IL_SEQ_POINT:
4209 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4214 case OP_COND_EXC_IC:
4215 case OP_COND_EXC_OV:
4216 case OP_COND_EXC_IOV:
4217 case OP_COND_EXC_NC:
4218 case OP_COND_EXC_INC:
4219 case OP_COND_EXC_NO:
4220 case OP_COND_EXC_INO:
4221 case OP_COND_EXC_EQ:
4222 case OP_COND_EXC_IEQ:
4223 case OP_COND_EXC_NE_UN:
4224 case OP_COND_EXC_INE_UN:
4225 case OP_COND_EXC_ILT:
4226 case OP_COND_EXC_LT:
4227 case OP_COND_EXC_ILT_UN:
4228 case OP_COND_EXC_LT_UN:
4229 case OP_COND_EXC_IGT:
4230 case OP_COND_EXC_GT:
4231 case OP_COND_EXC_IGT_UN:
4232 case OP_COND_EXC_GT_UN:
4233 case OP_COND_EXC_IGE:
4234 case OP_COND_EXC_GE:
4235 case OP_COND_EXC_IGE_UN:
4236 case OP_COND_EXC_GE_UN:
4237 case OP_COND_EXC_ILE:
4238 case OP_COND_EXC_LE:
4239 case OP_COND_EXC_ILE_UN:
4240 case OP_COND_EXC_LE_UN:
4241 code = emit_cond_exc (cfg, code, ins->opcode, ins->inst_p1);
4244 if (sreg1 != ARMREG_R0)
4245 arm_movx (code, ARMREG_R0, sreg1);
4246 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4247 (gpointer)"mono_arch_throw_exception");
4250 if (sreg1 != ARMREG_R0)
4251 arm_movx (code, ARMREG_R0, sreg1);
4252 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4253 (gpointer)"mono_arch_rethrow_exception");
4255 case OP_CALL_HANDLER:
4256 mono_add_patch_info_rel (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb, MONO_R_ARM64_BL);
4258 cfg->thunk_area += THUNK_SIZE;
4260 case OP_START_HANDLER: {
4261 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4263 /* Save caller address */
4264 code = emit_strx (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4267 * Reserve a param area, see test_0_finally_param_area ().
4268 * This is needed because the param area is not set up when
4269 * we are called from EH code.
4271 if (cfg->param_area)
4272 code = emit_subx_sp_imm (code, cfg->param_area);
4276 case OP_ENDFILTER: {
4277 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4279 if (cfg->param_area)
4280 code = emit_addx_sp_imm (code, cfg->param_area);
4282 if (ins->opcode == OP_ENDFILTER && sreg1 != ARMREG_R0)
4283 arm_movx (code, ARMREG_R0, sreg1);
4285 /* Return to either after the branch in OP_CALL_HANDLER, or to the EH code */
4286 code = emit_ldrx (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
4287 arm_brx (code, ARMREG_LR);
4291 if (ins->dreg != ARMREG_R0)
4292 arm_movx (code, ins->dreg, ARMREG_R0);
4294 case OP_GC_SAFE_POINT: {
4295 #if defined (USE_COOP_GC)
4298 arm_ldrx (code, ARMREG_IP1, ins->sreg1, 0);
4299 /* Call it if it is non-null */
4301 arm_cbzx (code, ARMREG_IP1, 0);
4302 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
4303 mono_arm_patch (buf [0], code, MONO_R_ARM64_CBZ);
4309 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4310 g_assert_not_reached ();
4313 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
4314 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4315 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4316 g_assert_not_reached ();
4321 * If the compiled code size is larger than the bcc displacement (19 bits signed),
4322 * insert branch islands between/inside basic blocks.
4324 if (cfg->arch.cond_branch_islands)
4325 code = emit_branch_island (cfg, code, start_offset);
4327 cfg->code_len = code - cfg->native_code;
4331 emit_move_args (MonoCompile *cfg, guint8 *code)
4338 cinfo = cfg->arch.cinfo;
4340 for (i = 0; i < cinfo->nargs; ++i) {
4341 ainfo = cinfo->args + i;
4342 ins = cfg->args [i];
4344 if (ins->opcode == OP_REGVAR) {
4345 switch (ainfo->storage) {
4347 arm_movx (code, ins->dreg, ainfo->reg);
4350 switch (ainfo->slot_size) {
4353 code = emit_ldrsbx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4355 code = emit_ldrb (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4359 code = emit_ldrshx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4361 code = emit_ldrh (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4365 code = emit_ldrswx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4367 code = emit_ldrw (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4370 code = emit_ldrx (code, ins->dreg, cfg->arch.args_reg, ainfo->offset);
4375 g_assert_not_reached ();
4379 if (ainfo->storage != ArgVtypeByRef && ainfo->storage != ArgVtypeByRefOnStack)
4380 g_assert (ins->opcode == OP_REGOFFSET);
4382 switch (ainfo->storage) {
4384 /* Stack slots for arguments have size 8 */
4385 code = emit_strx (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4388 code = emit_strfpx (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4391 code = emit_strfpw (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4396 case ArgVtypeByRefOnStack:
4397 case ArgVtypeOnStack:
4399 case ArgVtypeByRef: {
4400 MonoInst *addr_arg = ins->inst_left;
4402 if (ainfo->gsharedvt) {
4403 g_assert (ins->opcode == OP_GSHAREDVT_ARG_REGOFFSET);
4404 arm_strx (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
4406 g_assert (ins->opcode == OP_VTARG_ADDR);
4407 g_assert (addr_arg->opcode == OP_REGOFFSET);
4408 arm_strx (code, ainfo->reg, addr_arg->inst_basereg, addr_arg->inst_offset);
4412 case ArgVtypeInIRegs:
4413 for (part = 0; part < ainfo->nregs; part ++) {
4414 code = emit_strx (code, ainfo->reg + part, ins->inst_basereg, ins->inst_offset + (part * 8));
4418 for (part = 0; part < ainfo->nregs; part ++) {
4419 if (ainfo->esize == 4)
4420 code = emit_strfpw (code, ainfo->reg + part, ins->inst_basereg, ins->inst_offset + ainfo->foffsets [part]);
4422 code = emit_strfpx (code, ainfo->reg + part, ins->inst_basereg, ins->inst_offset + ainfo->foffsets [part]);
4426 g_assert_not_reached ();
4436 * emit_store_regarray:
4438 * Emit code to store the registers in REGS into the appropriate elements of
4439 * the register array at BASEREG+OFFSET.
4441 static __attribute__((warn_unused_result)) guint8*
4442 emit_store_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4446 for (i = 0; i < 32; ++i) {
4447 if (regs & (1 << i)) {
4448 if (i + 1 < 32 && (regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4449 arm_stpx (code, i, i + 1, basereg, offset + (i * 8));
4451 } else if (i == ARMREG_SP) {
4452 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
4453 arm_strx (code, ARMREG_IP1, basereg, offset + (i * 8));
4455 arm_strx (code, i, basereg, offset + (i * 8));
4463 * emit_load_regarray:
4465 * Emit code to load the registers in REGS from the appropriate elements of
4466 * the register array at BASEREG+OFFSET.
4468 static __attribute__((warn_unused_result)) guint8*
4469 emit_load_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4473 for (i = 0; i < 32; ++i) {
4474 if (regs & (1 << i)) {
4475 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4476 if (offset + (i * 8) < 500)
4477 arm_ldpx (code, i, i + 1, basereg, offset + (i * 8));
4479 code = emit_ldrx (code, i, basereg, offset + (i * 8));
4480 code = emit_ldrx (code, i + 1, basereg, offset + ((i + 1) * 8));
4483 } else if (i == ARMREG_SP) {
4484 g_assert_not_reached ();
4486 code = emit_ldrx (code, i, basereg, offset + (i * 8));
4494 * emit_store_regset:
4496 * Emit code to store the registers in REGS into consecutive memory locations starting
4497 * at BASEREG+OFFSET.
4499 static __attribute__((warn_unused_result)) guint8*
4500 emit_store_regset (guint8 *code, guint64 regs, int basereg, int offset)
4505 for (i = 0; i < 32; ++i) {
4506 if (regs & (1 << i)) {
4507 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4508 arm_stpx (code, i, i + 1, basereg, offset + (pos * 8));
4511 } else if (i == ARMREG_SP) {
4512 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
4513 arm_strx (code, ARMREG_IP1, basereg, offset + (pos * 8));
4515 arm_strx (code, i, basereg, offset + (pos * 8));
4526 * Emit code to load the registers in REGS from consecutive memory locations starting
4527 * at BASEREG+OFFSET.
4529 static __attribute__((warn_unused_result)) guint8*
4530 emit_load_regset (guint8 *code, guint64 regs, int basereg, int offset)
4535 for (i = 0; i < 32; ++i) {
4536 if (regs & (1 << i)) {
4537 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4538 arm_ldpx (code, i, i + 1, basereg, offset + (pos * 8));
4541 } else if (i == ARMREG_SP) {
4542 g_assert_not_reached ();
4544 arm_ldrx (code, i, basereg, offset + (pos * 8));
4552 __attribute__((warn_unused_result)) guint8*
4553 mono_arm_emit_load_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4555 return emit_load_regarray (code, regs, basereg, offset);
4558 __attribute__((warn_unused_result)) guint8*
4559 mono_arm_emit_store_regarray (guint8 *code, guint64 regs, int basereg, int offset)
4561 return emit_store_regarray (code, regs, basereg, offset);
4564 __attribute__((warn_unused_result)) guint8*
4565 mono_arm_emit_store_regset (guint8 *code, guint64 regs, int basereg, int offset)
4567 return emit_store_regset (code, regs, basereg, offset);
4570 /* Same as emit_store_regset, but emit unwind info too */
4571 /* CFA_OFFSET is the offset between the CFA and basereg */
4572 static __attribute__((warn_unused_result)) guint8*
4573 emit_store_regset_cfa (MonoCompile *cfg, guint8 *code, guint64 regs, int basereg, int offset, int cfa_offset, guint64 no_cfa_regset)
4575 int i, j, pos, nregs;
4576 guint32 cfa_regset = regs & ~no_cfa_regset;
4579 for (i = 0; i < 32; ++i) {
4581 if (regs & (1 << i)) {
4582 if ((regs & (1 << (i + 1))) && (i + 1 != ARMREG_SP)) {
4584 arm_stpx (code, i, i + 1, basereg, offset + (pos * 8));
4586 code = emit_strx (code, i, basereg, offset + (pos * 8));
4587 code = emit_strx (code, i + 1, basereg, offset + (pos * 8) + 8);
4590 } else if (i == ARMREG_SP) {
4591 arm_movspx (code, ARMREG_IP1, ARMREG_SP);
4592 code = emit_strx (code, ARMREG_IP1, basereg, offset + (pos * 8));
4594 code = emit_strx (code, i, basereg, offset + (pos * 8));
4597 for (j = 0; j < nregs; ++j) {
4598 if (cfa_regset & (1 << (i + j)))
4599 mono_emit_unwind_op_offset (cfg, code, i + j, (- cfa_offset) + offset + ((pos + j) * 8));
4612 * Emit code to initialize an LMF structure at LMF_OFFSET.
4616 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
4619 * The LMF should contain all the state required to be able to reconstruct the machine state
4620 * at the current point of execution. Since the LMF is only read during EH, only callee
4621 * saved etc. registers need to be saved.
4622 * FIXME: Save callee saved fp regs, JITted code doesn't use them, but native code does, and they
4623 * need to be restored during EH.
4627 arm_adrx (code, ARMREG_LR, code);
4628 code = emit_strx (code, ARMREG_LR, ARMREG_FP, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, pc));
4629 /* gregs + fp + sp */
4630 /* Don't emit unwind info for sp/fp, they are already handled in the prolog */
4631 code = emit_store_regset_cfa (cfg, code, MONO_ARCH_LMF_REGS, ARMREG_FP, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, gregs), cfa_offset, (1 << ARMREG_FP) | (1 << ARMREG_SP));
4637 mono_arch_emit_prolog (MonoCompile *cfg)
4639 MonoMethod *method = cfg->method;
4640 MonoMethodSignature *sig;
4643 int cfa_offset, max_offset;
4645 sig = mono_method_signature (method);
4646 cfg->code_size = 256 + sig->param_count * 64;
4647 code = cfg->native_code = g_malloc (cfg->code_size);
4649 /* This can be unaligned */
4650 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4656 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
4659 if (arm_is_ldpx_imm (-cfg->stack_offset)) {
4660 arm_stpx_pre (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, -cfg->stack_offset);
4662 /* sp -= cfg->stack_offset */
4663 /* This clobbers ip0/ip1 */
4664 code = emit_subx_sp_imm (code, cfg->stack_offset);
4665 arm_stpx (code, ARMREG_FP, ARMREG_LR, ARMREG_SP, 0);
4667 cfa_offset += cfg->stack_offset;
4668 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4669 mono_emit_unwind_op_offset (cfg, code, ARMREG_FP, (- cfa_offset) + 0);
4670 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, (- cfa_offset) + 8);
4671 arm_movspx (code, ARMREG_FP, ARMREG_SP);
4672 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_FP);
4673 if (cfg->param_area) {
4674 /* The param area is below the frame pointer */
4675 code = emit_subx_sp_imm (code, cfg->param_area);
4678 if (cfg->method->save_lmf) {
4679 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
4682 code = emit_store_regset_cfa (cfg, code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->arch.saved_gregs_offset, cfa_offset, 0);
4685 /* Setup args reg */
4686 if (cfg->arch.args_reg) {
4687 /* The register was already saved above */
4688 code = emit_addx_imm (code, cfg->arch.args_reg, ARMREG_FP, cfg->stack_offset);
4691 /* Save return area addr received in R8 */
4692 if (cfg->vret_addr) {
4693 MonoInst *ins = cfg->vret_addr;
4695 g_assert (ins->opcode == OP_REGOFFSET);
4696 code = emit_strx (code, ARMREG_R8, ins->inst_basereg, ins->inst_offset);
4699 /* Save mrgctx received in MONO_ARCH_RGCTX_REG */
4700 if (cfg->rgctx_var) {
4701 MonoInst *ins = cfg->rgctx_var;
4703 g_assert (ins->opcode == OP_REGOFFSET);
4705 code = emit_strx (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
4709 * Move arguments to their registers/stack locations.
4711 code = emit_move_args (cfg, code);
4713 /* Initialize seq_point_info_var */
4714 if (cfg->arch.seq_point_info_var) {
4715 MonoInst *ins = cfg->arch.seq_point_info_var;
4717 /* Initialize the variable from a GOT slot */
4718 code = emit_aotconst (cfg, code, ARMREG_IP0, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
4719 g_assert (ins->opcode == OP_REGOFFSET);
4720 code = emit_strx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4722 /* Initialize ss_tramp_var */
4723 ins = cfg->arch.ss_tramp_var;
4724 g_assert (ins->opcode == OP_REGOFFSET);
4726 code = emit_ldrx (code, ARMREG_IP1, ARMREG_IP0, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
4727 code = emit_strx (code, ARMREG_IP1, ins->inst_basereg, ins->inst_offset);
4731 if (cfg->arch.ss_tramp_var) {
4732 /* Initialize ss_tramp_var */
4733 ins = cfg->arch.ss_tramp_var;
4734 g_assert (ins->opcode == OP_REGOFFSET);
4736 code = emit_imm64 (code, ARMREG_IP0, (guint64)&ss_trampoline);
4737 code = emit_strx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4740 if (cfg->arch.bp_tramp_var) {
4741 /* Initialize bp_tramp_var */
4742 ins = cfg->arch.bp_tramp_var;
4743 g_assert (ins->opcode == OP_REGOFFSET);
4745 code = emit_imm64 (code, ARMREG_IP0, (guint64)bp_trampoline);
4746 code = emit_strx (code, ARMREG_IP0, ins->inst_basereg, ins->inst_offset);
4751 if (cfg->opt & MONO_OPT_BRANCH) {
4752 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4754 bb->max_offset = max_offset;
4756 MONO_BB_FOR_EACH_INS (bb, ins) {
4757 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4761 if (max_offset > 0x3ffff * 4)
4762 cfg->arch.cond_branch_islands = TRUE;
4768 realloc_code (MonoCompile *cfg, int size)
4770 while (cfg->code_len + size > (cfg->code_size - 16)) {
4771 cfg->code_size *= 2;
4772 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4773 cfg->stat_code_reallocs++;
4775 return cfg->native_code + cfg->code_len;
4779 mono_arch_emit_epilog (MonoCompile *cfg)
4782 int max_epilog_size;
4786 max_epilog_size = 16 + 20*4;
4787 code = realloc_code (cfg, max_epilog_size);
4789 if (cfg->method->save_lmf) {
4790 code = mono_arm_emit_load_regarray (code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, gregs) - (MONO_ARCH_FIRST_LMF_REG * 8));
4793 code = emit_load_regset (code, MONO_ARCH_CALLEE_SAVED_REGS & cfg->used_int_regs, ARMREG_FP, cfg->arch.saved_gregs_offset);
4796 /* Load returned vtypes into registers if needed */
4797 cinfo = cfg->arch.cinfo;
4798 switch (cinfo->ret.storage) {
4799 case ArgVtypeInIRegs: {
4800 MonoInst *ins = cfg->ret;
4802 for (i = 0; i < cinfo->ret.nregs; ++i)
4803 code = emit_ldrx (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * 8));
4807 MonoInst *ins = cfg->ret;
4809 for (i = 0; i < cinfo->ret.nregs; ++i) {
4810 if (cinfo->ret.esize == 4)
4811 code = emit_ldrfpw (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + cinfo->ret.foffsets [i]);
4813 code = emit_ldrfpx (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + cinfo->ret.foffsets [i]);
4822 code = mono_arm_emit_destroy_frame (code, cfg->stack_offset, ((1 << ARMREG_IP0) | (1 << ARMREG_IP1)));
4824 arm_retx (code, ARMREG_LR);
4826 g_assert (code - (cfg->native_code + cfg->code_len) < max_epilog_size);
4828 cfg->code_len = code - cfg->native_code;
4832 mono_arch_emit_exceptions (MonoCompile *cfg)
4835 MonoClass *exc_class;
4837 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
4838 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
4839 int i, id, size = 0;
4841 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
4842 exc_throw_pos [i] = NULL;
4843 exc_throw_found [i] = 0;
4846 for (ji = cfg->patch_info; ji; ji = ji->next) {
4847 if (ji->type == MONO_PATCH_INFO_EXC) {
4848 i = mini_exception_id_by_name (ji->data.target);
4849 if (!exc_throw_found [i]) {
4851 exc_throw_found [i] = TRUE;
4856 code = realloc_code (cfg, size);
4858 /* Emit code to raise corlib exceptions */
4859 for (ji = cfg->patch_info; ji; ji = ji->next) {
4860 if (ji->type != MONO_PATCH_INFO_EXC)
4863 ip = cfg->native_code + ji->ip.i;
4865 id = mini_exception_id_by_name (ji->data.target);
4867 if (exc_throw_pos [id]) {
4868 /* ip points to the bcc () in OP_COND_EXC_... */
4869 arm_patch_rel (ip, exc_throw_pos [id], ji->relocation);
4870 ji->type = MONO_PATCH_INFO_NONE;
4874 exc_throw_pos [id] = code;
4875 arm_patch_rel (ip, code, ji->relocation);
4877 /* We are being branched to from the code generated by emit_cond_exc (), the pc is in ip1 */
4879 /* r0 = type token */
4880 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", ji->data.name);
4881 code = emit_imm (code, ARMREG_R0, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
4883 arm_movx (code, ARMREG_R1, ARMREG_IP1);
4884 /* Branch to the corlib exception throwing trampoline */
4885 ji->ip.i = code - cfg->native_code;
4886 ji->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4887 ji->data.name = "mono_arch_throw_corlib_exception";
4888 ji->relocation = MONO_R_ARM64_BL;
4890 cfg->thunk_area += THUNK_SIZE;
4893 cfg->code_len = code - cfg->native_code;
4895 g_assert (cfg->code_len < cfg->code_size);
4899 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4905 mono_arch_print_tree (MonoInst *tree, int arity)
4911 mono_arch_get_patch_offset (guint8 *code)
4917 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
4918 gpointer fail_tramp)
4920 int i, buf_len, imt_reg;
4924 printf ("building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable);
4925 for (i = 0; i < count; ++i) {
4926 MonoIMTCheckItem *item = imt_entries [i];
4927 printf ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, item->key->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
4932 for (i = 0; i < count; ++i) {
4933 MonoIMTCheckItem *item = imt_entries [i];
4934 if (item->is_equals) {
4935 gboolean fail_case = !item->check_target_idx && fail_tramp;
4937 if (item->check_target_idx || fail_case) {
4938 if (!item->compare_done || fail_case) {
4939 buf_len += 4 * 4 + 4;
4942 if (item->has_target_code) {
4959 buf = mono_method_alloc_generic_virtual_thunk (domain, buf_len);
4961 buf = mono_domain_code_reserve (domain, buf_len);
4965 * We are called by JITted code, which passes in the IMT argument in
4966 * MONO_ARCH_RGCTX_REG (r27). We need to preserve all caller saved regs
4969 imt_reg = MONO_ARCH_RGCTX_REG;
4970 for (i = 0; i < count; ++i) {
4971 MonoIMTCheckItem *item = imt_entries [i];
4973 item->code_target = code;
4975 if (item->is_equals) {
4977 * Check the imt argument against item->key, if equals, jump to either
4978 * item->value.target_code or to vtable [item->value.vtable_slot].
4979 * If fail_tramp is set, jump to it if not-equals.
4981 gboolean fail_case = !item->check_target_idx && fail_tramp;
4983 if (item->check_target_idx || fail_case) {
4984 /* Compare imt_reg with item->key */
4985 if (!item->compare_done || fail_case) {
4986 // FIXME: Optimize this
4987 code = emit_imm64 (code, ARMREG_IP0, (guint64)item->key);
4988 arm_cmpx (code, imt_reg, ARMREG_IP0);
4990 item->jmp_code = code;
4991 arm_bcc (code, ARMCOND_NE, 0);
4992 /* Jump to target if equals */
4993 if (item->has_target_code) {
4994 code = emit_imm64 (code, ARMREG_IP0, (guint64)item->value.target_code);
4995 arm_brx (code, ARMREG_IP0);
4997 guint64 imm = (guint64)&(vtable->vtable [item->value.vtable_slot]);
4999 code = emit_imm64 (code, ARMREG_IP0, imm);
5000 arm_ldrx (code, ARMREG_IP0, ARMREG_IP0, 0);
5001 arm_brx (code, ARMREG_IP0);
5005 arm_patch_rel (item->jmp_code, code, MONO_R_ARM64_BCC);
5006 item->jmp_code = NULL;
5007 code = emit_imm64 (code, ARMREG_IP0, (guint64)fail_tramp);
5008 arm_brx (code, ARMREG_IP0);
5011 guint64 imm = (guint64)&(vtable->vtable [item->value.vtable_slot]);
5013 code = emit_imm64 (code, ARMREG_IP0, imm);
5014 arm_ldrx (code, ARMREG_IP0, ARMREG_IP0, 0);
5015 arm_brx (code, ARMREG_IP0);
5018 code = emit_imm64 (code, ARMREG_IP0, (guint64)item->key);
5019 arm_cmpx (code, imt_reg, ARMREG_IP0);
5020 item->jmp_code = code;
5021 arm_bcc (code, ARMCOND_HS, 0);
5024 /* Patch the branches */
5025 for (i = 0; i < count; ++i) {
5026 MonoIMTCheckItem *item = imt_entries [i];
5027 if (item->jmp_code && item->check_target_idx)
5028 arm_patch_rel (item->jmp_code, imt_entries [item->check_target_idx]->code_target, MONO_R_ARM64_BCC);
5031 g_assert ((code - buf) < buf_len);
5033 mono_arch_flush_icache (buf, code - buf);
5039 mono_arch_get_trampolines (gboolean aot)
5041 return mono_arm_get_exception_trampolines (aot);
5044 #else /* DISABLE_JIT */
5047 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5048 gpointer fail_tramp)
5050 g_assert_not_reached ();
5054 #endif /* !DISABLE_JIT */
5056 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
5059 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
5062 guint32 native_offset = ip - (guint8*)ji->code_start;
5065 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5067 g_assert (native_offset % 4 == 0);
5068 g_assert (info->bp_addrs [native_offset / 4] == 0);
5069 info->bp_addrs [native_offset / 4] = mini_get_breakpoint_trampoline ();
5071 /* ip points to an ldrx */
5073 arm_blrx (code, ARMREG_IP0);
5074 mono_arch_flush_icache (ip, code - ip);
5079 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
5084 guint32 native_offset = ip - (guint8*)ji->code_start;
5085 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
5087 g_assert (native_offset % 4 == 0);
5088 info->bp_addrs [native_offset / 4] = NULL;
5090 /* ip points to an ldrx */
5093 mono_arch_flush_icache (ip, code - ip);
5098 mono_arch_start_single_stepping (void)
5100 ss_trampoline = mini_get_single_step_trampoline ();
5104 mono_arch_stop_single_stepping (void)
5106 ss_trampoline = NULL;
5110 mono_arch_is_single_step_event (void *info, void *sigctx)
5112 /* We use soft breakpoints on arm64 */
5117 mono_arch_is_breakpoint_event (void *info, void *sigctx)
5119 /* We use soft breakpoints on arm64 */
5124 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
5126 g_assert_not_reached ();
5130 mono_arch_skip_single_step (MonoContext *ctx)
5132 g_assert_not_reached ();
5136 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
5141 // FIXME: Add a free function
5143 mono_domain_lock (domain);
5144 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
5146 mono_domain_unlock (domain);
5149 ji = mono_jit_info_table_find (domain, (char*)code);
5152 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size / 4) * sizeof(guint8*));
5154 info->ss_tramp_addr = &ss_trampoline;
5156 mono_domain_lock (domain);
5157 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
5159 mono_domain_unlock (domain);
5166 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
5168 ext->lmf.previous_lmf = prev_lmf;
5169 /* Mark that this is a MonoLMFExt */
5170 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
5171 ext->lmf.gregs [MONO_ARCH_LMF_REG_SP] = (gssize)ext;
5174 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
5177 mono_arch_opcode_supported (int opcode)
5180 case OP_ATOMIC_ADD_I4:
5181 case OP_ATOMIC_ADD_I8:
5182 case OP_ATOMIC_EXCHANGE_I4:
5183 case OP_ATOMIC_EXCHANGE_I8:
5184 case OP_ATOMIC_CAS_I4:
5185 case OP_ATOMIC_CAS_I8:
5186 case OP_ATOMIC_LOAD_I1:
5187 case OP_ATOMIC_LOAD_I2:
5188 case OP_ATOMIC_LOAD_I4:
5189 case OP_ATOMIC_LOAD_I8:
5190 case OP_ATOMIC_LOAD_U1:
5191 case OP_ATOMIC_LOAD_U2:
5192 case OP_ATOMIC_LOAD_U4:
5193 case OP_ATOMIC_LOAD_U8:
5194 case OP_ATOMIC_LOAD_R4:
5195 case OP_ATOMIC_LOAD_R8:
5196 case OP_ATOMIC_STORE_I1:
5197 case OP_ATOMIC_STORE_I2:
5198 case OP_ATOMIC_STORE_I4:
5199 case OP_ATOMIC_STORE_I8:
5200 case OP_ATOMIC_STORE_U1:
5201 case OP_ATOMIC_STORE_U2:
5202 case OP_ATOMIC_STORE_U4:
5203 case OP_ATOMIC_STORE_U8:
5204 case OP_ATOMIC_STORE_R4:
5205 case OP_ATOMIC_STORE_R8:
5213 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
5215 return get_call_info (mp, sig);