2 * mini-arm.c: ARM backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
8 * (C) 2003 Ximian, Inc.
9 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
10 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
11 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
16 #include <mono/metadata/abi-details.h>
17 #include <mono/metadata/appdomain.h>
18 #include <mono/metadata/profiler-private.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/utils/mono-mmap.h>
21 #include <mono/utils/mono-hwcap-arm.h>
22 #include <mono/utils/mono-memory-model.h>
23 #include <mono/utils/mono-threads-coop.h>
26 #include "mini-arm-tls.h"
30 #include "debugger-agent.h"
32 #include "mono/arch/arm/arm-vfp-codegen.h"
34 #if (defined(HAVE_KW_THREAD) && defined(__linux__) && defined(__ARM_EABI__)) \
35 || defined(TARGET_ANDROID) \
36 || (defined(TARGET_IOS) && !defined(TARGET_WATCHOS))
40 /* Sanity check: This makes no sense */
41 #if defined(ARM_FPU_NONE) && (defined(ARM_FPU_VFP) || defined(ARM_FPU_VFP_HARD))
42 #error "ARM_FPU_NONE is defined while one of ARM_FPU_VFP/ARM_FPU_VFP_HARD is defined"
46 * IS_SOFT_FLOAT: Is full software floating point used?
47 * IS_HARD_FLOAT: Is full hardware floating point used?
48 * IS_VFP: Is hardware floating point with software ABI used?
50 * These are not necessarily constants, e.g. IS_SOFT_FLOAT and
51 * IS_VFP may delegate to mono_arch_is_soft_float ().
54 #if defined(ARM_FPU_VFP_HARD)
55 #define IS_SOFT_FLOAT (FALSE)
56 #define IS_HARD_FLOAT (TRUE)
58 #elif defined(ARM_FPU_NONE)
59 #define IS_SOFT_FLOAT (mono_arch_is_soft_float ())
60 #define IS_HARD_FLOAT (FALSE)
61 #define IS_VFP (!mono_arch_is_soft_float ())
63 #define IS_SOFT_FLOAT (FALSE)
64 #define IS_HARD_FLOAT (FALSE)
68 #define THUNK_SIZE (3 * 4)
70 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
73 void sys_icache_invalidate (void *start, size_t len);
76 /* This mutex protects architecture specific caches */
77 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
78 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
79 static mono_mutex_t mini_arch_mutex;
81 static gboolean v5_supported = FALSE;
82 static gboolean v6_supported = FALSE;
83 static gboolean v7_supported = FALSE;
84 static gboolean v7s_supported = FALSE;
85 static gboolean v7k_supported = FALSE;
86 static gboolean thumb_supported = FALSE;
87 static gboolean thumb2_supported = FALSE;
89 * Whenever to use the ARM EABI
91 static gboolean eabi_supported = FALSE;
94 * Whenever to use the iphone ABI extensions:
95 * http://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/index.html
96 * Basically, r7 is used as a frame pointer and it should point to the saved r7 + lr.
97 * This is required for debugging/profiling tools to work, but it has some overhead so it should
98 * only be turned on in debug builds.
100 static gboolean iphone_abi = FALSE;
103 * The FPU we are generating code for. This is NOT runtime configurable right now,
104 * since some things like MONO_ARCH_CALLEE_FREGS still depend on defines.
106 static MonoArmFPU arm_fpu;
108 #if defined(ARM_FPU_VFP_HARD)
110 * On armhf, d0-d7 are used for argument passing and d8-d15
111 * must be preserved across calls, which leaves us no room
112 * for scratch registers. So we use d14-d15 but back up their
113 * previous contents to a stack slot before using them - see
114 * mono_arm_emit_vfp_scratch_save/_restore ().
116 static int vfp_scratch1 = ARM_VFP_D14;
117 static int vfp_scratch2 = ARM_VFP_D15;
120 * On armel, d0-d7 do not need to be preserved, so we can
121 * freely make use of them as scratch registers.
123 static int vfp_scratch1 = ARM_VFP_D0;
124 static int vfp_scratch2 = ARM_VFP_D1;
129 static gpointer single_step_tramp, breakpoint_tramp;
132 * The code generated for sequence points reads from this location, which is
133 * made read-only when single stepping is enabled.
135 static gpointer ss_trigger_page;
137 /* Enabled breakpoints read from this trigger page */
138 static gpointer bp_trigger_page;
142 * floating point support: on ARM it is a mess, there are at least 3
143 * different setups, each of which binary incompat with the other.
144 * 1) FPA: old and ugly, but unfortunately what current distros use
145 * the double binary format has the two words swapped. 8 double registers.
146 * Implemented usually by kernel emulation.
147 * 2) softfloat: the compiler emulates all the fp ops. Usually uses the
148 * ugly swapped double format (I guess a softfloat-vfp exists, too, though).
149 * 3) VFP: the new and actually sensible and useful FP support. Implemented
150 * in HW or kernel-emulated, requires new tools. I think this is what symbian uses.
152 * We do not care about FPA. We will support soft float and VFP.
154 int mono_exc_esp_offset = 0;
156 #define arm_is_imm12(v) ((v) > -4096 && (v) < 4096)
157 #define arm_is_imm8(v) ((v) > -256 && (v) < 256)
158 #define arm_is_fpimm8(v) ((v) >= -1020 && (v) <= 1020)
160 #define LDR_MASK ((0xf << ARMCOND_SHIFT) | (3 << 26) | (1 << 22) | (1 << 20) | (15 << 12))
161 #define LDR_PC_VAL ((ARMCOND_AL << ARMCOND_SHIFT) | (1 << 26) | (0 << 22) | (1 << 20) | (15 << 12))
162 #define IS_LDR_PC(val) (((val) & LDR_MASK) == LDR_PC_VAL)
164 //#define DEBUG_IMT 0
167 static void mono_arch_compute_omit_fp (MonoCompile *cfg);
171 mono_arch_regname (int reg)
173 static const char * rnames[] = {
174 "arm_r0", "arm_r1", "arm_r2", "arm_r3", "arm_v1",
175 "arm_v2", "arm_v3", "arm_v4", "arm_v5", "arm_v6",
176 "arm_v7", "arm_fp", "arm_ip", "arm_sp", "arm_lr",
179 if (reg >= 0 && reg < 16)
185 mono_arch_fregname (int reg)
187 static const char * rnames[] = {
188 "arm_f0", "arm_f1", "arm_f2", "arm_f3", "arm_f4",
189 "arm_f5", "arm_f6", "arm_f7", "arm_f8", "arm_f9",
190 "arm_f10", "arm_f11", "arm_f12", "arm_f13", "arm_f14",
191 "arm_f15", "arm_f16", "arm_f17", "arm_f18", "arm_f19",
192 "arm_f20", "arm_f21", "arm_f22", "arm_f23", "arm_f24",
193 "arm_f25", "arm_f26", "arm_f27", "arm_f28", "arm_f29",
196 if (reg >= 0 && reg < 32)
204 emit_big_add (guint8 *code, int dreg, int sreg, int imm)
206 int imm8, rot_amount;
207 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
208 ARM_ADD_REG_IMM (code, dreg, sreg, imm8, rot_amount);
212 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
213 ARM_ADD_REG_REG (code, dreg, sreg, ARMREG_IP);
215 code = mono_arm_emit_load_imm (code, dreg, imm);
216 ARM_ADD_REG_REG (code, dreg, dreg, sreg);
221 /* If dreg == sreg, this clobbers IP */
223 emit_sub_imm (guint8 *code, int dreg, int sreg, int imm)
225 int imm8, rot_amount;
226 if ((imm8 = mono_arm_is_rotated_imm8 (imm, &rot_amount)) >= 0) {
227 ARM_SUB_REG_IMM (code, dreg, sreg, imm8, rot_amount);
231 code = mono_arm_emit_load_imm (code, ARMREG_IP, imm);
232 ARM_SUB_REG_REG (code, dreg, sreg, ARMREG_IP);
234 code = mono_arm_emit_load_imm (code, dreg, imm);
235 ARM_SUB_REG_REG (code, dreg, dreg, sreg);
241 emit_memcpy (guint8 *code, int size, int dreg, int doffset, int sreg, int soffset)
243 /* we can use r0-r3, since this is called only for incoming args on the stack */
244 if (size > sizeof (gpointer) * 4) {
246 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
247 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
248 start_loop = code = mono_arm_emit_load_imm (code, ARMREG_R2, size);
249 ARM_LDR_IMM (code, ARMREG_R3, ARMREG_R0, 0);
250 ARM_STR_IMM (code, ARMREG_R3, ARMREG_R1, 0);
251 ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, 4);
252 ARM_ADD_REG_IMM8 (code, ARMREG_R1, ARMREG_R1, 4);
253 ARM_SUBS_REG_IMM8 (code, ARMREG_R2, ARMREG_R2, 4);
254 ARM_B_COND (code, ARMCOND_NE, 0);
255 arm_patch (code - 4, start_loop);
258 if (arm_is_imm12 (doffset) && arm_is_imm12 (doffset + size) &&
259 arm_is_imm12 (soffset) && arm_is_imm12 (soffset + size)) {
261 ARM_LDR_IMM (code, ARMREG_LR, sreg, soffset);
262 ARM_STR_IMM (code, ARMREG_LR, dreg, doffset);
268 code = emit_big_add (code, ARMREG_R0, sreg, soffset);
269 code = emit_big_add (code, ARMREG_R1, dreg, doffset);
270 doffset = soffset = 0;
272 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_R0, soffset);
273 ARM_STR_IMM (code, ARMREG_LR, ARMREG_R1, doffset);
279 g_assert (size == 0);
284 emit_call_reg (guint8 *code, int reg)
287 ARM_BLX_REG (code, reg);
289 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
293 ARM_MOV_REG_REG (code, ARMREG_PC, reg);
299 emit_call_seq (MonoCompile *cfg, guint8 *code)
301 if (cfg->method->dynamic) {
302 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
304 *(gpointer*)code = NULL;
306 code = emit_call_reg (code, ARMREG_IP);
310 cfg->thunk_area += THUNK_SIZE;
315 mono_arm_patchable_b (guint8 *code, int cond)
317 ARM_B_COND (code, cond, 0);
322 mono_arm_patchable_bl (guint8 *code, int cond)
324 ARM_BL_COND (code, cond, 0);
329 mono_arm_emit_tls_get (MonoCompile *cfg, guint8* code, int dreg, int tls_offset)
332 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
333 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
335 code = emit_call_seq (cfg, code);
336 if (dreg != ARMREG_R0)
337 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
339 g_assert_not_reached ();
345 mono_arm_emit_tls_get_reg (MonoCompile *cfg, guint8* code, int dreg, int tls_offset_reg)
348 if (tls_offset_reg != ARMREG_R0)
349 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
350 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
352 code = emit_call_seq (cfg, code);
353 if (dreg != ARMREG_R0)
354 ARM_MOV_REG_REG (code, dreg, ARMREG_R0);
356 g_assert_not_reached ();
362 mono_arm_emit_tls_set (MonoCompile *cfg, guint8* code, int sreg, int tls_offset)
365 if (sreg != ARMREG_R1)
366 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
367 code = mono_arm_emit_load_imm (code, ARMREG_R0, tls_offset);
368 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
370 code = emit_call_seq (cfg, code);
372 g_assert_not_reached ();
378 mono_arm_emit_tls_set_reg (MonoCompile *cfg, guint8* code, int sreg, int tls_offset_reg)
381 /* Get sreg in R1 and tls_offset_reg in R0 */
382 if (tls_offset_reg == ARMREG_R1) {
383 if (sreg == ARMREG_R0) {
384 /* swap sreg and tls_offset_reg */
385 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
386 ARM_EOR_REG_REG (code, tls_offset_reg, sreg, tls_offset_reg);
387 ARM_EOR_REG_REG (code, sreg, sreg, tls_offset_reg);
389 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
390 if (sreg != ARMREG_R1)
391 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
394 if (sreg != ARMREG_R1)
395 ARM_MOV_REG_REG (code, ARMREG_R1, sreg);
396 if (tls_offset_reg != ARMREG_R0)
397 ARM_MOV_REG_REG (code, ARMREG_R0, tls_offset_reg);
399 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
401 code = emit_call_seq (cfg, code);
403 g_assert_not_reached ();
411 * Emit code to push an LMF structure on the LMF stack.
412 * On arm, this is intermixed with the initialization of other fields of the structure.
415 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
417 gboolean get_lmf_fast = FALSE;
420 if (mono_arm_have_tls_get ()) {
422 if (cfg->compile_aot) {
424 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_TLS_OFFSET, (gpointer)TLS_KEY_LMF_ADDR);
425 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
427 *(gpointer*)code = NULL;
429 /* Load the value from the GOT */
430 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_PC, ARMREG_R1);
431 code = mono_arm_emit_tls_get_reg (cfg, code, ARMREG_R0, ARMREG_R1);
433 gint32 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
434 g_assert (lmf_addr_tls_offset != -1);
435 code = mono_arm_emit_tls_get (cfg, code, ARMREG_R0, lmf_addr_tls_offset);
440 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
441 (gpointer)"mono_get_lmf_addr");
442 code = emit_call_seq (cfg, code);
444 /* we build the MonoLMF structure on the stack - see mini-arm.h */
445 /* lmf_offset is the offset from the previous stack pointer,
446 * alloc_size is the total stack space allocated, so the offset
447 * of MonoLMF from the current stack ptr is alloc_size - lmf_offset.
448 * The pointer to the struct is put in r1 (new_lmf).
449 * ip is used as scratch
450 * The callee-saved registers are already in the MonoLMF structure
452 code = emit_big_add (code, ARMREG_R1, ARMREG_SP, lmf_offset);
453 /* r0 is the result from mono_get_lmf_addr () */
454 ARM_STR_IMM (code, ARMREG_R0, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
455 /* new_lmf->previous_lmf = *lmf_addr */
456 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
457 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
458 /* *(lmf_addr) = r1 */
459 ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
460 /* Skip method (only needed for trampoline LMF frames) */
461 ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, sp));
462 ARM_STR_IMM (code, ARMREG_FP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, fp));
463 /* save the current IP */
464 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_PC);
465 ARM_STR_IMM (code, ARMREG_IP, ARMREG_R1, MONO_STRUCT_OFFSET (MonoLMF, ip));
467 for (i = 0; i < sizeof (MonoLMF); i += sizeof (mgreg_t))
468 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + i, SLOT_NOREF);
479 emit_float_args (MonoCompile *cfg, MonoCallInst *inst, guint8 *code, int *max_len, guint *offset)
483 for (list = inst->float_args; list; list = list->next) {
484 FloatArgData *fad = list->data;
485 MonoInst *var = get_vreg_to_inst (cfg, fad->vreg);
486 gboolean imm = arm_is_fpimm8 (var->inst_offset);
488 /* 4+1 insns for emit_big_add () and 1 for FLDS. */
494 if (*offset + *max_len > cfg->code_size) {
495 cfg->code_size += *max_len;
496 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
498 code = cfg->native_code + *offset;
502 code = emit_big_add (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
503 ARM_FLDS (code, fad->hreg, ARMREG_LR, 0);
505 ARM_FLDS (code, fad->hreg, var->inst_basereg, var->inst_offset);
507 *offset = code - cfg->native_code;
514 mono_arm_emit_vfp_scratch_save (MonoCompile *cfg, guint8 *code, int reg)
518 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
520 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
523 if (!arm_is_fpimm8 (inst->inst_offset)) {
524 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
525 ARM_FSTD (code, reg, ARMREG_LR, 0);
527 ARM_FSTD (code, reg, inst->inst_basereg, inst->inst_offset);
534 mono_arm_emit_vfp_scratch_restore (MonoCompile *cfg, guint8 *code, int reg)
538 g_assert (reg == vfp_scratch1 || reg == vfp_scratch2);
540 inst = (MonoInst *) cfg->arch.vfp_scratch_slots [reg == vfp_scratch1 ? 0 : 1];
543 if (!arm_is_fpimm8 (inst->inst_offset)) {
544 code = emit_big_add (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
545 ARM_FLDD (code, reg, ARMREG_LR, 0);
547 ARM_FLDD (code, reg, inst->inst_basereg, inst->inst_offset);
556 * Emit code to pop an LMF structure from the LMF stack.
559 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
563 if (lmf_offset < 32) {
564 basereg = cfg->frame_reg;
569 code = emit_big_add (code, ARMREG_R2, cfg->frame_reg, lmf_offset);
572 /* ip = previous_lmf */
573 ARM_LDR_IMM (code, ARMREG_IP, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
575 ARM_LDR_IMM (code, ARMREG_LR, basereg, offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr));
576 /* *(lmf_addr) = previous_lmf */
577 ARM_STR_IMM (code, ARMREG_IP, ARMREG_LR, MONO_STRUCT_OFFSET (MonoLMF, previous_lmf));
582 #endif /* #ifndef DISABLE_JIT */
585 * mono_arm_have_tls_get:
587 * Returns whether we have tls access implemented on the current
591 mono_arm_have_tls_get (void)
601 * mono_arch_get_argument_info:
602 * @csig: a method signature
603 * @param_count: the number of parameters to consider
604 * @arg_info: an array to store the result infos
606 * Gathers information on parameters such as size, alignment and
607 * padding. arg_info should be large enought to hold param_count + 1 entries.
609 * Returns the size of the activation frame.
612 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
614 int k, frame_size = 0;
615 guint32 size, align, pad;
619 t = mini_get_underlying_type (csig->ret);
620 if (MONO_TYPE_ISSTRUCT (t)) {
621 frame_size += sizeof (gpointer);
625 arg_info [0].offset = offset;
628 frame_size += sizeof (gpointer);
632 arg_info [0].size = frame_size;
634 for (k = 0; k < param_count; k++) {
635 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
637 /* ignore alignment for now */
640 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
641 arg_info [k].pad = pad;
643 arg_info [k + 1].pad = 0;
644 arg_info [k + 1].size = size;
646 arg_info [k + 1].offset = offset;
650 align = MONO_ARCH_FRAME_ALIGNMENT;
651 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
652 arg_info [k].pad = pad;
657 #define MAX_ARCH_DELEGATE_PARAMS 3
660 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, gboolean param_count)
662 guint8 *code, *start;
663 GSList *unwind_ops = mono_arch_get_cie_program ();
666 start = code = mono_global_codeman_reserve (12);
668 /* Replace the this argument with the target */
669 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
670 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, target));
671 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
673 g_assert ((code - start) <= 12);
675 mono_arch_flush_icache (start, 12);
679 size = 8 + param_count * 4;
680 start = code = mono_global_codeman_reserve (size);
682 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_R0, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
683 /* slide down the arguments */
684 for (i = 0; i < param_count; ++i) {
685 ARM_MOV_REG_REG (code, (ARMREG_R0 + i), (ARMREG_R0 + i + 1));
687 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
689 g_assert ((code - start) <= size);
691 mono_arch_flush_icache (start, size);
695 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
697 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
698 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
702 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
708 * mono_arch_get_delegate_invoke_impls:
710 * Return a list of MonoAotTrampInfo structures for the delegate invoke impl
714 mono_arch_get_delegate_invoke_impls (void)
720 get_delegate_invoke_impl (&info, TRUE, 0);
721 res = g_slist_prepend (res, info);
723 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
724 get_delegate_invoke_impl (&info, FALSE, i);
725 res = g_slist_prepend (res, info);
732 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
734 guint8 *code, *start;
737 /* FIXME: Support more cases */
738 sig_ret = mini_get_underlying_type (sig->ret);
739 if (MONO_TYPE_ISSTRUCT (sig_ret))
743 static guint8* cached = NULL;
744 mono_mini_arch_lock ();
746 mono_mini_arch_unlock ();
751 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
754 start = get_delegate_invoke_impl (&info, TRUE, 0);
755 mono_tramp_info_register (info, NULL);
758 mono_mini_arch_unlock ();
761 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
764 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
766 for (i = 0; i < sig->param_count; ++i)
767 if (!mono_is_regsize_var (sig->params [i]))
770 mono_mini_arch_lock ();
771 code = cache [sig->param_count];
773 mono_mini_arch_unlock ();
778 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
779 start = mono_aot_get_trampoline (name);
783 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
784 mono_tramp_info_register (info, NULL);
786 cache [sig->param_count] = start;
787 mono_mini_arch_unlock ();
795 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
801 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
803 return (gpointer)regs [ARMREG_R0];
807 * Initialize the cpu to execute managed code.
810 mono_arch_cpu_init (void)
812 i8_align = MONO_ABI_ALIGNOF (gint64);
813 #ifdef MONO_CROSS_COMPILE
814 /* Need to set the alignment of i8 since it can different on the target */
815 #ifdef TARGET_ANDROID
817 mono_type_set_alignment (MONO_TYPE_I8, i8_align);
823 * Initialize architecture specific code.
826 mono_arch_init (void)
828 const char *cpu_arch;
830 mono_os_mutex_init_recursive (&mini_arch_mutex);
831 if (mini_get_debug_options ()->soft_breakpoints) {
832 breakpoint_tramp = mini_get_breakpoint_trampoline ();
834 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
835 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
836 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
839 mono_aot_register_jit_icall ("mono_arm_throw_exception", mono_arm_throw_exception);
840 mono_aot_register_jit_icall ("mono_arm_throw_exception_by_token", mono_arm_throw_exception_by_token);
841 mono_aot_register_jit_icall ("mono_arm_resume_unwind", mono_arm_resume_unwind);
842 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
843 mono_aot_register_jit_icall ("mono_arm_start_gsharedvt_call", mono_arm_start_gsharedvt_call);
845 mono_aot_register_jit_icall ("mono_arm_unaligned_stack", mono_arm_unaligned_stack);
847 #if defined(__ARM_EABI__)
848 eabi_supported = TRUE;
851 #if defined(ARM_FPU_VFP_HARD)
852 arm_fpu = MONO_ARM_FPU_VFP_HARD;
854 arm_fpu = MONO_ARM_FPU_VFP;
856 #if defined(ARM_FPU_NONE) && !defined(__APPLE__)
858 * If we're compiling with a soft float fallback and it
859 * turns out that no VFP unit is available, we need to
860 * switch to soft float. We don't do this for iOS, since
861 * iOS devices always have a VFP unit.
863 if (!mono_hwcap_arm_has_vfp)
864 arm_fpu = MONO_ARM_FPU_NONE;
867 * This environment variable can be useful in testing
868 * environments to make sure the soft float fallback
869 * works. Most ARM devices have VFP units these days, so
870 * normally soft float code would not be exercised much.
872 const char *soft = g_getenv ("MONO_ARM_FORCE_SOFT_FLOAT");
874 if (soft && !strncmp (soft, "1", 1))
875 arm_fpu = MONO_ARM_FPU_NONE;
879 v5_supported = mono_hwcap_arm_is_v5;
880 v6_supported = mono_hwcap_arm_is_v6;
881 v7_supported = mono_hwcap_arm_is_v7;
883 #if defined(__APPLE__)
884 /* iOS is special-cased here because we don't yet
885 have a way to properly detect CPU features on it. */
886 thumb_supported = TRUE;
889 thumb_supported = mono_hwcap_arm_has_thumb;
890 thumb2_supported = mono_hwcap_arm_has_thumb2;
893 /* Format: armv(5|6|7[s])[-thumb[2]] */
894 cpu_arch = g_getenv ("MONO_CPU_ARCH");
896 /* Do this here so it overrides any detection. */
898 if (strncmp (cpu_arch, "armv", 4) == 0) {
899 v5_supported = cpu_arch [4] >= '5';
900 v6_supported = cpu_arch [4] >= '6';
901 v7_supported = cpu_arch [4] >= '7';
902 v7s_supported = strncmp (cpu_arch, "armv7s", 6) == 0;
903 v7k_supported = strncmp (cpu_arch, "armv7k", 6) == 0;
906 thumb_supported = strstr (cpu_arch, "thumb") != NULL;
907 thumb2_supported = strstr (cpu_arch, "thumb2") != NULL;
912 * Cleanup architecture specific code.
915 mono_arch_cleanup (void)
920 * This function returns the optimizations supported on this cpu.
923 mono_arch_cpu_optimizations (guint32 *exclude_mask)
925 /* no arm-specific optimizations yet */
931 * This function test for all SIMD functions supported.
933 * Returns a bitmask corresponding to all supported versions.
937 mono_arch_cpu_enumerate_simd_versions (void)
939 /* SIMD is currently unimplemented */
944 mono_arm_is_hard_float (void)
946 return arm_fpu == MONO_ARM_FPU_VFP_HARD;
952 mono_arch_opcode_needs_emulation (MonoCompile *cfg, int opcode)
954 if (v7s_supported || v7k_supported) {
968 #ifdef MONO_ARCH_SOFT_FLOAT_FALLBACK
970 mono_arch_is_soft_float (void)
972 return arm_fpu == MONO_ARM_FPU_NONE;
977 is_regsize_var (MonoType *t)
981 t = mini_get_underlying_type (t);
988 case MONO_TYPE_FNPTR:
990 case MONO_TYPE_OBJECT:
991 case MONO_TYPE_STRING:
992 case MONO_TYPE_CLASS:
993 case MONO_TYPE_SZARRAY:
994 case MONO_TYPE_ARRAY:
996 case MONO_TYPE_GENERICINST:
997 if (!mono_type_generic_inst_is_valuetype (t))
1000 case MONO_TYPE_VALUETYPE:
1007 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1012 for (i = 0; i < cfg->num_varinfo; i++) {
1013 MonoInst *ins = cfg->varinfo [i];
1014 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1017 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1020 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1023 /* we can only allocate 32 bit values */
1024 if (is_regsize_var (ins->inst_vtype)) {
1025 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1026 g_assert (i == vmv->idx);
1027 vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
1035 mono_arch_get_global_int_regs (MonoCompile *cfg)
1039 mono_arch_compute_omit_fp (cfg);
1042 * FIXME: Interface calls might go through a static rgctx trampoline which
1043 * sets V5, but it doesn't save it, so we need to save it ourselves, and
1046 if (cfg->flags & MONO_CFG_HAS_CALLS)
1047 cfg->uses_rgctx_reg = TRUE;
1049 if (cfg->arch.omit_fp)
1050 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_FP));
1051 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V1));
1052 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V2));
1053 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V3));
1055 /* V4=R7 is used as a frame pointer, but V7=R10 is preserved */
1056 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));
1058 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V4));
1059 if (!(cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg)))
1060 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1061 regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V5));
1062 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V6));*/
1063 /*regs = g_list_prepend (regs, GUINT_TO_POINTER (ARMREG_V7));*/
1069 * mono_arch_regalloc_cost:
1071 * Return the cost, in number of memory references, of the action of
1072 * allocating the variable VMV into a register during global register
1076 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1082 #endif /* #ifndef DISABLE_JIT */
1085 mono_arch_flush_icache (guint8 *code, gint size)
1087 #if defined(MONO_CROSS_COMPILE)
1089 sys_icache_invalidate (code, size);
1091 __builtin___clear_cache (code, code + size);
1098 add_general (guint *gr, guint *stack_size, ArgInfo *ainfo, gboolean simple)
1101 if (*gr > ARMREG_R3) {
1103 ainfo->offset = *stack_size;
1104 ainfo->reg = ARMREG_SP; /* in the caller */
1105 ainfo->storage = RegTypeBase;
1108 ainfo->storage = RegTypeGeneral;
1115 split = i8_align == 4;
1120 if (*gr == ARMREG_R3 && split) {
1121 /* first word in r3 and the second on the stack */
1122 ainfo->offset = *stack_size;
1123 ainfo->reg = ARMREG_SP; /* in the caller */
1124 ainfo->storage = RegTypeBaseGen;
1126 } else if (*gr >= ARMREG_R3) {
1127 if (eabi_supported) {
1128 /* darwin aligns longs to 4 byte only */
1129 if (i8_align == 8) {
1134 ainfo->offset = *stack_size;
1135 ainfo->reg = ARMREG_SP; /* in the caller */
1136 ainfo->storage = RegTypeBase;
1139 if (eabi_supported) {
1140 if (i8_align == 8 && ((*gr) & 1))
1143 ainfo->storage = RegTypeIRegPair;
1152 add_float (guint *fpr, guint *stack_size, ArgInfo *ainfo, gboolean is_double, gint *float_spare)
1155 * If we're calling a function like this:
1157 * void foo(float a, double b, float c)
1159 * We pass a in s0 and b in d1. That leaves us
1160 * with s1 being unused. The armhf ABI recognizes
1161 * this and requires register assignment to then
1162 * use that for the next single-precision arg,
1163 * i.e. c in this example. So float_spare either
1164 * tells us which reg to use for the next single-
1165 * precision arg, or it's -1, meaning use *fpr.
1167 * Note that even though most of the JIT speaks
1168 * double-precision, fpr represents single-
1169 * precision registers.
1171 * See parts 5.5 and 6.1.2 of the AAPCS for how
1175 if (*fpr < ARM_VFP_F16 || (!is_double && *float_spare >= 0)) {
1176 ainfo->storage = RegTypeFP;
1180 * If we're passing a double-precision value
1181 * and *fpr is odd (e.g. it's s1, s3, ...)
1182 * we need to use the next even register. So
1183 * we mark the current *fpr as a spare that
1184 * can be used for the next single-precision
1188 *float_spare = *fpr;
1193 * At this point, we have an even register
1194 * so we assign that and move along.
1198 } else if (*float_spare >= 0) {
1200 * We're passing a single-precision value
1201 * and it looks like a spare single-
1202 * precision register is available. Let's
1206 ainfo->reg = *float_spare;
1210 * If we hit this branch, we're passing a
1211 * single-precision value and we can simply
1212 * use the next available register.
1220 * We've exhausted available floating point
1221 * regs, so pass the rest on the stack.
1229 ainfo->offset = *stack_size;
1230 ainfo->reg = ARMREG_SP;
1231 ainfo->storage = RegTypeBase;
1238 is_hfa (MonoType *t, int *out_nfields, int *out_esize)
1242 MonoClassField *field;
1243 MonoType *ftype, *prev_ftype = NULL;
1246 klass = mono_class_from_mono_type (t);
1248 while ((field = mono_class_get_fields (klass, &iter))) {
1249 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
1251 ftype = mono_field_get_type (field);
1252 ftype = mini_get_underlying_type (ftype);
1254 if (MONO_TYPE_ISSTRUCT (ftype)) {
1255 int nested_nfields, nested_esize;
1257 if (!is_hfa (ftype, &nested_nfields, &nested_esize))
1259 if (nested_esize == 4)
1260 ftype = &mono_defaults.single_class->byval_arg;
1262 ftype = &mono_defaults.double_class->byval_arg;
1263 if (prev_ftype && prev_ftype->type != ftype->type)
1266 nfields += nested_nfields;
1268 if (!(!ftype->byref && (ftype->type == MONO_TYPE_R4 || ftype->type == MONO_TYPE_R8)))
1270 if (prev_ftype && prev_ftype->type != ftype->type)
1276 if (nfields == 0 || nfields > 4)
1278 *out_nfields = nfields;
1279 *out_esize = prev_ftype->type == MONO_TYPE_R4 ? 4 : 8;
1284 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1286 guint i, gr, fpr, pstart;
1288 int n = sig->hasthis + sig->param_count;
1292 guint32 stack_size = 0;
1294 gboolean is_pinvoke = sig->pinvoke;
1295 gboolean vtype_retaddr = FALSE;
1298 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1300 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1307 t = mini_get_underlying_type (sig->ret);
1318 case MONO_TYPE_FNPTR:
1319 case MONO_TYPE_CLASS:
1320 case MONO_TYPE_OBJECT:
1321 case MONO_TYPE_SZARRAY:
1322 case MONO_TYPE_ARRAY:
1323 case MONO_TYPE_STRING:
1324 cinfo->ret.storage = RegTypeGeneral;
1325 cinfo->ret.reg = ARMREG_R0;
1329 cinfo->ret.storage = RegTypeIRegPair;
1330 cinfo->ret.reg = ARMREG_R0;
1334 cinfo->ret.storage = RegTypeFP;
1336 if (t->type == MONO_TYPE_R4)
1337 cinfo->ret.size = 4;
1339 cinfo->ret.size = 8;
1341 if (IS_HARD_FLOAT) {
1342 cinfo->ret.reg = ARM_VFP_F0;
1344 cinfo->ret.reg = ARMREG_R0;
1347 case MONO_TYPE_GENERICINST:
1348 if (!mono_type_generic_inst_is_valuetype (t)) {
1349 cinfo->ret.storage = RegTypeGeneral;
1350 cinfo->ret.reg = ARMREG_R0;
1353 if (mini_is_gsharedvt_variable_type (t)) {
1354 cinfo->ret.storage = RegTypeStructByAddr;
1358 case MONO_TYPE_VALUETYPE:
1359 case MONO_TYPE_TYPEDBYREF:
1360 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1361 cinfo->ret.storage = RegTypeHFA;
1363 cinfo->ret.nregs = nfields;
1364 cinfo->ret.esize = esize;
1367 int native_size = mono_class_native_size (mono_class_from_mono_type (t), &align);
1370 #ifdef TARGET_WATCHOS
1375 if (native_size <= max_size) {
1376 cinfo->ret.storage = RegTypeStructByVal;
1377 cinfo->ret.struct_size = native_size;
1378 cinfo->ret.nregs = ALIGN_TO (native_size, 4) / 4;
1380 cinfo->ret.storage = RegTypeStructByAddr;
1383 cinfo->ret.storage = RegTypeStructByAddr;
1388 case MONO_TYPE_MVAR:
1389 g_assert (mini_is_gsharedvt_type (t));
1390 cinfo->ret.storage = RegTypeStructByAddr;
1392 case MONO_TYPE_VOID:
1395 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1398 vtype_retaddr = cinfo->ret.storage == RegTypeStructByAddr;
1403 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1404 * the first argument, allowing 'this' to be always passed in the first arg reg.
1405 * Also do this if the first argument is a reference type, since virtual calls
1406 * are sometimes made using calli without sig->hasthis set, like in the delegate
1409 if (vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1411 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1413 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0], TRUE);
1417 cinfo->ret.reg = gr;
1419 cinfo->vret_arg_index = 1;
1423 add_general (&gr, &stack_size, cinfo->args + 0, TRUE);
1426 if (vtype_retaddr) {
1427 cinfo->ret.reg = gr;
1432 DEBUG(g_print("params: %d\n", sig->param_count));
1433 for (i = pstart; i < sig->param_count; ++i) {
1434 ArgInfo *ainfo = &cinfo->args [n];
1436 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1437 /* Prevent implicit arguments and sig_cookie from
1438 being passed in registers */
1441 /* Emit the signature cookie just before the implicit arguments */
1442 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1444 DEBUG(g_print("param %d: ", i));
1445 if (sig->params [i]->byref) {
1446 DEBUG(g_print("byref\n"));
1447 add_general (&gr, &stack_size, ainfo, TRUE);
1451 t = mini_get_underlying_type (sig->params [i]);
1455 cinfo->args [n].size = 1;
1456 add_general (&gr, &stack_size, ainfo, TRUE);
1460 cinfo->args [n].size = 2;
1461 add_general (&gr, &stack_size, ainfo, TRUE);
1465 cinfo->args [n].size = 4;
1466 add_general (&gr, &stack_size, ainfo, TRUE);
1471 case MONO_TYPE_FNPTR:
1472 case MONO_TYPE_CLASS:
1473 case MONO_TYPE_OBJECT:
1474 case MONO_TYPE_STRING:
1475 case MONO_TYPE_SZARRAY:
1476 case MONO_TYPE_ARRAY:
1477 cinfo->args [n].size = sizeof (gpointer);
1478 add_general (&gr, &stack_size, ainfo, TRUE);
1480 case MONO_TYPE_GENERICINST:
1481 if (!mono_type_generic_inst_is_valuetype (t)) {
1482 cinfo->args [n].size = sizeof (gpointer);
1483 add_general (&gr, &stack_size, ainfo, TRUE);
1486 if (mini_is_gsharedvt_variable_type (t)) {
1487 /* gsharedvt arguments are passed by ref */
1488 g_assert (mini_is_gsharedvt_type (t));
1489 add_general (&gr, &stack_size, ainfo, TRUE);
1490 switch (ainfo->storage) {
1491 case RegTypeGeneral:
1492 ainfo->storage = RegTypeGSharedVtInReg;
1495 ainfo->storage = RegTypeGSharedVtOnStack;
1498 g_assert_not_reached ();
1503 case MONO_TYPE_TYPEDBYREF:
1504 case MONO_TYPE_VALUETYPE: {
1507 int nwords, nfields, esize;
1510 if (IS_HARD_FLOAT && sig->pinvoke && is_hfa (t, &nfields, &esize)) {
1511 if (fpr + nfields < ARM_VFP_F16) {
1512 ainfo->storage = RegTypeHFA;
1514 ainfo->nregs = nfields;
1515 ainfo->esize = esize;
1526 if (t->type == MONO_TYPE_TYPEDBYREF) {
1527 size = sizeof (MonoTypedRef);
1528 align = sizeof (gpointer);
1530 MonoClass *klass = mono_class_from_mono_type (sig->params [i]);
1532 size = mono_class_native_size (klass, &align);
1534 size = mini_type_stack_size_full (t, &align, FALSE);
1536 DEBUG(g_print ("load %d bytes struct\n", size));
1538 #ifdef TARGET_WATCHOS
1539 /* Watchos pass large structures by ref */
1540 /* We only do this for pinvoke to make gsharedvt/dyncall simpler */
1541 if (sig->pinvoke && size > 16) {
1542 add_general (&gr, &stack_size, ainfo, TRUE);
1543 switch (ainfo->storage) {
1544 case RegTypeGeneral:
1545 ainfo->storage = RegTypeStructByAddr;
1548 ainfo->storage = RegTypeStructByAddrOnStack;
1551 g_assert_not_reached ();
1560 align_size += (sizeof (gpointer) - 1);
1561 align_size &= ~(sizeof (gpointer) - 1);
1562 nwords = (align_size + sizeof (gpointer) -1 ) / sizeof (gpointer);
1563 ainfo->storage = RegTypeStructByVal;
1564 ainfo->struct_size = size;
1565 /* FIXME: align stack_size if needed */
1566 if (eabi_supported) {
1567 if (align >= 8 && (gr & 1))
1570 if (gr > ARMREG_R3) {
1572 ainfo->vtsize = nwords;
1574 int rest = ARMREG_R3 - gr + 1;
1575 int n_in_regs = rest >= nwords? nwords: rest;
1577 ainfo->size = n_in_regs;
1578 ainfo->vtsize = nwords - n_in_regs;
1581 nwords -= n_in_regs;
1583 if (sig->call_convention == MONO_CALL_VARARG)
1584 /* This matches the alignment in mono_ArgIterator_IntGetNextArg () */
1585 stack_size = ALIGN_TO (stack_size, align);
1586 ainfo->offset = stack_size;
1587 /*g_print ("offset for arg %d at %d\n", n, stack_size);*/
1588 stack_size += nwords * sizeof (gpointer);
1594 add_general (&gr, &stack_size, ainfo, FALSE);
1600 add_float (&fpr, &stack_size, ainfo, FALSE, &float_spare);
1602 add_general (&gr, &stack_size, ainfo, TRUE);
1608 add_float (&fpr, &stack_size, ainfo, TRUE, &float_spare);
1610 add_general (&gr, &stack_size, ainfo, FALSE);
1613 case MONO_TYPE_MVAR:
1614 /* gsharedvt arguments are passed by ref */
1615 g_assert (mini_is_gsharedvt_type (t));
1616 add_general (&gr, &stack_size, ainfo, TRUE);
1617 switch (ainfo->storage) {
1618 case RegTypeGeneral:
1619 ainfo->storage = RegTypeGSharedVtInReg;
1622 ainfo->storage = RegTypeGSharedVtOnStack;
1625 g_assert_not_reached ();
1629 g_error ("Can't handle 0x%x", sig->params [i]->type);
1634 /* Handle the case where there are no implicit arguments */
1635 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1636 /* Prevent implicit arguments and sig_cookie from
1637 being passed in registers */
1640 /* Emit the signature cookie just before the implicit arguments */
1641 add_general (&gr, &stack_size, &cinfo->sig_cookie, TRUE);
1644 /* align stack size to 8 */
1645 DEBUG (g_print (" stack size: %d (%d)\n", (stack_size + 15) & ~15, stack_size));
1646 stack_size = (stack_size + 7) & ~7;
1648 cinfo->stack_usage = stack_size;
1654 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1656 MonoType *callee_ret;
1660 c1 = get_call_info (NULL, caller_sig);
1661 c2 = get_call_info (NULL, callee_sig);
1664 * Tail calls with more callee stack usage than the caller cannot be supported, since
1665 * the extra stack space would be left on the stack after the tail call.
1667 res = c1->stack_usage >= c2->stack_usage;
1668 callee_ret = mini_get_underlying_type (callee_sig->ret);
1669 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != RegTypeStructByVal)
1670 /* An address on the callee's stack is passed as the first argument */
1673 if (c2->stack_usage > 16 * 4)
1685 debug_omit_fp (void)
1688 return mono_debug_count ();
1695 * mono_arch_compute_omit_fp:
1697 * Determine whenever the frame pointer can be eliminated.
1700 mono_arch_compute_omit_fp (MonoCompile *cfg)
1702 MonoMethodSignature *sig;
1703 MonoMethodHeader *header;
1707 if (cfg->arch.omit_fp_computed)
1710 header = cfg->header;
1712 sig = mono_method_signature (cfg->method);
1714 if (!cfg->arch.cinfo)
1715 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1716 cinfo = cfg->arch.cinfo;
1719 * FIXME: Remove some of the restrictions.
1721 cfg->arch.omit_fp = TRUE;
1722 cfg->arch.omit_fp_computed = TRUE;
1724 if (cfg->disable_omit_fp)
1725 cfg->arch.omit_fp = FALSE;
1726 if (!debug_omit_fp ())
1727 cfg->arch.omit_fp = FALSE;
1729 if (cfg->method->save_lmf)
1730 cfg->arch.omit_fp = FALSE;
1732 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1733 cfg->arch.omit_fp = FALSE;
1734 if (header->num_clauses)
1735 cfg->arch.omit_fp = FALSE;
1736 if (cfg->param_area)
1737 cfg->arch.omit_fp = FALSE;
1738 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1739 cfg->arch.omit_fp = FALSE;
1740 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1741 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1742 cfg->arch.omit_fp = FALSE;
1743 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1744 ArgInfo *ainfo = &cinfo->args [i];
1746 if (ainfo->storage == RegTypeBase || ainfo->storage == RegTypeBaseGen || ainfo->storage == RegTypeStructByVal) {
1748 * The stack offset can only be determined when the frame
1751 cfg->arch.omit_fp = FALSE;
1756 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1757 MonoInst *ins = cfg->varinfo [i];
1760 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1765 * Set var information according to the calling convention. arm version.
1766 * The locals var stuff should most likely be split in another method.
1769 mono_arch_allocate_vars (MonoCompile *cfg)
1771 MonoMethodSignature *sig;
1772 MonoMethodHeader *header;
1775 int i, offset, size, align, curinst;
1780 sig = mono_method_signature (cfg->method);
1782 if (!cfg->arch.cinfo)
1783 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1784 cinfo = cfg->arch.cinfo;
1785 sig_ret = mini_get_underlying_type (sig->ret);
1787 mono_arch_compute_omit_fp (cfg);
1789 if (cfg->arch.omit_fp)
1790 cfg->frame_reg = ARMREG_SP;
1792 cfg->frame_reg = ARMREG_FP;
1794 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1796 /* allow room for the vararg method args: void* and long/double */
1797 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1798 cfg->param_area = MAX (cfg->param_area, sizeof (gpointer)*8);
1800 header = cfg->header;
1802 /* See mono_arch_get_global_int_regs () */
1803 if (cfg->flags & MONO_CFG_HAS_CALLS)
1804 cfg->uses_rgctx_reg = TRUE;
1806 if (cfg->frame_reg != ARMREG_SP)
1807 cfg->used_int_regs |= 1 << cfg->frame_reg;
1809 if (cfg->compile_aot || cfg->uses_rgctx_reg || COMPILE_LLVM (cfg))
1810 /* V5 is reserved for passing the vtable/rgctx/IMT method */
1811 cfg->used_int_regs |= (1 << MONO_ARCH_IMT_REG);
1815 if (!MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage != RegTypeStructByAddr) {
1816 if (sig_ret->type != MONO_TYPE_VOID) {
1817 cfg->ret->opcode = OP_REGVAR;
1818 cfg->ret->inst_c0 = ARMREG_R0;
1821 /* local vars are at a positive offset from the stack pointer */
1823 * also note that if the function uses alloca, we use FP
1824 * to point at the local variables.
1826 offset = 0; /* linkage area */
1827 /* align the offset to 16 bytes: not sure this is needed here */
1829 //offset &= ~(8 - 1);
1831 /* add parameter area size for called functions */
1832 offset += cfg->param_area;
1835 if (cfg->flags & MONO_CFG_HAS_FPOUT)
1838 /* allow room to save the return value */
1839 if (mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method))
1842 switch (cinfo->ret.storage) {
1843 case RegTypeStructByVal:
1845 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1846 offset = ALIGN_TO (offset, 8);
1847 cfg->ret->opcode = OP_REGOFFSET;
1848 cfg->ret->inst_basereg = cfg->frame_reg;
1849 cfg->ret->inst_offset = offset;
1850 if (cinfo->ret.storage == RegTypeStructByVal)
1851 offset += cinfo->ret.nregs * sizeof (gpointer);
1855 case RegTypeStructByAddr:
1856 ins = cfg->vret_addr;
1857 offset += sizeof(gpointer) - 1;
1858 offset &= ~(sizeof(gpointer) - 1);
1859 ins->inst_offset = offset;
1860 ins->opcode = OP_REGOFFSET;
1861 ins->inst_basereg = cfg->frame_reg;
1862 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1863 g_print ("vret_addr =");
1864 mono_print_ins (cfg->vret_addr);
1866 offset += sizeof(gpointer);
1872 /* Allocate these first so they have a small offset, OP_SEQ_POINT depends on this */
1873 if (cfg->arch.seq_point_info_var) {
1876 ins = cfg->arch.seq_point_info_var;
1880 offset += align - 1;
1881 offset &= ~(align - 1);
1882 ins->opcode = OP_REGOFFSET;
1883 ins->inst_basereg = cfg->frame_reg;
1884 ins->inst_offset = offset;
1887 ins = cfg->arch.ss_trigger_page_var;
1890 offset += align - 1;
1891 offset &= ~(align - 1);
1892 ins->opcode = OP_REGOFFSET;
1893 ins->inst_basereg = cfg->frame_reg;
1894 ins->inst_offset = offset;
1898 if (cfg->arch.seq_point_ss_method_var) {
1901 ins = cfg->arch.seq_point_ss_method_var;
1904 offset += align - 1;
1905 offset &= ~(align - 1);
1906 ins->opcode = OP_REGOFFSET;
1907 ins->inst_basereg = cfg->frame_reg;
1908 ins->inst_offset = offset;
1911 ins = cfg->arch.seq_point_bp_method_var;
1914 offset += align - 1;
1915 offset &= ~(align - 1);
1916 ins->opcode = OP_REGOFFSET;
1917 ins->inst_basereg = cfg->frame_reg;
1918 ins->inst_offset = offset;
1922 if (cfg->has_atomic_exchange_i4 || cfg->has_atomic_cas_i4 || cfg->has_atomic_add_i4) {
1923 /* Allocate a temporary used by the atomic ops */
1927 /* Allocate a local slot to hold the sig cookie address */
1928 offset += align - 1;
1929 offset &= ~(align - 1);
1930 cfg->arch.atomic_tmp_offset = offset;
1933 cfg->arch.atomic_tmp_offset = -1;
1936 cfg->locals_min_stack_offset = offset;
1938 curinst = cfg->locals_start;
1939 for (i = curinst; i < cfg->num_varinfo; ++i) {
1942 ins = cfg->varinfo [i];
1943 if ((ins->flags & MONO_INST_IS_DEAD) || ins->opcode == OP_REGVAR || ins->opcode == OP_REGOFFSET)
1946 t = ins->inst_vtype;
1947 if (cfg->gsharedvt && mini_is_gsharedvt_variable_type (t))
1950 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
1951 * pinvoke wrappers when they call functions returning structure */
1952 if (ins->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (t) && t->type != MONO_TYPE_TYPEDBYREF) {
1953 size = mono_class_native_size (mono_class_from_mono_type (t), &ualign);
1957 size = mono_type_size (t, &align);
1959 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
1960 * since it loads/stores misaligned words, which don't do the right thing.
1962 if (align < 4 && size >= 4)
1964 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
1965 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
1966 offset += align - 1;
1967 offset &= ~(align - 1);
1968 ins->opcode = OP_REGOFFSET;
1969 ins->inst_offset = offset;
1970 ins->inst_basereg = cfg->frame_reg;
1972 //g_print ("allocating local %d to %d\n", i, inst->inst_offset);
1975 cfg->locals_max_stack_offset = offset;
1979 ins = cfg->args [curinst];
1980 if (ins->opcode != OP_REGVAR) {
1981 ins->opcode = OP_REGOFFSET;
1982 ins->inst_basereg = cfg->frame_reg;
1983 offset += sizeof (gpointer) - 1;
1984 offset &= ~(sizeof (gpointer) - 1);
1985 ins->inst_offset = offset;
1986 offset += sizeof (gpointer);
1991 if (sig->call_convention == MONO_CALL_VARARG) {
1995 /* Allocate a local slot to hold the sig cookie address */
1996 offset += align - 1;
1997 offset &= ~(align - 1);
1998 cfg->sig_cookie = offset;
2002 for (i = 0; i < sig->param_count; ++i) {
2003 ainfo = cinfo->args + i;
2005 ins = cfg->args [curinst];
2007 switch (ainfo->storage) {
2009 offset = ALIGN_TO (offset, 8);
2010 ins->opcode = OP_REGOFFSET;
2011 ins->inst_basereg = cfg->frame_reg;
2012 /* These arguments are saved to the stack in the prolog */
2013 ins->inst_offset = offset;
2014 if (cfg->verbose_level >= 2)
2015 g_print ("arg %d allocated to %s+0x%0x.\n", i, mono_arch_regname (ins->inst_basereg), (int)ins->inst_offset);
2023 if (ins->opcode != OP_REGVAR) {
2024 ins->opcode = OP_REGOFFSET;
2025 ins->inst_basereg = cfg->frame_reg;
2026 size = mini_type_stack_size_full (sig->params [i], &ualign, sig->pinvoke);
2028 /* FIXME: if a structure is misaligned, our memcpy doesn't work,
2029 * since it loads/stores misaligned words, which don't do the right thing.
2031 if (align < 4 && size >= 4)
2033 /* The code in the prolog () stores words when storing vtypes received in a register */
2034 if (MONO_TYPE_ISSTRUCT (sig->params [i]))
2036 if (ALIGN_TO (offset, align) > ALIGN_TO (offset, 4))
2037 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2038 offset += align - 1;
2039 offset &= ~(align - 1);
2040 ins->inst_offset = offset;
2046 /* align the offset to 8 bytes */
2047 if (ALIGN_TO (offset, 8) > ALIGN_TO (offset, 4))
2048 mini_gc_set_slot_type_from_fp (cfg, ALIGN_TO (offset, 4), SLOT_NOREF);
2053 cfg->stack_offset = offset;
2057 mono_arch_create_vars (MonoCompile *cfg)
2059 MonoMethodSignature *sig;
2063 sig = mono_method_signature (cfg->method);
2065 if (!cfg->arch.cinfo)
2066 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2067 cinfo = cfg->arch.cinfo;
2069 if (IS_HARD_FLOAT) {
2070 for (i = 0; i < 2; i++) {
2071 MonoInst *inst = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
2072 inst->flags |= MONO_INST_VOLATILE;
2074 cfg->arch.vfp_scratch_slots [i] = (gpointer) inst;
2078 if (cinfo->ret.storage == RegTypeStructByVal)
2079 cfg->ret_var_is_local = TRUE;
2081 if (cinfo->ret.storage == RegTypeStructByAddr) {
2082 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2083 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2084 g_print ("vret_addr = ");
2085 mono_print_ins (cfg->vret_addr);
2089 if (cfg->gen_sdb_seq_points) {
2090 if (cfg->soft_breakpoints) {
2093 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2094 ins->flags |= MONO_INST_VOLATILE;
2095 cfg->arch.seq_point_ss_method_var = ins;
2097 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2098 ins->flags |= MONO_INST_VOLATILE;
2099 cfg->arch.seq_point_bp_method_var = ins;
2101 g_assert (!cfg->compile_aot);
2102 } else if (cfg->compile_aot) {
2103 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2104 ins->flags |= MONO_INST_VOLATILE;
2105 cfg->arch.seq_point_info_var = ins;
2107 /* Allocate a separate variable for this to save 1 load per seq point */
2108 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2109 ins->flags |= MONO_INST_VOLATILE;
2110 cfg->arch.ss_trigger_page_var = ins;
2116 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2118 MonoMethodSignature *tmp_sig;
2121 if (call->tail_call)
2124 g_assert (cinfo->sig_cookie.storage == RegTypeBase);
2127 * mono_ArgIterator_Setup assumes the signature cookie is
2128 * passed first and all the arguments which were before it are
2129 * passed on the stack after the signature. So compensate by
2130 * passing a different signature.
2132 tmp_sig = mono_metadata_signature_dup (call->signature);
2133 tmp_sig->param_count -= call->signature->sentinelpos;
2134 tmp_sig->sentinelpos = 0;
2135 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2137 sig_reg = mono_alloc_ireg (cfg);
2138 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2140 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, cinfo->sig_cookie.offset, sig_reg);
2145 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2150 LLVMCallInfo *linfo;
2152 n = sig->param_count + sig->hasthis;
2154 cinfo = get_call_info (cfg->mempool, sig);
2156 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2159 * LLVM always uses the native ABI while we use our own ABI, the
2160 * only difference is the handling of vtypes:
2161 * - we only pass/receive them in registers in some cases, and only
2162 * in 1 or 2 integer registers.
2164 switch (cinfo->ret.storage) {
2165 case RegTypeGeneral:
2168 case RegTypeIRegPair:
2170 case RegTypeStructByAddr:
2171 /* Vtype returned using a hidden argument */
2172 linfo->ret.storage = LLVMArgVtypeRetAddr;
2173 linfo->vret_arg_index = cinfo->vret_arg_index;
2176 case RegTypeStructByVal:
2177 /* LLVM models this by returning an int array */
2178 linfo->ret.storage = LLVMArgAsIArgs;
2179 linfo->ret.nslots = cinfo->ret.nregs;
2183 cfg->exception_message = g_strdup_printf ("unknown ret conv (%d)", cinfo->ret.storage);
2184 cfg->disable_llvm = TRUE;
2188 for (i = 0; i < n; ++i) {
2189 LLVMArgInfo *lainfo = &linfo->args [i];
2190 ainfo = cinfo->args + i;
2192 lainfo->storage = LLVMArgNone;
2194 switch (ainfo->storage) {
2195 case RegTypeGeneral:
2196 case RegTypeIRegPair:
2198 case RegTypeBaseGen:
2200 lainfo->storage = LLVMArgNormal;
2202 case RegTypeStructByVal:
2203 lainfo->storage = LLVMArgAsIArgs;
2204 lainfo->nslots = ainfo->struct_size / sizeof (gpointer);
2206 case RegTypeStructByAddr:
2207 case RegTypeStructByAddrOnStack:
2208 lainfo->storage = LLVMArgVtypeByRef;
2211 cfg->exception_message = g_strdup_printf ("ainfo->storage (%d)", ainfo->storage);
2212 cfg->disable_llvm = TRUE;
2222 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2225 MonoMethodSignature *sig;
2229 sig = call->signature;
2230 n = sig->param_count + sig->hasthis;
2232 cinfo = get_call_info (cfg->mempool, sig);
2234 switch (cinfo->ret.storage) {
2235 case RegTypeStructByVal:
2237 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
2238 /* The JIT will transform this into a normal call */
2239 call->vret_in_reg = TRUE;
2242 if (call->inst.opcode == OP_TAILCALL)
2245 * The vtype is returned in registers, save the return area address in a local, and save the vtype into
2246 * the location pointed to by it after call in emit_move_return_value ().
2248 if (!cfg->arch.vret_addr_loc) {
2249 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2250 /* Prevent it from being register allocated or optimized away */
2251 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2254 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2256 case RegTypeStructByAddr: {
2258 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2259 vtarg->sreg1 = call->vret_var->dreg;
2260 vtarg->dreg = mono_alloc_preg (cfg);
2261 MONO_ADD_INS (cfg->cbb, vtarg);
2263 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2270 for (i = 0; i < n; ++i) {
2271 ArgInfo *ainfo = cinfo->args + i;
2274 if (i >= sig->hasthis)
2275 t = sig->params [i - sig->hasthis];
2277 t = &mono_defaults.int_class->byval_arg;
2278 t = mini_get_underlying_type (t);
2280 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2281 /* Emit the signature cookie just before the implicit arguments */
2282 emit_sig_cookie (cfg, call, cinfo);
2285 in = call->args [i];
2287 switch (ainfo->storage) {
2288 case RegTypeGeneral:
2289 case RegTypeIRegPair:
2290 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2291 MONO_INST_NEW (cfg, ins, OP_MOVE);
2292 ins->dreg = mono_alloc_ireg (cfg);
2293 ins->sreg1 = MONO_LVREG_LS (in->dreg);
2294 MONO_ADD_INS (cfg->cbb, ins);
2295 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2297 MONO_INST_NEW (cfg, ins, OP_MOVE);
2298 ins->dreg = mono_alloc_ireg (cfg);
2299 ins->sreg1 = MONO_LVREG_MS (in->dreg);
2300 MONO_ADD_INS (cfg->cbb, ins);
2301 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2302 } else if (!t->byref && ((t->type == MONO_TYPE_R8) || (t->type == MONO_TYPE_R4))) {
2303 if (ainfo->size == 4) {
2304 if (IS_SOFT_FLOAT) {
2305 /* mono_emit_call_args () have already done the r8->r4 conversion */
2306 /* The converted value is in an int vreg */
2307 MONO_INST_NEW (cfg, ins, OP_MOVE);
2308 ins->dreg = mono_alloc_ireg (cfg);
2309 ins->sreg1 = in->dreg;
2310 MONO_ADD_INS (cfg->cbb, ins);
2311 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2315 cfg->param_area = MAX (cfg->param_area, 8);
2316 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2317 creg = mono_alloc_ireg (cfg);
2318 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2319 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2322 if (IS_SOFT_FLOAT) {
2323 MONO_INST_NEW (cfg, ins, OP_FGETLOW32);
2324 ins->dreg = mono_alloc_ireg (cfg);
2325 ins->sreg1 = in->dreg;
2326 MONO_ADD_INS (cfg->cbb, ins);
2327 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2329 MONO_INST_NEW (cfg, ins, OP_FGETHIGH32);
2330 ins->dreg = mono_alloc_ireg (cfg);
2331 ins->sreg1 = in->dreg;
2332 MONO_ADD_INS (cfg->cbb, ins);
2333 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg + 1, FALSE);
2337 cfg->param_area = MAX (cfg->param_area, 8);
2338 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2339 creg = mono_alloc_ireg (cfg);
2340 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2341 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg, FALSE);
2342 creg = mono_alloc_ireg (cfg);
2343 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8 + 4));
2344 mono_call_inst_add_outarg_reg (cfg, call, creg, ainfo->reg + 1, FALSE);
2347 cfg->flags |= MONO_CFG_HAS_FPOUT;
2349 MONO_INST_NEW (cfg, ins, OP_MOVE);
2350 ins->dreg = mono_alloc_ireg (cfg);
2351 ins->sreg1 = in->dreg;
2352 MONO_ADD_INS (cfg->cbb, ins);
2354 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, FALSE);
2357 case RegTypeStructByVal:
2358 case RegTypeGSharedVtInReg:
2359 case RegTypeGSharedVtOnStack:
2361 case RegTypeStructByAddr:
2362 case RegTypeStructByAddrOnStack:
2363 MONO_INST_NEW (cfg, ins, OP_OUTARG_VT);
2364 ins->opcode = OP_OUTARG_VT;
2365 ins->sreg1 = in->dreg;
2366 ins->klass = in->klass;
2367 ins->inst_p0 = call;
2368 ins->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2369 memcpy (ins->inst_p1, ainfo, sizeof (ArgInfo));
2370 mono_call_inst_add_outarg_vt (cfg, call, ins);
2371 MONO_ADD_INS (cfg->cbb, ins);
2374 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2375 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2376 } else if (!t->byref && ((t->type == MONO_TYPE_R4) || (t->type == MONO_TYPE_R8))) {
2377 if (t->type == MONO_TYPE_R8) {
2378 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2381 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2383 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2386 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, in->dreg);
2389 case RegTypeBaseGen:
2390 if (!t->byref && ((t->type == MONO_TYPE_I8) || (t->type == MONO_TYPE_U8))) {
2391 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, (G_BYTE_ORDER == G_BIG_ENDIAN) ? MONO_LVREG_LS (in->dreg) : MONO_LVREG_MS (in->dreg));
2392 MONO_INST_NEW (cfg, ins, OP_MOVE);
2393 ins->dreg = mono_alloc_ireg (cfg);
2394 ins->sreg1 = G_BYTE_ORDER == G_BIG_ENDIAN ? MONO_LVREG_MS (in->dreg) : MONO_LVREG_LS (in->dreg);
2395 MONO_ADD_INS (cfg->cbb, ins);
2396 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ARMREG_R3, FALSE);
2397 } else if (!t->byref && (t->type == MONO_TYPE_R8)) {
2400 /* This should work for soft-float as well */
2402 cfg->param_area = MAX (cfg->param_area, 8);
2403 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, ARMREG_SP, (cfg->param_area - 8), in->dreg);
2404 creg = mono_alloc_ireg (cfg);
2405 mono_call_inst_add_outarg_reg (cfg, call, creg, ARMREG_R3, FALSE);
2406 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 8));
2407 creg = mono_alloc_ireg (cfg);
2408 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOAD_MEMBASE, creg, ARMREG_SP, (cfg->param_area - 4));
2409 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, creg);
2410 cfg->flags |= MONO_CFG_HAS_FPOUT;
2412 g_assert_not_reached ();
2416 int fdreg = mono_alloc_freg (cfg);
2418 if (ainfo->size == 8) {
2419 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2420 ins->sreg1 = in->dreg;
2422 MONO_ADD_INS (cfg->cbb, ins);
2424 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, ainfo->reg, TRUE);
2429 * Mono's register allocator doesn't speak single-precision registers that
2430 * overlap double-precision registers (i.e. armhf). So we have to work around
2431 * the register allocator and load the value from memory manually.
2433 * So we create a variable for the float argument and an instruction to store
2434 * the argument into the variable. We then store the list of these arguments
2435 * in call->float_args. This list is then used by emit_float_args later to
2436 * pass the arguments in the various call opcodes.
2438 * This is not very nice, and we should really try to fix the allocator.
2441 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2443 /* Make sure the instruction isn't seen as pointless and removed.
2445 float_arg->flags |= MONO_INST_VOLATILE;
2447 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, in->dreg);
2449 /* We use the dreg to look up the instruction later. The hreg is used to
2450 * emit the instruction that loads the value into the FP reg.
2452 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2453 fad->vreg = float_arg->dreg;
2454 fad->hreg = ainfo->reg;
2456 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2459 call->used_iregs |= 1 << ainfo->reg;
2460 cfg->flags |= MONO_CFG_HAS_FPOUT;
2464 g_assert_not_reached ();
2468 /* Handle the case where there are no implicit arguments */
2469 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2470 emit_sig_cookie (cfg, call, cinfo);
2472 call->call_info = cinfo;
2473 call->stack_usage = cinfo->stack_usage;
2477 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *arg)
2483 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2484 ins->dreg = mono_alloc_freg (cfg);
2485 ins->sreg1 = arg->dreg;
2486 MONO_ADD_INS (cfg->cbb, ins);
2487 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2490 g_assert_not_reached ();
2496 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2498 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2500 ArgInfo *ainfo = ins->inst_p1;
2501 int ovf_size = ainfo->vtsize;
2502 int doffset = ainfo->offset;
2503 int struct_size = ainfo->struct_size;
2504 int i, soffset, dreg, tmpreg;
2506 switch (ainfo->storage) {
2507 case RegTypeGSharedVtInReg:
2508 case RegTypeStructByAddr:
2510 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2512 case RegTypeGSharedVtOnStack:
2513 case RegTypeStructByAddrOnStack:
2514 /* Pass by addr on stack */
2515 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, ARMREG_SP, ainfo->offset, src->dreg);
2518 for (i = 0; i < ainfo->nregs; ++i) {
2519 if (ainfo->esize == 4)
2520 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
2522 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
2523 load->dreg = mono_alloc_freg (cfg);
2524 load->inst_basereg = src->dreg;
2525 load->inst_offset = i * ainfo->esize;
2526 MONO_ADD_INS (cfg->cbb, load);
2528 if (ainfo->esize == 4) {
2531 /* See RegTypeFP in mono_arch_emit_call () */
2532 MonoInst *float_arg = mono_compile_create_var (cfg, &mono_defaults.single_class->byval_arg, OP_LOCAL);
2533 float_arg->flags |= MONO_INST_VOLATILE;
2534 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, float_arg->dreg, load->dreg);
2536 fad = mono_mempool_alloc0 (cfg->mempool, sizeof (FloatArgData));
2537 fad->vreg = float_arg->dreg;
2538 fad->hreg = ainfo->reg + i;
2540 call->float_args = g_slist_append_mempool (cfg->mempool, call->float_args, fad);
2542 add_outarg_reg (cfg, call, RegTypeFP, ainfo->reg + (i * 2), load);
2548 for (i = 0; i < ainfo->size; ++i) {
2549 dreg = mono_alloc_ireg (cfg);
2550 switch (struct_size) {
2552 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2555 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, soffset);
2558 tmpreg = mono_alloc_ireg (cfg);
2559 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, soffset);
2560 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 1);
2561 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 8);
2562 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2563 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, tmpreg, src->dreg, soffset + 2);
2564 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SHL_IMM, tmpreg, tmpreg, 16);
2565 MONO_EMIT_NEW_BIALU (cfg, OP_IOR, dreg, dreg, tmpreg);
2568 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, soffset);
2571 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg + i, FALSE);
2572 soffset += sizeof (gpointer);
2573 struct_size -= sizeof (gpointer);
2575 //g_print ("vt size: %d at R%d + %d\n", doffset, vt->inst_basereg, vt->inst_offset);
2577 mini_emit_memcpy (cfg, ARMREG_SP, doffset, src->dreg, soffset, MIN (ovf_size * sizeof (gpointer), struct_size), struct_size < 4 ? 1 : 4);
2583 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2585 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2588 if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
2591 if (COMPILE_LLVM (cfg)) {
2592 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2594 MONO_INST_NEW (cfg, ins, OP_SETLRET);
2595 ins->sreg1 = MONO_LVREG_LS (val->dreg);
2596 ins->sreg2 = MONO_LVREG_MS (val->dreg);
2597 MONO_ADD_INS (cfg->cbb, ins);
2602 case MONO_ARM_FPU_NONE:
2603 if (ret->type == MONO_TYPE_R8) {
2606 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2607 ins->dreg = cfg->ret->dreg;
2608 ins->sreg1 = val->dreg;
2609 MONO_ADD_INS (cfg->cbb, ins);
2612 if (ret->type == MONO_TYPE_R4) {
2613 /* Already converted to an int in method_to_ir () */
2614 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2618 case MONO_ARM_FPU_VFP:
2619 case MONO_ARM_FPU_VFP_HARD:
2620 if (ret->type == MONO_TYPE_R8 || ret->type == MONO_TYPE_R4) {
2623 MONO_INST_NEW (cfg, ins, OP_SETFRET);
2624 ins->dreg = cfg->ret->dreg;
2625 ins->sreg1 = val->dreg;
2626 MONO_ADD_INS (cfg->cbb, ins);
2631 g_assert_not_reached ();
2635 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2638 #endif /* #ifndef DISABLE_JIT */
2641 mono_arch_is_inst_imm (gint64 imm)
2647 MonoMethodSignature *sig;
2650 MonoType **param_types;
2654 dyn_call_supported (CallInfo *cinfo, MonoMethodSignature *sig)
2658 if (sig->hasthis + sig->param_count > PARAM_REGS + DYN_CALL_STACK_ARGS)
2661 switch (cinfo->ret.storage) {
2663 case RegTypeGeneral:
2664 case RegTypeIRegPair:
2665 case RegTypeStructByAddr:
2676 for (i = 0; i < cinfo->nargs; ++i) {
2677 ArgInfo *ainfo = &cinfo->args [i];
2680 switch (ainfo->storage) {
2681 case RegTypeGeneral:
2682 case RegTypeIRegPair:
2683 case RegTypeBaseGen:
2687 if (ainfo->offset >= (DYN_CALL_STACK_ARGS * sizeof (gpointer)))
2690 case RegTypeStructByVal:
2691 if (ainfo->size == 0)
2692 last_slot = PARAM_REGS + (ainfo->offset / 4) + ainfo->vtsize;
2694 last_slot = ainfo->reg + ainfo->size + ainfo->vtsize;
2695 if (last_slot >= PARAM_REGS + DYN_CALL_STACK_ARGS)
2703 // FIXME: Can't use cinfo only as it doesn't contain info about I8/float */
2704 for (i = 0; i < sig->param_count; ++i) {
2705 MonoType *t = sig->params [i];
2710 t = mini_get_underlying_type (t);
2733 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2735 ArchDynCallInfo *info;
2739 cinfo = get_call_info (NULL, sig);
2741 if (!dyn_call_supported (cinfo, sig)) {
2746 info = g_new0 (ArchDynCallInfo, 1);
2747 // FIXME: Preprocess the info to speed up start_dyn_call ()
2749 info->cinfo = cinfo;
2750 info->rtype = mini_get_underlying_type (sig->ret);
2751 info->param_types = g_new0 (MonoType*, sig->param_count);
2752 for (i = 0; i < sig->param_count; ++i)
2753 info->param_types [i] = mini_get_underlying_type (sig->params [i]);
2755 return (MonoDynCallInfo*)info;
2759 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2761 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2763 g_free (ainfo->cinfo);
2768 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2770 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2771 DynCallArgs *p = (DynCallArgs*)buf;
2772 int arg_index, greg, i, j, pindex;
2773 MonoMethodSignature *sig = dinfo->sig;
2775 g_assert (buf_len >= sizeof (DynCallArgs));
2785 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2786 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2791 if (dinfo->cinfo->ret.storage == RegTypeStructByAddr)
2792 p->regs [greg ++] = (mgreg_t)ret;
2794 for (i = pindex; i < sig->param_count; i++) {
2795 MonoType *t = dinfo->param_types [i];
2796 gpointer *arg = args [arg_index ++];
2797 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2800 if (ainfo->storage == RegTypeGeneral || ainfo->storage == RegTypeIRegPair || ainfo->storage == RegTypeStructByVal) {
2802 } else if (ainfo->storage == RegTypeFP) {
2803 } else if (ainfo->storage == RegTypeBase) {
2804 slot = PARAM_REGS + (ainfo->offset / 4);
2805 } else if (ainfo->storage == RegTypeBaseGen) {
2806 /* slot + 1 is the first stack slot, so the code below will work */
2809 g_assert_not_reached ();
2813 p->regs [slot] = (mgreg_t)*arg;
2818 case MONO_TYPE_STRING:
2819 case MONO_TYPE_CLASS:
2820 case MONO_TYPE_ARRAY:
2821 case MONO_TYPE_SZARRAY:
2822 case MONO_TYPE_OBJECT:
2826 p->regs [slot] = (mgreg_t)*arg;
2829 p->regs [slot] = *(guint8*)arg;
2832 p->regs [slot] = *(gint8*)arg;
2835 p->regs [slot] = *(gint16*)arg;
2838 p->regs [slot] = *(guint16*)arg;
2841 p->regs [slot] = *(gint32*)arg;
2844 p->regs [slot] = *(guint32*)arg;
2848 p->regs [slot ++] = (mgreg_t)arg [0];
2849 p->regs [slot] = (mgreg_t)arg [1];
2852 if (ainfo->storage == RegTypeFP) {
2853 float f = *(float*)arg;
2854 p->fpregs [ainfo->reg / 2] = *(double*)&f;
2857 p->regs [slot] = *(mgreg_t*)arg;
2861 if (ainfo->storage == RegTypeFP) {
2862 p->fpregs [ainfo->reg / 2] = *(double*)arg;
2865 p->regs [slot ++] = (mgreg_t)arg [0];
2866 p->regs [slot] = (mgreg_t)arg [1];
2869 case MONO_TYPE_GENERICINST:
2870 if (MONO_TYPE_IS_REFERENCE (t)) {
2871 p->regs [slot] = (mgreg_t)*arg;
2874 if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2875 MonoClass *klass = mono_class_from_mono_type (t);
2876 guint8 *nullable_buf;
2879 size = mono_class_value_size (klass, NULL);
2880 nullable_buf = g_alloca (size);
2881 g_assert (nullable_buf);
2883 /* The argument pointed to by arg is either a boxed vtype or null */
2884 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2886 arg = (gpointer*)nullable_buf;
2892 case MONO_TYPE_VALUETYPE:
2893 g_assert (ainfo->storage == RegTypeStructByVal);
2895 if (ainfo->size == 0)
2896 slot = PARAM_REGS + (ainfo->offset / 4);
2900 for (j = 0; j < ainfo->size + ainfo->vtsize; ++j)
2901 p->regs [slot ++] = ((mgreg_t*)arg) [j];
2904 g_assert_not_reached ();
2910 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2912 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2913 DynCallArgs *p = (DynCallArgs*)buf;
2914 MonoType *ptype = ainfo->rtype;
2915 guint8 *ret = p->ret;
2916 mgreg_t res = p->res;
2917 mgreg_t res2 = p->res2;
2919 switch (ptype->type) {
2920 case MONO_TYPE_VOID:
2921 *(gpointer*)ret = NULL;
2923 case MONO_TYPE_STRING:
2924 case MONO_TYPE_CLASS:
2925 case MONO_TYPE_ARRAY:
2926 case MONO_TYPE_SZARRAY:
2927 case MONO_TYPE_OBJECT:
2931 *(gpointer*)ret = (gpointer)res;
2937 *(guint8*)ret = res;
2940 *(gint16*)ret = res;
2943 *(guint16*)ret = res;
2946 *(gint32*)ret = res;
2949 *(guint32*)ret = res;
2953 /* This handles endianness as well */
2954 ((gint32*)ret) [0] = res;
2955 ((gint32*)ret) [1] = res2;
2957 case MONO_TYPE_GENERICINST:
2958 if (MONO_TYPE_IS_REFERENCE (ptype)) {
2959 *(gpointer*)ret = (gpointer)res;
2964 case MONO_TYPE_VALUETYPE:
2965 g_assert (ainfo->cinfo->ret.storage == RegTypeStructByAddr);
2971 *(float*)ret = *(float*)&p->fpregs [0];
2973 *(float*)ret = *(float*)&res;
2975 case MONO_TYPE_R8: {
2979 if (IS_HARD_FLOAT) {
2980 *(double*)ret = p->fpregs [0];
2985 *(double*)ret = *(double*)®s;
2990 g_assert_not_reached ();
2997 * Allow tracing to work with this interface (with an optional argument)
3001 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3005 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3006 ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
3007 code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
3008 code = emit_call_reg (code, ARMREG_R2);
3022 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
3025 int save_mode = SAVE_NONE;
3027 MonoMethod *method = cfg->method;
3028 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
3029 int rtype = ret_type->type;
3030 int save_offset = cfg->param_area;
3034 offset = code - cfg->native_code;
3035 /* we need about 16 instructions */
3036 if (offset > (cfg->code_size - 16 * 4)) {
3037 cfg->code_size *= 2;
3038 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3039 code = cfg->native_code + offset;
3042 case MONO_TYPE_VOID:
3043 /* special case string .ctor icall */
3044 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3045 save_mode = SAVE_ONE;
3047 save_mode = SAVE_NONE;
3051 save_mode = SAVE_TWO;
3055 save_mode = SAVE_ONE_FP;
3057 save_mode = SAVE_ONE;
3061 save_mode = SAVE_TWO_FP;
3063 save_mode = SAVE_TWO;
3065 case MONO_TYPE_GENERICINST:
3066 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
3067 save_mode = SAVE_ONE;
3071 case MONO_TYPE_VALUETYPE:
3072 save_mode = SAVE_STRUCT;
3075 save_mode = SAVE_ONE;
3079 switch (save_mode) {
3081 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3082 ARM_STR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3083 if (enable_arguments) {
3084 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_R1);
3085 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3089 ARM_STR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3090 if (enable_arguments) {
3091 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3095 ARM_FSTS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3096 if (enable_arguments) {
3097 ARM_FMRS (code, ARMREG_R1, ARM_VFP_F0);
3101 ARM_FSTD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3102 if (enable_arguments) {
3103 ARM_FMDRR (code, ARMREG_R1, ARMREG_R2, ARM_VFP_D0);
3107 if (enable_arguments) {
3108 /* FIXME: get the actual address */
3109 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_R0);
3117 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
3118 code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
3119 code = emit_call_reg (code, ARMREG_IP);
3121 switch (save_mode) {
3123 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3124 ARM_LDR_IMM (code, ARMREG_R1, cfg->frame_reg, save_offset + 4);
3127 ARM_LDR_IMM (code, ARMREG_R0, cfg->frame_reg, save_offset);
3130 ARM_FLDS (code, ARM_VFP_F0, cfg->frame_reg, save_offset);
3133 ARM_FLDD (code, ARM_VFP_D0, cfg->frame_reg, save_offset);
3144 * The immediate field for cond branches is big enough for all reasonable methods
3146 #define EMIT_COND_BRANCH_FLAGS(ins,condcode) \
3147 if (0 && ins->inst_true_bb->native_offset) { \
3148 ARM_B_COND (code, (condcode), (code - cfg->native_code + ins->inst_true_bb->native_offset) & 0xffffff); \
3150 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
3151 ARM_B_COND (code, (condcode), 0); \
3154 #define EMIT_COND_BRANCH(ins,cond) EMIT_COND_BRANCH_FLAGS(ins, branch_cc_table [(cond)])
3156 /* emit an exception if condition is fail
3158 * We assign the extra code used to throw the implicit exceptions
3159 * to cfg->bb_exit as far as the big branch handling is concerned
3161 #define EMIT_COND_SYSTEM_EXCEPTION_FLAGS(condcode,exc_name) \
3163 mono_add_patch_info (cfg, code - cfg->native_code, \
3164 MONO_PATCH_INFO_EXC, exc_name); \
3165 ARM_BL_COND (code, (condcode), 0); \
3168 #define EMIT_COND_SYSTEM_EXCEPTION(cond,exc_name) EMIT_COND_SYSTEM_EXCEPTION_FLAGS(branch_cc_table [(cond)], (exc_name))
3171 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3176 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3180 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3181 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3183 switch (ins->opcode) {
3186 /* Already done by an arch-independent pass */
3188 case OP_LOAD_MEMBASE:
3189 case OP_LOADI4_MEMBASE:
3191 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3192 * OP_LOAD_MEMBASE offset(basereg), reg
3194 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
3195 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
3196 ins->inst_basereg == last_ins->inst_destbasereg &&
3197 ins->inst_offset == last_ins->inst_offset) {
3198 if (ins->dreg == last_ins->sreg1) {
3199 MONO_DELETE_INS (bb, ins);
3202 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3203 ins->opcode = OP_MOVE;
3204 ins->sreg1 = last_ins->sreg1;
3208 * Note: reg1 must be different from the basereg in the second load
3209 * OP_LOAD_MEMBASE offset(basereg), reg1
3210 * OP_LOAD_MEMBASE offset(basereg), reg2
3212 * OP_LOAD_MEMBASE offset(basereg), reg1
3213 * OP_MOVE reg1, reg2
3215 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
3216 || last_ins->opcode == OP_LOAD_MEMBASE) &&
3217 ins->inst_basereg != last_ins->dreg &&
3218 ins->inst_basereg == last_ins->inst_basereg &&
3219 ins->inst_offset == last_ins->inst_offset) {
3221 if (ins->dreg == last_ins->dreg) {
3222 MONO_DELETE_INS (bb, ins);
3225 ins->opcode = OP_MOVE;
3226 ins->sreg1 = last_ins->dreg;
3229 //g_assert_not_reached ();
3233 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3234 * OP_LOAD_MEMBASE offset(basereg), reg
3236 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
3237 * OP_ICONST reg, imm
3239 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
3240 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
3241 ins->inst_basereg == last_ins->inst_destbasereg &&
3242 ins->inst_offset == last_ins->inst_offset) {
3243 //static int c = 0; g_print ("MATCHX %s %d\n", cfg->method->name,c++);
3244 ins->opcode = OP_ICONST;
3245 ins->inst_c0 = last_ins->inst_imm;
3246 g_assert_not_reached (); // check this rule
3250 case OP_LOADU1_MEMBASE:
3251 case OP_LOADI1_MEMBASE:
3252 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
3253 ins->inst_basereg == last_ins->inst_destbasereg &&
3254 ins->inst_offset == last_ins->inst_offset) {
3255 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_ICONV_TO_I1 : OP_ICONV_TO_U1;
3256 ins->sreg1 = last_ins->sreg1;
3259 case OP_LOADU2_MEMBASE:
3260 case OP_LOADI2_MEMBASE:
3261 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
3262 ins->inst_basereg == last_ins->inst_destbasereg &&
3263 ins->inst_offset == last_ins->inst_offset) {
3264 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_ICONV_TO_I2 : OP_ICONV_TO_U2;
3265 ins->sreg1 = last_ins->sreg1;
3269 ins->opcode = OP_MOVE;
3273 if (ins->dreg == ins->sreg1) {
3274 MONO_DELETE_INS (bb, ins);
3278 * OP_MOVE sreg, dreg
3279 * OP_MOVE dreg, sreg
3281 if (last_ins && last_ins->opcode == OP_MOVE &&
3282 ins->sreg1 == last_ins->dreg &&
3283 ins->dreg == last_ins->sreg1) {
3284 MONO_DELETE_INS (bb, ins);
3293 * the branch_cc_table should maintain the order of these
3307 branch_cc_table [] = {
3321 #define ADD_NEW_INS(cfg,dest,op) do { \
3322 MONO_INST_NEW ((cfg), (dest), (op)); \
3323 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3327 map_to_reg_reg_op (int op)
3336 case OP_COMPARE_IMM:
3338 case OP_ICOMPARE_IMM:
3352 case OP_LOAD_MEMBASE:
3353 return OP_LOAD_MEMINDEX;
3354 case OP_LOADI4_MEMBASE:
3355 return OP_LOADI4_MEMINDEX;
3356 case OP_LOADU4_MEMBASE:
3357 return OP_LOADU4_MEMINDEX;
3358 case OP_LOADU1_MEMBASE:
3359 return OP_LOADU1_MEMINDEX;
3360 case OP_LOADI2_MEMBASE:
3361 return OP_LOADI2_MEMINDEX;
3362 case OP_LOADU2_MEMBASE:
3363 return OP_LOADU2_MEMINDEX;
3364 case OP_LOADI1_MEMBASE:
3365 return OP_LOADI1_MEMINDEX;
3366 case OP_STOREI1_MEMBASE_REG:
3367 return OP_STOREI1_MEMINDEX;
3368 case OP_STOREI2_MEMBASE_REG:
3369 return OP_STOREI2_MEMINDEX;
3370 case OP_STOREI4_MEMBASE_REG:
3371 return OP_STOREI4_MEMINDEX;
3372 case OP_STORE_MEMBASE_REG:
3373 return OP_STORE_MEMINDEX;
3374 case OP_STORER4_MEMBASE_REG:
3375 return OP_STORER4_MEMINDEX;
3376 case OP_STORER8_MEMBASE_REG:
3377 return OP_STORER8_MEMINDEX;
3378 case OP_STORE_MEMBASE_IMM:
3379 return OP_STORE_MEMBASE_REG;
3380 case OP_STOREI1_MEMBASE_IMM:
3381 return OP_STOREI1_MEMBASE_REG;
3382 case OP_STOREI2_MEMBASE_IMM:
3383 return OP_STOREI2_MEMBASE_REG;
3384 case OP_STOREI4_MEMBASE_IMM:
3385 return OP_STOREI4_MEMBASE_REG;
3387 g_assert_not_reached ();
3391 * Remove from the instruction list the instructions that can't be
3392 * represented with very simple instructions with no register
3396 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3398 MonoInst *ins, *temp, *last_ins = NULL;
3399 int rot_amount, imm8, low_imm;
3401 MONO_BB_FOR_EACH_INS (bb, ins) {
3403 switch (ins->opcode) {
3407 case OP_COMPARE_IMM:
3408 case OP_ICOMPARE_IMM:
3422 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount)) < 0) {
3423 int opcode2 = mono_op_imm_to_op (ins->opcode);
3424 ADD_NEW_INS (cfg, temp, OP_ICONST);
3425 temp->inst_c0 = ins->inst_imm;
3426 temp->dreg = mono_alloc_ireg (cfg);
3427 ins->sreg2 = temp->dreg;
3429 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3430 ins->opcode = opcode2;
3432 if (ins->opcode == OP_SBB || ins->opcode == OP_ISBB || ins->opcode == OP_SUBCC)
3438 if (ins->inst_imm == 1) {
3439 ins->opcode = OP_MOVE;
3442 if (ins->inst_imm == 0) {
3443 ins->opcode = OP_ICONST;
3447 imm8 = mono_is_power_of_two (ins->inst_imm);
3449 ins->opcode = OP_SHL_IMM;
3450 ins->inst_imm = imm8;
3453 ADD_NEW_INS (cfg, temp, OP_ICONST);
3454 temp->inst_c0 = ins->inst_imm;
3455 temp->dreg = mono_alloc_ireg (cfg);
3456 ins->sreg2 = temp->dreg;
3457 ins->opcode = OP_IMUL;
3463 if (ins->next && (ins->next->opcode == OP_COND_EXC_C || ins->next->opcode == OP_COND_EXC_IC))
3464 /* ARM sets the C flag to 1 if there was _no_ overflow */
3465 ins->next->opcode = OP_COND_EXC_NC;
3468 case OP_IDIV_UN_IMM:
3470 case OP_IREM_UN_IMM: {
3471 int opcode2 = mono_op_imm_to_op (ins->opcode);
3472 ADD_NEW_INS (cfg, temp, OP_ICONST);
3473 temp->inst_c0 = ins->inst_imm;
3474 temp->dreg = mono_alloc_ireg (cfg);
3475 ins->sreg2 = temp->dreg;
3477 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
3478 ins->opcode = opcode2;
3481 case OP_LOCALLOC_IMM:
3482 ADD_NEW_INS (cfg, temp, OP_ICONST);
3483 temp->inst_c0 = ins->inst_imm;
3484 temp->dreg = mono_alloc_ireg (cfg);
3485 ins->sreg1 = temp->dreg;
3486 ins->opcode = OP_LOCALLOC;
3488 case OP_LOAD_MEMBASE:
3489 case OP_LOADI4_MEMBASE:
3490 case OP_LOADU4_MEMBASE:
3491 case OP_LOADU1_MEMBASE:
3492 /* we can do two things: load the immed in a register
3493 * and use an indexed load, or see if the immed can be
3494 * represented as an ad_imm + a load with a smaller offset
3495 * that fits. We just do the first for now, optimize later.
3497 if (arm_is_imm12 (ins->inst_offset))
3499 ADD_NEW_INS (cfg, temp, OP_ICONST);
3500 temp->inst_c0 = ins->inst_offset;
3501 temp->dreg = mono_alloc_ireg (cfg);
3502 ins->sreg2 = temp->dreg;
3503 ins->opcode = map_to_reg_reg_op (ins->opcode);
3505 case OP_LOADI2_MEMBASE:
3506 case OP_LOADU2_MEMBASE:
3507 case OP_LOADI1_MEMBASE:
3508 if (arm_is_imm8 (ins->inst_offset))
3510 ADD_NEW_INS (cfg, temp, OP_ICONST);
3511 temp->inst_c0 = ins->inst_offset;
3512 temp->dreg = mono_alloc_ireg (cfg);
3513 ins->sreg2 = temp->dreg;
3514 ins->opcode = map_to_reg_reg_op (ins->opcode);
3516 case OP_LOADR4_MEMBASE:
3517 case OP_LOADR8_MEMBASE:
3518 if (arm_is_fpimm8 (ins->inst_offset))
3520 low_imm = ins->inst_offset & 0x1ff;
3521 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~0x1ff, &rot_amount)) >= 0) {
3522 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3523 temp->inst_imm = ins->inst_offset & ~0x1ff;
3524 temp->sreg1 = ins->inst_basereg;
3525 temp->dreg = mono_alloc_ireg (cfg);
3526 ins->inst_basereg = temp->dreg;
3527 ins->inst_offset = low_imm;
3531 ADD_NEW_INS (cfg, temp, OP_ICONST);
3532 temp->inst_c0 = ins->inst_offset;
3533 temp->dreg = mono_alloc_ireg (cfg);
3535 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3536 add_ins->sreg1 = ins->inst_basereg;
3537 add_ins->sreg2 = temp->dreg;
3538 add_ins->dreg = mono_alloc_ireg (cfg);
3540 ins->inst_basereg = add_ins->dreg;
3541 ins->inst_offset = 0;
3544 case OP_STORE_MEMBASE_REG:
3545 case OP_STOREI4_MEMBASE_REG:
3546 case OP_STOREI1_MEMBASE_REG:
3547 if (arm_is_imm12 (ins->inst_offset))
3549 ADD_NEW_INS (cfg, temp, OP_ICONST);
3550 temp->inst_c0 = ins->inst_offset;
3551 temp->dreg = mono_alloc_ireg (cfg);
3552 ins->sreg2 = temp->dreg;
3553 ins->opcode = map_to_reg_reg_op (ins->opcode);
3555 case OP_STOREI2_MEMBASE_REG:
3556 if (arm_is_imm8 (ins->inst_offset))
3558 ADD_NEW_INS (cfg, temp, OP_ICONST);
3559 temp->inst_c0 = ins->inst_offset;
3560 temp->dreg = mono_alloc_ireg (cfg);
3561 ins->sreg2 = temp->dreg;
3562 ins->opcode = map_to_reg_reg_op (ins->opcode);
3564 case OP_STORER4_MEMBASE_REG:
3565 case OP_STORER8_MEMBASE_REG:
3566 if (arm_is_fpimm8 (ins->inst_offset))
3568 low_imm = ins->inst_offset & 0x1ff;
3569 if ((imm8 = mono_arm_is_rotated_imm8 (ins->inst_offset & ~ 0x1ff, &rot_amount)) >= 0 && arm_is_fpimm8 (low_imm)) {
3570 ADD_NEW_INS (cfg, temp, OP_ADD_IMM);
3571 temp->inst_imm = ins->inst_offset & ~0x1ff;
3572 temp->sreg1 = ins->inst_destbasereg;
3573 temp->dreg = mono_alloc_ireg (cfg);
3574 ins->inst_destbasereg = temp->dreg;
3575 ins->inst_offset = low_imm;
3579 ADD_NEW_INS (cfg, temp, OP_ICONST);
3580 temp->inst_c0 = ins->inst_offset;
3581 temp->dreg = mono_alloc_ireg (cfg);
3583 ADD_NEW_INS (cfg, add_ins, OP_IADD);
3584 add_ins->sreg1 = ins->inst_destbasereg;
3585 add_ins->sreg2 = temp->dreg;
3586 add_ins->dreg = mono_alloc_ireg (cfg);
3588 ins->inst_destbasereg = add_ins->dreg;
3589 ins->inst_offset = 0;
3592 case OP_STORE_MEMBASE_IMM:
3593 case OP_STOREI1_MEMBASE_IMM:
3594 case OP_STOREI2_MEMBASE_IMM:
3595 case OP_STOREI4_MEMBASE_IMM:
3596 ADD_NEW_INS (cfg, temp, OP_ICONST);
3597 temp->inst_c0 = ins->inst_imm;
3598 temp->dreg = mono_alloc_ireg (cfg);
3599 ins->sreg1 = temp->dreg;
3600 ins->opcode = map_to_reg_reg_op (ins->opcode);
3602 goto loop_start; /* make it handle the possibly big ins->inst_offset */
3605 gboolean swap = FALSE;
3609 /* Optimized away */
3614 /* Some fp compares require swapped operands */
3615 switch (ins->next->opcode) {
3617 ins->next->opcode = OP_FBLT;
3621 ins->next->opcode = OP_FBLT_UN;
3625 ins->next->opcode = OP_FBGE;
3629 ins->next->opcode = OP_FBGE_UN;
3637 ins->sreg1 = ins->sreg2;
3646 bb->last_ins = last_ins;
3647 bb->max_vreg = cfg->next_vreg;
3651 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
3655 if (long_ins->opcode == OP_LNEG) {
3657 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSBS_IMM, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1), 0);
3658 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ARM_RSC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
3664 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3666 /* sreg is a float, dreg is an integer reg */
3668 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3670 ARM_TOSIZD (code, vfp_scratch1, sreg);
3672 ARM_TOUIZD (code, vfp_scratch1, sreg);
3673 ARM_FMRS (code, dreg, vfp_scratch1);
3674 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3678 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3679 else if (size == 2) {
3680 ARM_SHL_IMM (code, dreg, dreg, 16);
3681 ARM_SHR_IMM (code, dreg, dreg, 16);
3685 ARM_SHL_IMM (code, dreg, dreg, 24);
3686 ARM_SAR_IMM (code, dreg, dreg, 24);
3687 } else if (size == 2) {
3688 ARM_SHL_IMM (code, dreg, dreg, 16);
3689 ARM_SAR_IMM (code, dreg, dreg, 16);
3696 emit_r4_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3698 /* sreg is a float, dreg is an integer reg */
3700 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
3702 ARM_TOSIZS (code, vfp_scratch1, sreg);
3704 ARM_TOUIZS (code, vfp_scratch1, sreg);
3705 ARM_FMRS (code, dreg, vfp_scratch1);
3706 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
3710 ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
3711 else if (size == 2) {
3712 ARM_SHL_IMM (code, dreg, dreg, 16);
3713 ARM_SHR_IMM (code, dreg, dreg, 16);
3717 ARM_SHL_IMM (code, dreg, dreg, 24);
3718 ARM_SAR_IMM (code, dreg, dreg, 24);
3719 } else if (size == 2) {
3720 ARM_SHL_IMM (code, dreg, dreg, 16);
3721 ARM_SAR_IMM (code, dreg, dreg, 16);
3727 #endif /* #ifndef DISABLE_JIT */
3729 #define is_call_imm(diff) ((gint)(diff) >= -33554432 && (gint)(diff) <= 33554431)
3732 emit_thunk (guint8 *code, gconstpointer target)
3736 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
3737 if (thumb_supported)
3738 ARM_BX (code, ARMREG_IP);
3740 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
3741 *(guint32*)code = (guint32)target;
3743 mono_arch_flush_icache (p, code - p);
3747 handle_thunk (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3749 MonoJitInfo *ji = NULL;
3750 MonoThunkJitInfo *info;
3753 guint8 *orig_target;
3754 guint8 *target_thunk;
3757 domain = mono_domain_get ();
3761 * This can be called multiple times during JITting,
3762 * save the current position in cfg->arch to avoid
3763 * doing a O(n^2) search.
3765 if (!cfg->arch.thunks) {
3766 cfg->arch.thunks = cfg->thunks;
3767 cfg->arch.thunks_size = cfg->thunk_area;
3769 thunks = cfg->arch.thunks;
3770 thunks_size = cfg->arch.thunks_size;
3772 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, mono_method_full_name (cfg->method, TRUE));
3773 g_assert_not_reached ();
3776 g_assert (*(guint32*)thunks == 0);
3777 emit_thunk (thunks, target);
3778 arm_patch (code, thunks);
3780 cfg->arch.thunks += THUNK_SIZE;
3781 cfg->arch.thunks_size -= THUNK_SIZE;
3783 ji = mini_jit_info_table_find (domain, (char*)code, NULL);
3785 info = mono_jit_info_get_thunk_info (ji);
3788 thunks = (guint8*)ji->code_start + info->thunks_offset;
3789 thunks_size = info->thunks_size;
3791 orig_target = mono_arch_get_call_target (code + 4);
3793 mono_mini_arch_lock ();
3795 target_thunk = NULL;
3796 if (orig_target >= thunks && orig_target < thunks + thunks_size) {
3797 /* The call already points to a thunk, because of trampolines etc. */
3798 target_thunk = orig_target;
3800 for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) {
3801 if (((guint32*)p) [0] == 0) {
3805 } else if (((guint32*)p) [2] == (guint32)target) {
3806 /* Thunk already points to target */
3813 //g_print ("THUNK: %p %p %p\n", code, target, target_thunk);
3815 if (!target_thunk) {
3816 mono_mini_arch_unlock ();
3817 g_print ("thunk failed %p->%p, thunk space=%d method %s", code, target, thunks_size, cfg ? mono_method_full_name (cfg->method, TRUE) : mono_method_full_name (jinfo_get_method (ji), TRUE));
3818 g_assert_not_reached ();
3821 emit_thunk (target_thunk, target);
3822 arm_patch (code, target_thunk);
3823 mono_arch_flush_icache (code, 4);
3825 mono_mini_arch_unlock ();
3830 arm_patch_general (MonoCompile *cfg, MonoDomain *domain, guchar *code, const guchar *target)
3832 guint32 *code32 = (void*)code;
3833 guint32 ins = *code32;
3834 guint32 prim = (ins >> 25) & 7;
3835 guint32 tval = GPOINTER_TO_UINT (target);
3837 //g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
3838 if (prim == 5) { /* 101b */
3839 /* the diff starts 8 bytes from the branch opcode */
3840 gint diff = target - code - 8;
3842 gint tmask = 0xffffffff;
3843 if (tval & 1) { /* entering thumb mode */
3844 diff = target - 1 - code - 8;
3845 g_assert (thumb_supported);
3846 tbits = 0xf << 28; /* bl->blx bit pattern */
3847 g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
3848 /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
3852 tmask = ~(1 << 24); /* clear the link bit */
3853 /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
3858 if (diff <= 33554431) {
3860 ins = (ins & 0xff000000) | diff;
3862 *code32 = ins | tbits;
3866 /* diff between 0 and -33554432 */
3867 if (diff >= -33554432) {
3869 ins = (ins & 0xff000000) | (diff & ~0xff000000);
3871 *code32 = ins | tbits;
3876 handle_thunk (cfg, domain, code, target);
3881 * The alternative call sequences looks like this:
3883 * ldr ip, [pc] // loads the address constant
3884 * b 1f // jumps around the constant
3885 * address constant embedded in the code
3890 * There are two cases for patching:
3891 * a) at the end of method emission: in this case code points to the start
3892 * of the call sequence
3893 * b) during runtime patching of the call site: in this case code points
3894 * to the mov pc, ip instruction
3896 * We have to handle also the thunk jump code sequence:
3900 * address constant // execution never reaches here
3902 if ((ins & 0x0ffffff0) == 0x12fff10) {
3903 /* Branch and exchange: the address is constructed in a reg
3904 * We can patch BX when the code sequence is the following:
3905 * ldr ip, [pc, #0] ; 0x8
3912 guint8 *emit = (guint8*)ccode;
3913 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3915 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3916 ARM_BX (emit, ARMREG_IP);
3918 /*patching from magic trampoline*/
3919 if (ins == ccode [3]) {
3920 g_assert (code32 [-4] == ccode [0]);
3921 g_assert (code32 [-3] == ccode [1]);
3922 g_assert (code32 [-1] == ccode [2]);
3923 code32 [-2] = (guint32)target;
3926 /*patching from JIT*/
3927 if (ins == ccode [0]) {
3928 g_assert (code32 [1] == ccode [1]);
3929 g_assert (code32 [3] == ccode [2]);
3930 g_assert (code32 [4] == ccode [3]);
3931 code32 [2] = (guint32)target;
3934 g_assert_not_reached ();
3935 } else if ((ins & 0x0ffffff0) == 0x12fff30) {
3943 guint8 *emit = (guint8*)ccode;
3944 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3946 ARM_BLX_REG (emit, ARMREG_IP);
3948 g_assert (code32 [-3] == ccode [0]);
3949 g_assert (code32 [-2] == ccode [1]);
3950 g_assert (code32 [0] == ccode [2]);
3952 code32 [-1] = (guint32)target;
3955 guint32 *tmp = ccode;
3956 guint8 *emit = (guint8*)tmp;
3957 ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
3958 ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
3959 ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
3960 ARM_BX (emit, ARMREG_IP);
3961 if (ins == ccode [2]) {
3962 g_assert_not_reached (); // should be -2 ...
3963 code32 [-1] = (guint32)target;
3966 if (ins == ccode [0]) {
3967 /* handles both thunk jump code and the far call sequence */
3968 code32 [2] = (guint32)target;
3971 g_assert_not_reached ();
3973 // g_print ("patched with 0x%08x\n", ins);
3977 arm_patch (guchar *code, const guchar *target)
3979 arm_patch_general (NULL, NULL, code, target);
3983 * Return the >= 0 uimm8 value if val can be represented with a byte + rotation
3984 * (with the rotation amount in *rot_amount. rot_amount is already adjusted
3985 * to be used with the emit macros.
3986 * Return -1 otherwise.
3989 mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
3992 for (i = 0; i < 31; i+= 2) {
3993 res = (val << (32 - i)) | (val >> i);
3996 *rot_amount = i? 32 - i: 0;
4003 * Emits in code a sequence of instructions that load the value 'val'
4004 * into the dreg register. Uses at most 4 instructions.
4007 mono_arm_emit_load_imm (guint8 *code, int dreg, guint32 val)
4009 int imm8, rot_amount;
4011 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4012 /* skip the constant pool */
4018 if (mini_get_debug_options()->single_imm_size && v7_supported) {
4019 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4020 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4024 if ((imm8 = mono_arm_is_rotated_imm8 (val, &rot_amount)) >= 0) {
4025 ARM_MOV_REG_IMM (code, dreg, imm8, rot_amount);
4026 } else if ((imm8 = mono_arm_is_rotated_imm8 (~val, &rot_amount)) >= 0) {
4027 ARM_MVN_REG_IMM (code, dreg, imm8, rot_amount);
4030 ARM_MOVW_REG_IMM (code, dreg, val & 0xffff);
4032 ARM_MOVT_REG_IMM (code, dreg, (val >> 16) & 0xffff);
4036 ARM_MOV_REG_IMM8 (code, dreg, (val & 0xFF));
4038 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4040 if (val & 0xFF0000) {
4041 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4043 if (val & 0xFF000000) {
4044 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4046 } else if (val & 0xFF00) {
4047 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF00) >> 8, 24);
4048 if (val & 0xFF0000) {
4049 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4051 if (val & 0xFF000000) {
4052 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4054 } else if (val & 0xFF0000) {
4055 ARM_MOV_REG_IMM (code, dreg, (val & 0xFF0000) >> 16, 16);
4056 if (val & 0xFF000000) {
4057 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF000000) >> 24, 8);
4060 //g_assert_not_reached ();
4066 mono_arm_thumb_supported (void)
4068 return thumb_supported;
4074 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
4079 call = (MonoCallInst*)ins;
4080 cinfo = call->call_info;
4082 switch (cinfo->ret.storage) {
4083 case RegTypeStructByVal:
4085 MonoInst *loc = cfg->arch.vret_addr_loc;
4088 if (cinfo->ret.storage == RegTypeStructByVal && cinfo->ret.nregs == 1) {
4089 /* The JIT treats this as a normal call */
4093 /* Load the destination address */
4094 g_assert (loc && loc->opcode == OP_REGOFFSET);
4096 if (arm_is_imm12 (loc->inst_offset)) {
4097 ARM_LDR_IMM (code, ARMREG_LR, loc->inst_basereg, loc->inst_offset);
4099 code = mono_arm_emit_load_imm (code, ARMREG_LR, loc->inst_offset);
4100 ARM_LDR_REG_REG (code, ARMREG_LR, loc->inst_basereg, ARMREG_LR);
4103 if (cinfo->ret.storage == RegTypeStructByVal) {
4104 int rsize = cinfo->ret.struct_size;
4106 for (i = 0; i < cinfo->ret.nregs; ++i) {
4107 g_assert (rsize >= 0);
4112 ARM_STRB_IMM (code, i, ARMREG_LR, i * 4);
4115 ARM_STRH_IMM (code, i, ARMREG_LR, i * 4);
4118 ARM_STR_IMM (code, i, ARMREG_LR, i * 4);
4124 for (i = 0; i < cinfo->ret.nregs; ++i) {
4125 if (cinfo->ret.esize == 4)
4126 ARM_FSTS (code, cinfo->ret.reg + i, ARMREG_LR, i * 4);
4128 ARM_FSTD (code, cinfo->ret.reg + (i * 2), ARMREG_LR, i * 8);
4137 switch (ins->opcode) {
4140 case OP_FCALL_MEMBASE:
4142 MonoType *sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4143 if (sig_ret->type == MONO_TYPE_R4) {
4144 if (IS_HARD_FLOAT) {
4145 ARM_CVTS (code, ins->dreg, ARM_VFP_F0);
4147 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4148 ARM_CVTS (code, ins->dreg, ins->dreg);
4151 if (IS_HARD_FLOAT) {
4152 ARM_CPYD (code, ins->dreg, ARM_VFP_D0);
4154 ARM_FMDRR (code, ARMREG_R0, ARMREG_R1, ins->dreg);
4161 case OP_RCALL_MEMBASE: {
4166 sig_ret = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
4167 g_assert (sig_ret->type == MONO_TYPE_R4);
4168 if (IS_HARD_FLOAT) {
4169 ARM_CPYS (code, ins->dreg, ARM_VFP_F0);
4171 ARM_FMSR (code, ins->dreg, ARMREG_R0);
4172 ARM_CPYS (code, ins->dreg, ins->dreg);
4184 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
4189 guint8 *code = cfg->native_code + cfg->code_len;
4190 MonoInst *last_ins = NULL;
4191 guint last_offset = 0;
4193 int imm8, rot_amount;
4195 /* we don't align basic blocks of loops on arm */
4197 if (cfg->verbose_level > 2)
4198 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4200 cpos = bb->max_offset;
4202 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
4203 //MonoCoverageInfo *cov = mono_get_coverage_info (cfg->method);
4204 //g_assert (!mono_compile_aot);
4207 // cov->data [bb->dfn].iloffset = bb->cil_code - cfg->cil_code;
4208 /* this is not thread save, but good enough */
4209 /* fixme: howto handle overflows? */
4210 //x86_inc_mem (code, &cov->data [bb->dfn].count);
4213 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num) {
4214 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4215 (gpointer)"mono_break");
4216 code = emit_call_seq (cfg, code);
4219 MONO_BB_FOR_EACH_INS (bb, ins) {
4220 offset = code - cfg->native_code;
4222 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4224 if (offset > (cfg->code_size - max_len - 16)) {
4225 cfg->code_size *= 2;
4226 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4227 code = cfg->native_code + offset;
4229 // if (ins->cil_code)
4230 // g_print ("cil code\n");
4231 mono_debug_record_line_number (cfg, ins, offset);
4233 switch (ins->opcode) {
4234 case OP_MEMORY_BARRIER:
4236 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
4237 ARM_MCR (code, 15, 0, ARMREG_R0, 7, 10, 5);
4241 code = mono_arm_emit_tls_get (cfg, code, ins->dreg, ins->inst_offset);
4243 case OP_TLS_GET_REG:
4244 code = mono_arm_emit_tls_get_reg (cfg, code, ins->dreg, ins->sreg1);
4247 code = mono_arm_emit_tls_set (cfg, code, ins->sreg1, ins->inst_offset);
4249 case OP_TLS_SET_REG:
4250 code = mono_arm_emit_tls_set_reg (cfg, code, ins->sreg1, ins->sreg2);
4252 case OP_ATOMIC_EXCHANGE_I4:
4253 case OP_ATOMIC_CAS_I4:
4254 case OP_ATOMIC_ADD_I4: {
4258 g_assert (v7_supported);
4261 if (ins->sreg1 != ARMREG_IP && ins->sreg2 != ARMREG_IP && ins->sreg3 != ARMREG_IP)
4263 else if (ins->sreg1 != ARMREG_R0 && ins->sreg2 != ARMREG_R0 && ins->sreg3 != ARMREG_R0)
4265 else if (ins->sreg1 != ARMREG_R1 && ins->sreg2 != ARMREG_R1 && ins->sreg3 != ARMREG_R1)
4269 g_assert (cfg->arch.atomic_tmp_offset != -1);
4270 ARM_STR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4272 switch (ins->opcode) {
4273 case OP_ATOMIC_EXCHANGE_I4:
4275 ARM_DMB (code, ARM_DMB_SY);
4276 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4277 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4278 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4280 ARM_B_COND (code, ARMCOND_NE, 0);
4281 arm_patch (buf [1], buf [0]);
4283 case OP_ATOMIC_CAS_I4:
4284 ARM_DMB (code, ARM_DMB_SY);
4286 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4287 ARM_CMP_REG_REG (code, ARMREG_LR, ins->sreg3);
4289 ARM_B_COND (code, ARMCOND_NE, 0);
4290 ARM_STREX_REG (code, tmpreg, ins->sreg2, ins->sreg1);
4291 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4293 ARM_B_COND (code, ARMCOND_NE, 0);
4294 arm_patch (buf [2], buf [0]);
4295 arm_patch (buf [1], code);
4297 case OP_ATOMIC_ADD_I4:
4299 ARM_DMB (code, ARM_DMB_SY);
4300 ARM_LDREX_REG (code, ARMREG_LR, ins->sreg1);
4301 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->sreg2);
4302 ARM_STREX_REG (code, tmpreg, ARMREG_LR, ins->sreg1);
4303 ARM_CMP_REG_IMM (code, tmpreg, 0, 0);
4305 ARM_B_COND (code, ARMCOND_NE, 0);
4306 arm_patch (buf [1], buf [0]);
4309 g_assert_not_reached ();
4312 ARM_DMB (code, ARM_DMB_SY);
4313 if (tmpreg != ins->dreg)
4314 ARM_LDR_IMM (code, tmpreg, cfg->frame_reg, cfg->arch.atomic_tmp_offset);
4315 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_LR);
4318 case OP_ATOMIC_LOAD_I1:
4319 case OP_ATOMIC_LOAD_U1:
4320 case OP_ATOMIC_LOAD_I2:
4321 case OP_ATOMIC_LOAD_U2:
4322 case OP_ATOMIC_LOAD_I4:
4323 case OP_ATOMIC_LOAD_U4:
4324 case OP_ATOMIC_LOAD_R4:
4325 case OP_ATOMIC_LOAD_R8: {
4326 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4327 ARM_DMB (code, ARM_DMB_SY);
4329 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4331 switch (ins->opcode) {
4332 case OP_ATOMIC_LOAD_I1:
4333 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4335 case OP_ATOMIC_LOAD_U1:
4336 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4338 case OP_ATOMIC_LOAD_I2:
4339 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4341 case OP_ATOMIC_LOAD_U2:
4342 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4344 case OP_ATOMIC_LOAD_I4:
4345 case OP_ATOMIC_LOAD_U4:
4346 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4348 case OP_ATOMIC_LOAD_R4:
4350 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4351 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
4353 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4354 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4355 ARM_FLDS (code, vfp_scratch1, ARMREG_LR, 0);
4356 ARM_CVTS (code, ins->dreg, vfp_scratch1);
4357 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4360 case OP_ATOMIC_LOAD_R8:
4361 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_basereg, ARMREG_LR);
4362 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
4366 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4367 ARM_DMB (code, ARM_DMB_SY);
4370 case OP_ATOMIC_STORE_I1:
4371 case OP_ATOMIC_STORE_U1:
4372 case OP_ATOMIC_STORE_I2:
4373 case OP_ATOMIC_STORE_U2:
4374 case OP_ATOMIC_STORE_I4:
4375 case OP_ATOMIC_STORE_U4:
4376 case OP_ATOMIC_STORE_R4:
4377 case OP_ATOMIC_STORE_R8: {
4378 if (ins->backend.memory_barrier_kind != MONO_MEMORY_BARRIER_NONE)
4379 ARM_DMB (code, ARM_DMB_SY);
4381 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4383 switch (ins->opcode) {
4384 case OP_ATOMIC_STORE_I1:
4385 case OP_ATOMIC_STORE_U1:
4386 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4388 case OP_ATOMIC_STORE_I2:
4389 case OP_ATOMIC_STORE_U2:
4390 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4392 case OP_ATOMIC_STORE_I4:
4393 case OP_ATOMIC_STORE_U4:
4394 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4396 case OP_ATOMIC_STORE_R4:
4398 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4399 ARM_FSTS (code, ins->sreg1, ARMREG_LR, 0);
4401 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4402 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4403 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4404 ARM_FSTS (code, vfp_scratch1, ARMREG_LR, 0);
4405 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4408 case OP_ATOMIC_STORE_R8:
4409 ARM_ADD_REG_REG (code, ARMREG_LR, ins->inst_destbasereg, ARMREG_LR);
4410 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
4414 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4415 ARM_DMB (code, ARM_DMB_SY);
4419 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4420 ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
4423 ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
4424 ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
4426 case OP_STOREI1_MEMBASE_IMM:
4427 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
4428 g_assert (arm_is_imm12 (ins->inst_offset));
4429 ARM_STRB_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4431 case OP_STOREI2_MEMBASE_IMM:
4432 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFFFF);
4433 g_assert (arm_is_imm8 (ins->inst_offset));
4434 ARM_STRH_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4436 case OP_STORE_MEMBASE_IMM:
4437 case OP_STOREI4_MEMBASE_IMM:
4438 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm);
4439 g_assert (arm_is_imm12 (ins->inst_offset));
4440 ARM_STR_IMM (code, ARMREG_LR, ins->inst_destbasereg, ins->inst_offset);
4442 case OP_STOREI1_MEMBASE_REG:
4443 g_assert (arm_is_imm12 (ins->inst_offset));
4444 ARM_STRB_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4446 case OP_STOREI2_MEMBASE_REG:
4447 g_assert (arm_is_imm8 (ins->inst_offset));
4448 ARM_STRH_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4450 case OP_STORE_MEMBASE_REG:
4451 case OP_STOREI4_MEMBASE_REG:
4452 /* this case is special, since it happens for spill code after lowering has been called */
4453 if (arm_is_imm12 (ins->inst_offset)) {
4454 ARM_STR_IMM (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
4456 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4457 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ARMREG_LR);
4460 case OP_STOREI1_MEMINDEX:
4461 ARM_STRB_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4463 case OP_STOREI2_MEMINDEX:
4464 ARM_STRH_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4466 case OP_STORE_MEMINDEX:
4467 case OP_STOREI4_MEMINDEX:
4468 ARM_STR_REG_REG (code, ins->sreg1, ins->inst_destbasereg, ins->sreg2);
4471 g_assert_not_reached ();
4473 case OP_LOAD_MEMINDEX:
4474 case OP_LOADI4_MEMINDEX:
4475 case OP_LOADU4_MEMINDEX:
4476 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4478 case OP_LOADI1_MEMINDEX:
4479 ARM_LDRSB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4481 case OP_LOADU1_MEMINDEX:
4482 ARM_LDRB_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4484 case OP_LOADI2_MEMINDEX:
4485 ARM_LDRSH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4487 case OP_LOADU2_MEMINDEX:
4488 ARM_LDRH_REG_REG (code, ins->dreg, ins->inst_basereg, ins->sreg2);
4490 case OP_LOAD_MEMBASE:
4491 case OP_LOADI4_MEMBASE:
4492 case OP_LOADU4_MEMBASE:
4493 /* this case is special, since it happens for spill code after lowering has been called */
4494 if (arm_is_imm12 (ins->inst_offset)) {
4495 ARM_LDR_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4497 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
4498 ARM_LDR_REG_REG (code, ins->dreg, ins->inst_basereg, ARMREG_LR);
4501 case OP_LOADI1_MEMBASE:
4502 g_assert (arm_is_imm8 (ins->inst_offset));
4503 ARM_LDRSB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4505 case OP_LOADU1_MEMBASE:
4506 g_assert (arm_is_imm12 (ins->inst_offset));
4507 ARM_LDRB_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4509 case OP_LOADU2_MEMBASE:
4510 g_assert (arm_is_imm8 (ins->inst_offset));
4511 ARM_LDRH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4513 case OP_LOADI2_MEMBASE:
4514 g_assert (arm_is_imm8 (ins->inst_offset));
4515 ARM_LDRSH_IMM (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4517 case OP_ICONV_TO_I1:
4518 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 24);
4519 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 24);
4521 case OP_ICONV_TO_I2:
4522 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4523 ARM_SAR_IMM (code, ins->dreg, ins->dreg, 16);
4525 case OP_ICONV_TO_U1:
4526 ARM_AND_REG_IMM8 (code, ins->dreg, ins->sreg1, 0xff);
4528 case OP_ICONV_TO_U2:
4529 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, 16);
4530 ARM_SHR_IMM (code, ins->dreg, ins->dreg, 16);
4534 ARM_CMP_REG_REG (code, ins->sreg1, ins->sreg2);
4536 case OP_COMPARE_IMM:
4537 case OP_ICOMPARE_IMM:
4538 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4539 g_assert (imm8 >= 0);
4540 ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
4544 * gdb does not like encountering the hw breakpoint ins in the debugged code.
4545 * So instead of emitting a trap, we emit a call a C function and place a
4548 //*(int*)code = 0xef9f0001;
4551 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4552 (gpointer)"mono_break");
4553 code = emit_call_seq (cfg, code);
4555 case OP_RELAXED_NOP:
4560 case OP_DUMMY_STORE:
4561 case OP_DUMMY_ICONST:
4562 case OP_DUMMY_R8CONST:
4563 case OP_NOT_REACHED:
4566 case OP_IL_SEQ_POINT:
4567 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4569 case OP_SEQ_POINT: {
4571 MonoInst *info_var = cfg->arch.seq_point_info_var;
4572 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
4573 MonoInst *ss_method_var = cfg->arch.seq_point_ss_method_var;
4574 MonoInst *bp_method_var = cfg->arch.seq_point_bp_method_var;
4576 int dreg = ARMREG_LR;
4578 if (cfg->soft_breakpoints) {
4579 g_assert (!cfg->compile_aot);
4583 * For AOT, we use one got slot per method, which will point to a
4584 * SeqPointInfo structure, containing all the information required
4585 * by the code below.
4587 if (cfg->compile_aot) {
4588 g_assert (info_var);
4589 g_assert (info_var->opcode == OP_REGOFFSET);
4590 g_assert (arm_is_imm12 (info_var->inst_offset));
4593 if (!cfg->soft_breakpoints && !cfg->compile_aot) {
4595 * Read from the single stepping trigger page. This will cause a
4596 * SIGSEGV when single stepping is enabled.
4597 * We do this _before_ the breakpoint, so single stepping after
4598 * a breakpoint is hit will step to the next IL offset.
4600 g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
4603 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4604 if (cfg->soft_breakpoints) {
4605 /* Load the address of the sequence point method variable. */
4606 var = ss_method_var;
4608 g_assert (var->opcode == OP_REGOFFSET);
4609 g_assert (arm_is_imm12 (var->inst_offset));
4610 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4612 /* Read the value and check whether it is non-zero. */
4613 ARM_LDR_IMM (code, dreg, dreg, 0);
4614 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4615 /* Call it conditionally. */
4616 ARM_BLX_REG_COND (code, ARMCOND_NE, dreg);
4618 if (cfg->compile_aot) {
4619 /* Load the trigger page addr from the variable initialized in the prolog */
4620 var = ss_trigger_page_var;
4622 g_assert (var->opcode == OP_REGOFFSET);
4623 g_assert (arm_is_imm12 (var->inst_offset));
4624 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4626 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
4628 *(int*)code = (int)ss_trigger_page;
4631 ARM_LDR_IMM (code, dreg, dreg, 0);
4635 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4637 if (cfg->soft_breakpoints) {
4638 /* Load the address of the breakpoint method into ip. */
4639 var = bp_method_var;
4641 g_assert (var->opcode == OP_REGOFFSET);
4642 g_assert (arm_is_imm12 (var->inst_offset));
4643 ARM_LDR_IMM (code, dreg, var->inst_basereg, var->inst_offset);
4646 * A placeholder for a possible breakpoint inserted by
4647 * mono_arch_set_breakpoint ().
4650 } else if (cfg->compile_aot) {
4651 guint32 offset = code - cfg->native_code;
4654 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
4655 /* Add the offset */
4656 val = ((offset / 4) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4657 /* Load the info->bp_addrs [offset], which is either 0 or the address of a trigger page */
4658 if (arm_is_imm12 ((int)val)) {
4659 ARM_LDR_IMM (code, dreg, dreg, val);
4661 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF), 0);
4663 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF00) >> 8, 24);
4665 ARM_ADD_REG_IMM (code, dreg, dreg, (val & 0xFF0000) >> 16, 16);
4666 g_assert (!(val & 0xFF000000));
4668 ARM_LDR_IMM (code, dreg, dreg, 0);
4670 /* What is faster, a branch or a load ? */
4671 ARM_CMP_REG_IMM (code, dreg, 0, 0);
4672 /* The breakpoint instruction */
4673 ARM_LDR_IMM_COND (code, dreg, dreg, 0, ARMCOND_NE);
4676 * A placeholder for a possible breakpoint inserted by
4677 * mono_arch_set_breakpoint ().
4679 for (i = 0; i < 4; ++i)
4684 * Add an additional nop so skipping the bp doesn't cause the ip to point
4685 * to another IL offset.
4693 ARM_ADDS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4696 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4700 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4703 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4704 g_assert (imm8 >= 0);
4705 ARM_ADDS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4709 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4710 g_assert (imm8 >= 0);
4711 ARM_ADD_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4715 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4716 g_assert (imm8 >= 0);
4717 ARM_ADCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4720 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4721 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4723 case OP_IADD_OVF_UN:
4724 ARM_ADD_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4725 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4728 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4729 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4731 case OP_ISUB_OVF_UN:
4732 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4733 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4735 case OP_ADD_OVF_CARRY:
4736 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4737 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4739 case OP_ADD_OVF_UN_CARRY:
4740 ARM_ADCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4741 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4743 case OP_SUB_OVF_CARRY:
4744 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4745 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_FALSE, PPC_BR_EQ, "OverflowException");
4747 case OP_SUB_OVF_UN_CARRY:
4748 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4749 //EMIT_COND_SYSTEM_EXCEPTION_FLAGS (PPC_BR_TRUE, PPC_BR_EQ, "OverflowException");
4753 ARM_SUBS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4756 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4757 g_assert (imm8 >= 0);
4758 ARM_SUBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4761 ARM_SUB_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4765 ARM_SBCS_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4769 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4770 g_assert (imm8 >= 0);
4771 ARM_SUB_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4775 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4776 g_assert (imm8 >= 0);
4777 ARM_SBCS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4779 case OP_ARM_RSBS_IMM:
4780 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4781 g_assert (imm8 >= 0);
4782 ARM_RSBS_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4784 case OP_ARM_RSC_IMM:
4785 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4786 g_assert (imm8 >= 0);
4787 ARM_RSC_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4790 ARM_AND_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4794 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4795 g_assert (imm8 >= 0);
4796 ARM_AND_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4799 g_assert (v7s_supported || v7k_supported);
4800 ARM_SDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4803 g_assert (v7s_supported || v7k_supported);
4804 ARM_UDIV (code, ins->dreg, ins->sreg1, ins->sreg2);
4807 g_assert (v7s_supported || v7k_supported);
4808 ARM_SDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4809 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4812 g_assert (v7s_supported || v7k_supported);
4813 ARM_UDIV (code, ARMREG_LR, ins->sreg1, ins->sreg2);
4814 ARM_MLS (code, ins->dreg, ARMREG_LR, ins->sreg2, ins->sreg1);
4818 g_assert_not_reached ();
4820 ARM_ORR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4824 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4825 g_assert (imm8 >= 0);
4826 ARM_ORR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4829 ARM_EOR_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4833 imm8 = mono_arm_is_rotated_imm8 (ins->inst_imm, &rot_amount);
4834 g_assert (imm8 >= 0);
4835 ARM_EOR_REG_IMM (code, ins->dreg, ins->sreg1, imm8, rot_amount);
4838 ARM_SHL_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4843 ARM_SHL_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4844 else if (ins->dreg != ins->sreg1)
4845 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4848 ARM_SAR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4853 ARM_SAR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4854 else if (ins->dreg != ins->sreg1)
4855 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4858 case OP_ISHR_UN_IMM:
4860 ARM_SHR_IMM (code, ins->dreg, ins->sreg1, (ins->inst_imm & 0x1f));
4861 else if (ins->dreg != ins->sreg1)
4862 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4865 ARM_SHR_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4868 ARM_MVN_REG_REG (code, ins->dreg, ins->sreg1);
4871 ARM_RSB_REG_IMM8 (code, ins->dreg, ins->sreg1, 0);
4874 if (ins->dreg == ins->sreg2)
4875 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4877 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg2, ins->sreg1);
4880 g_assert_not_reached ();
4883 /* FIXME: handle ovf/ sreg2 != dreg */
4884 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4885 /* FIXME: MUL doesn't set the C/O flags on ARM */
4887 case OP_IMUL_OVF_UN:
4888 /* FIXME: handle ovf/ sreg2 != dreg */
4889 ARM_MUL_REG_REG (code, ins->dreg, ins->sreg1, ins->sreg2);
4890 /* FIXME: MUL doesn't set the C/O flags on ARM */
4893 code = mono_arm_emit_load_imm (code, ins->dreg, ins->inst_c0);
4896 /* Load the GOT offset */
4897 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4898 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4900 *(gpointer*)code = NULL;
4902 /* Load the value from the GOT */
4903 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4905 case OP_OBJC_GET_SELECTOR:
4906 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_OBJC_SELECTOR_REF, ins->inst_p0);
4907 ARM_LDR_IMM (code, ins->dreg, ARMREG_PC, 0);
4909 *(gpointer*)code = NULL;
4911 ARM_LDR_REG_REG (code, ins->dreg, ARMREG_PC, ins->dreg);
4913 case OP_ICONV_TO_I4:
4914 case OP_ICONV_TO_U4:
4916 if (ins->dreg != ins->sreg1)
4917 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
4920 int saved = ins->sreg2;
4921 if (ins->sreg2 == ARM_LSW_REG) {
4922 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg2);
4925 if (ins->sreg1 != ARM_LSW_REG)
4926 ARM_MOV_REG_REG (code, ARM_LSW_REG, ins->sreg1);
4927 if (saved != ARM_MSW_REG)
4928 ARM_MOV_REG_REG (code, ARM_MSW_REG, saved);
4932 if (IS_VFP && ins->dreg != ins->sreg1)
4933 ARM_CPYD (code, ins->dreg, ins->sreg1);
4936 if (IS_VFP && ins->dreg != ins->sreg1)
4937 ARM_CPYS (code, ins->dreg, ins->sreg1);
4939 case OP_MOVE_F_TO_I4:
4941 ARM_FMRS (code, ins->dreg, ins->sreg1);
4943 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
4944 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
4945 ARM_FMRS (code, ins->dreg, vfp_scratch1);
4946 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
4949 case OP_MOVE_I4_TO_F:
4951 ARM_FMSR (code, ins->dreg, ins->sreg1);
4953 ARM_FMSR (code, ins->dreg, ins->sreg1);
4954 ARM_CVTS (code, ins->dreg, ins->dreg);
4957 case OP_FCONV_TO_R4:
4960 ARM_CVTD (code, ins->dreg, ins->sreg1);
4962 ARM_CVTD (code, ins->dreg, ins->sreg1);
4963 ARM_CVTS (code, ins->dreg, ins->dreg);
4968 MonoCallInst *call = (MonoCallInst*)ins;
4971 * The stack looks like the following:
4972 * <caller argument area>
4975 * <callee argument area>
4976 * Need to copy the arguments from the callee argument area to
4977 * the caller argument area, and pop the frame.
4979 if (call->stack_usage) {
4980 int i, prev_sp_offset = 0;
4982 /* Compute size of saved registers restored below */
4984 prev_sp_offset = 2 * 4;
4986 prev_sp_offset = 1 * 4;
4987 for (i = 0; i < 16; ++i) {
4988 if (cfg->used_int_regs & (1 << i))
4989 prev_sp_offset += 4;
4992 code = emit_big_add (code, ARMREG_IP, cfg->frame_reg, cfg->stack_usage + prev_sp_offset);
4994 /* Copy arguments on the stack to our argument area */
4995 for (i = 0; i < call->stack_usage; i += sizeof (mgreg_t)) {
4996 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, i);
4997 ARM_STR_IMM (code, ARMREG_LR, ARMREG_IP, i);
5002 * Keep in sync with mono_arch_emit_epilog
5004 g_assert (!cfg->method->save_lmf);
5006 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage);
5008 if (cfg->used_int_regs)
5009 ARM_POP (code, cfg->used_int_regs);
5010 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
5012 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_LR));
5015 mono_add_patch_info (cfg, (guint8*) code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
5016 if (cfg->compile_aot) {
5017 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
5019 *(gpointer*)code = NULL;
5021 ARM_LDR_REG_REG (code, ARMREG_PC, ARMREG_PC, ARMREG_IP);
5023 code = mono_arm_patchable_b (code, ARMCOND_AL);
5024 cfg->thunk_area += THUNK_SIZE;
5029 /* ensure ins->sreg1 is not NULL */
5030 ARM_LDRB_IMM (code, ARMREG_LR, ins->sreg1, 0);
5033 g_assert (cfg->sig_cookie < 128);
5034 ARM_LDR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
5035 ARM_STR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5045 call = (MonoCallInst*)ins;
5048 code = emit_float_args (cfg, call, code, &max_len, &offset);
5050 if (ins->flags & MONO_INST_HAS_METHOD)
5051 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
5053 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
5054 code = emit_call_seq (cfg, code);
5055 ins->flags |= MONO_INST_GC_CALLSITE;
5056 ins->backend.pc_offset = code - cfg->native_code;
5057 code = emit_move_return_value (cfg, ins, code);
5064 case OP_VOIDCALL_REG:
5067 code = emit_float_args (cfg, (MonoCallInst *)ins, code, &max_len, &offset);
5069 code = emit_call_reg (code, ins->sreg1);
5070 ins->flags |= MONO_INST_GC_CALLSITE;
5071 ins->backend.pc_offset = code - cfg->native_code;
5072 code = emit_move_return_value (cfg, ins, code);
5074 case OP_FCALL_MEMBASE:
5075 case OP_RCALL_MEMBASE:
5076 case OP_LCALL_MEMBASE:
5077 case OP_VCALL_MEMBASE:
5078 case OP_VCALL2_MEMBASE:
5079 case OP_VOIDCALL_MEMBASE:
5080 case OP_CALL_MEMBASE: {
5081 g_assert (ins->sreg1 != ARMREG_LR);
5082 call = (MonoCallInst*)ins;
5085 code = emit_float_args (cfg, call, code, &max_len, &offset);
5086 if (!arm_is_imm12 (ins->inst_offset)) {
5087 /* sreg1 might be IP */
5088 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5089 code = mono_arm_emit_load_imm (code, ARMREG_IP, ins->inst_offset);
5090 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, ARMREG_LR);
5091 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5092 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, 0);
5094 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5095 ARM_LDR_IMM (code, ARMREG_PC, ins->sreg1, ins->inst_offset);
5097 ins->flags |= MONO_INST_GC_CALLSITE;
5098 ins->backend.pc_offset = code - cfg->native_code;
5099 code = emit_move_return_value (cfg, ins, code);
5102 case OP_GENERIC_CLASS_INIT: {
5103 static int byte_offset = -1;
5104 static guint8 bitmask;
5108 if (byte_offset < 0)
5109 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5111 g_assert (arm_is_imm8 (byte_offset));
5112 ARM_LDRSB_IMM (code, ARMREG_IP, ins->sreg1, byte_offset);
5113 imm8 = mono_arm_is_rotated_imm8 (bitmask, &rot_amount);
5114 g_assert (imm8 >= 0);
5115 ARM_AND_REG_IMM (code, ARMREG_IP, ARMREG_IP, imm8, rot_amount);
5116 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5118 ARM_B_COND (code, ARMCOND_NE, 0);
5120 /* Uninitialized case */
5121 g_assert (ins->sreg1 == ARMREG_R0);
5123 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5124 (gpointer)"mono_generic_class_init");
5125 code = emit_call_seq (cfg, code);
5127 /* Initialized case */
5128 arm_patch (jump, code);
5132 /* round the size to 8 bytes */
5133 ARM_ADD_REG_IMM8 (code, ins->dreg, ins->sreg1, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5134 ARM_BIC_REG_IMM8 (code, ins->dreg, ins->dreg, (MONO_ARCH_FRAME_ALIGNMENT - 1));
5135 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ins->dreg);
5136 /* memzero the area: dreg holds the size, sp is the pointer */
5137 if (ins->flags & MONO_INST_INIT) {
5138 guint8 *start_loop, *branch_to_cond;
5139 ARM_MOV_REG_IMM8 (code, ARMREG_LR, 0);
5140 branch_to_cond = code;
5143 ARM_STR_REG_REG (code, ARMREG_LR, ARMREG_SP, ins->dreg);
5144 arm_patch (branch_to_cond, code);
5145 /* decrement by 4 and set flags */
5146 ARM_SUBS_REG_IMM8 (code, ins->dreg, ins->dreg, sizeof (mgreg_t));
5147 ARM_B_COND (code, ARMCOND_GE, 0);
5148 arm_patch (code - 4, start_loop);
5150 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_SP);
5151 if (cfg->param_area)
5152 code = emit_sub_imm (code, ARMREG_SP, ARMREG_SP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5157 MonoInst *var = cfg->dyn_call_var;
5160 g_assert (var->opcode == OP_REGOFFSET);
5161 g_assert (arm_is_imm12 (var->inst_offset));
5163 /* lr = args buffer filled by mono_arch_get_dyn_call_args () */
5164 ARM_MOV_REG_REG (code, ARMREG_LR, ins->sreg1);
5166 ARM_MOV_REG_REG (code, ARMREG_IP, ins->sreg2);
5168 /* Save args buffer */
5169 ARM_STR_IMM (code, ARMREG_LR, var->inst_basereg, var->inst_offset);
5171 /* Set stack slots using R0 as scratch reg */
5172 /* MONO_ARCH_DYN_CALL_PARAM_AREA gives the size of stack space available */
5173 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
5174 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, (PARAM_REGS + i) * sizeof (mgreg_t));
5175 ARM_STR_IMM (code, ARMREG_R0, ARMREG_SP, i * sizeof (mgreg_t));
5178 /* Set fp argument registers */
5179 if (IS_HARD_FLOAT) {
5180 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, MONO_STRUCT_OFFSET (DynCallArgs, has_fpregs));
5181 ARM_CMP_REG_IMM (code, ARMREG_R0, 0, 0);
5183 ARM_B_COND (code, ARMCOND_EQ, 0);
5184 for (i = 0; i < FP_PARAM_REGS; ++i) {
5185 int offset = MONO_STRUCT_OFFSET (DynCallArgs, fpregs) + (i * sizeof (double));
5186 g_assert (arm_is_fpimm8 (offset));
5187 ARM_FLDD (code, i * 2, ARMREG_LR, offset);
5189 arm_patch (buf [0], code);
5192 /* Set argument registers */
5193 for (i = 0; i < PARAM_REGS; ++i)
5194 ARM_LDR_IMM (code, i, ARMREG_LR, i * sizeof (mgreg_t));
5197 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
5198 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5201 ARM_LDR_IMM (code, ARMREG_IP, var->inst_basereg, var->inst_offset);
5202 ARM_STR_IMM (code, ARMREG_R0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res));
5203 ARM_STR_IMM (code, ARMREG_R1, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, res2));
5205 ARM_FSTD (code, ARM_VFP_D0, ARMREG_IP, MONO_STRUCT_OFFSET (DynCallArgs, fpregs));
5209 if (ins->sreg1 != ARMREG_R0)
5210 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5211 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5212 (gpointer)"mono_arch_throw_exception");
5213 code = emit_call_seq (cfg, code);
5217 if (ins->sreg1 != ARMREG_R0)
5218 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5219 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
5220 (gpointer)"mono_arch_rethrow_exception");
5221 code = emit_call_seq (cfg, code);
5224 case OP_START_HANDLER: {
5225 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5226 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5229 /* Reserve a param area, see filter-stack.exe */
5231 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5232 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5234 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5235 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5239 if (arm_is_imm12 (spvar->inst_offset)) {
5240 ARM_STR_IMM (code, ARMREG_LR, spvar->inst_basereg, spvar->inst_offset);
5242 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5243 ARM_STR_REG_REG (code, ARMREG_LR, spvar->inst_basereg, ARMREG_IP);
5247 case OP_ENDFILTER: {
5248 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5249 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5252 /* Free the param area */
5254 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5255 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5257 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5258 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5262 if (ins->sreg1 != ARMREG_R0)
5263 ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
5264 if (arm_is_imm12 (spvar->inst_offset)) {
5265 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5267 g_assert (ARMREG_IP != spvar->inst_basereg);
5268 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5269 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5271 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5274 case OP_ENDFINALLY: {
5275 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5276 int param_area = ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT);
5279 /* Free the param area */
5281 if ((i = mono_arm_is_rotated_imm8 (param_area, &rot_amount)) >= 0) {
5282 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
5284 code = mono_arm_emit_load_imm (code, ARMREG_IP, param_area);
5285 ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
5289 if (arm_is_imm12 (spvar->inst_offset)) {
5290 ARM_LDR_IMM (code, ARMREG_IP, spvar->inst_basereg, spvar->inst_offset);
5292 g_assert (ARMREG_IP != spvar->inst_basereg);
5293 code = mono_arm_emit_load_imm (code, ARMREG_IP, spvar->inst_offset);
5294 ARM_LDR_REG_REG (code, ARMREG_IP, spvar->inst_basereg, ARMREG_IP);
5296 ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
5299 case OP_CALL_HANDLER:
5300 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5301 code = mono_arm_patchable_bl (code, ARMCOND_AL);
5302 cfg->thunk_area += THUNK_SIZE;
5303 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5306 if (ins->dreg != ARMREG_R0)
5307 ARM_MOV_REG_REG (code, ins->dreg, ARMREG_R0);
5311 ins->inst_c0 = code - cfg->native_code;
5314 /*if (ins->inst_target_bb->native_offset) {
5316 //x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5318 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5319 code = mono_arm_patchable_b (code, ARMCOND_AL);
5323 ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
5327 * In the normal case we have:
5328 * ldr pc, [pc, ins->sreg1 << 2]
5331 * ldr lr, [pc, ins->sreg1 << 2]
5333 * After follows the data.
5334 * FIXME: add aot support.
5336 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_SWITCH, ins->inst_p0);
5337 max_len += 4 * GPOINTER_TO_INT (ins->klass);
5338 if (offset + max_len > (cfg->code_size - 16)) {
5339 cfg->code_size += max_len;
5340 cfg->code_size *= 2;
5341 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5342 code = cfg->native_code + offset;
5344 ARM_LDR_REG_REG_SHIFT (code, ARMREG_PC, ARMREG_PC, ins->sreg1, ARMSHIFT_LSL, 2);
5346 code += 4 * GPOINTER_TO_INT (ins->klass);
5350 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5351 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5355 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5356 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LT);
5360 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5361 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_LO);
5365 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5366 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_GT);
5370 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5371 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_HI);
5374 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5375 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5378 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5379 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LT);
5382 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5383 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_GT);
5386 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5387 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_LO);
5390 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5391 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_HI);
5393 case OP_COND_EXC_EQ:
5394 case OP_COND_EXC_NE_UN:
5395 case OP_COND_EXC_LT:
5396 case OP_COND_EXC_LT_UN:
5397 case OP_COND_EXC_GT:
5398 case OP_COND_EXC_GT_UN:
5399 case OP_COND_EXC_GE:
5400 case OP_COND_EXC_GE_UN:
5401 case OP_COND_EXC_LE:
5402 case OP_COND_EXC_LE_UN:
5403 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_EQ, ins->inst_p1);
5405 case OP_COND_EXC_IEQ:
5406 case OP_COND_EXC_INE_UN:
5407 case OP_COND_EXC_ILT:
5408 case OP_COND_EXC_ILT_UN:
5409 case OP_COND_EXC_IGT:
5410 case OP_COND_EXC_IGT_UN:
5411 case OP_COND_EXC_IGE:
5412 case OP_COND_EXC_IGE_UN:
5413 case OP_COND_EXC_ILE:
5414 case OP_COND_EXC_ILE_UN:
5415 EMIT_COND_SYSTEM_EXCEPTION (ins->opcode - OP_COND_EXC_IEQ, ins->inst_p1);
5418 case OP_COND_EXC_IC:
5419 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CS, ins->inst_p1);
5421 case OP_COND_EXC_OV:
5422 case OP_COND_EXC_IOV:
5423 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, ins->inst_p1);
5425 case OP_COND_EXC_NC:
5426 case OP_COND_EXC_INC:
5427 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_CC, ins->inst_p1);
5429 case OP_COND_EXC_NO:
5430 case OP_COND_EXC_INO:
5431 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VC, ins->inst_p1);
5443 EMIT_COND_BRANCH (ins, ins->opcode - OP_IBEQ);
5446 /* floating point opcodes */
5448 if (cfg->compile_aot) {
5449 ARM_FLDD (code, ins->dreg, ARMREG_PC, 0);
5451 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5453 *(guint32*)code = ((guint32*)(ins->inst_p0))[1];
5456 /* FIXME: we can optimize the imm load by dealing with part of
5457 * the displacement in LDFD (aligning to 512).
5459 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5460 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5464 if (cfg->compile_aot) {
5465 ARM_FLDS (code, ins->dreg, ARMREG_PC, 0);
5467 *(guint32*)code = ((guint32*)(ins->inst_p0))[0];
5470 ARM_CVTS (code, ins->dreg, ins->dreg);
5472 code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
5473 ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
5475 ARM_CVTS (code, ins->dreg, ins->dreg);
5478 case OP_STORER8_MEMBASE_REG:
5479 /* This is generated by the local regalloc pass which runs after the lowering pass */
5480 if (!arm_is_fpimm8 (ins->inst_offset)) {
5481 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5482 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_destbasereg);
5483 ARM_FSTD (code, ins->sreg1, ARMREG_LR, 0);
5485 ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5488 case OP_LOADR8_MEMBASE:
5489 /* This is generated by the local regalloc pass which runs after the lowering pass */
5490 if (!arm_is_fpimm8 (ins->inst_offset)) {
5491 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
5492 ARM_ADD_REG_REG (code, ARMREG_LR, ARMREG_LR, ins->inst_basereg);
5493 ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
5495 ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5498 case OP_STORER4_MEMBASE_REG:
5499 g_assert (arm_is_fpimm8 (ins->inst_offset));
5501 ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
5503 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5504 ARM_CVTD (code, vfp_scratch1, ins->sreg1);
5505 ARM_FSTS (code, vfp_scratch1, ins->inst_destbasereg, ins->inst_offset);
5506 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5509 case OP_LOADR4_MEMBASE:
5511 ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5513 g_assert (arm_is_fpimm8 (ins->inst_offset));
5514 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5515 ARM_FLDS (code, vfp_scratch1, ins->inst_basereg, ins->inst_offset);
5516 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5517 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5520 case OP_ICONV_TO_R_UN: {
5521 g_assert_not_reached ();
5524 case OP_ICONV_TO_R4:
5526 ARM_FMSR (code, ins->dreg, ins->sreg1);
5527 ARM_FSITOS (code, ins->dreg, ins->dreg);
5529 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5530 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5531 ARM_FSITOS (code, vfp_scratch1, vfp_scratch1);
5532 ARM_CVTS (code, ins->dreg, vfp_scratch1);
5533 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5536 case OP_ICONV_TO_R8:
5537 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5538 ARM_FMSR (code, vfp_scratch1, ins->sreg1);
5539 ARM_FSITOD (code, ins->dreg, vfp_scratch1);
5540 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5544 MonoType *sig_ret = mini_get_underlying_type (mono_method_signature (cfg->method)->ret);
5545 if (sig_ret->type == MONO_TYPE_R4) {
5547 if (IS_HARD_FLOAT) {
5548 if (ins->sreg1 != ARM_VFP_D0)
5549 ARM_CPYS (code, ARM_VFP_D0, ins->sreg1);
5551 ARM_FMRS (code, ARMREG_R0, ins->sreg1);
5554 ARM_CVTD (code, ARM_VFP_F0, ins->sreg1);
5557 ARM_FMRS (code, ARMREG_R0, ARM_VFP_F0);
5561 ARM_CPYD (code, ARM_VFP_D0, ins->sreg1);
5563 ARM_FMRRD (code, ARMREG_R0, ARMREG_R1, ins->sreg1);
5567 case OP_FCONV_TO_I1:
5568 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5570 case OP_FCONV_TO_U1:
5571 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5573 case OP_FCONV_TO_I2:
5574 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5576 case OP_FCONV_TO_U2:
5577 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5579 case OP_FCONV_TO_I4:
5581 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5583 case OP_FCONV_TO_U4:
5585 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5587 case OP_FCONV_TO_I8:
5588 case OP_FCONV_TO_U8:
5589 g_assert_not_reached ();
5590 /* Implemented as helper calls */
5592 case OP_LCONV_TO_R_UN:
5593 g_assert_not_reached ();
5594 /* Implemented as helper calls */
5596 case OP_LCONV_TO_OVF_I4_2: {
5597 guint8 *high_bit_not_set, *valid_negative, *invalid_negative, *valid_positive;
5599 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
5602 ARM_CMP_REG_IMM8 (code, ins->sreg1, 0);
5603 high_bit_not_set = code;
5604 ARM_B_COND (code, ARMCOND_GE, 0); /*branch if bit 31 of the lower part is not set*/
5606 ARM_CMN_REG_IMM8 (code, ins->sreg2, 1); /*This have the same effect as CMP reg, 0xFFFFFFFF */
5607 valid_negative = code;
5608 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0xFFFFFFFF (lower part has bit 31 set) */
5609 invalid_negative = code;
5610 ARM_B_COND (code, ARMCOND_AL, 0);
5612 arm_patch (high_bit_not_set, code);
5614 ARM_CMP_REG_IMM8 (code, ins->sreg2, 0);
5615 valid_positive = code;
5616 ARM_B_COND (code, ARMCOND_EQ, 0); /*branch if upper part == 0 (lower part has bit 31 clear)*/
5618 arm_patch (invalid_negative, code);
5619 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_AL, "OverflowException");
5621 arm_patch (valid_negative, code);
5622 arm_patch (valid_positive, code);
5624 if (ins->dreg != ins->sreg1)
5625 ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
5629 ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
5632 ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
5635 ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
5638 ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
5641 ARM_NEGD (code, ins->dreg, ins->sreg1);
5645 g_assert_not_reached ();
5649 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5655 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5660 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5663 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5664 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5668 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5671 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5672 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5676 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5679 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5680 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5681 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5685 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5688 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5689 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5693 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5696 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5697 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5698 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5702 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5705 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5706 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5710 ARM_CMPD (code, ins->sreg1, ins->sreg2);
5713 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5714 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5718 ARM_CMPD (code, ins->sreg2, ins->sreg1);
5721 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5722 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5725 /* ARM FPA flags table:
5726 * N Less than ARMCOND_MI
5727 * Z Equal ARMCOND_EQ
5728 * C Greater Than or Equal ARMCOND_CS
5729 * V Unordered ARMCOND_VS
5732 EMIT_COND_BRANCH (ins, OP_IBEQ - OP_IBEQ);
5735 EMIT_COND_BRANCH (ins, OP_IBNE_UN - OP_IBEQ);
5738 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5741 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5742 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
5748 g_assert_not_reached ();
5752 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5754 /* FPA requires EQ even thou the docs suggests that just CS is enough */
5755 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_EQ);
5756 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
5760 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
5761 EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
5766 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch1);
5767 code = mono_arm_emit_vfp_scratch_save (cfg, code, vfp_scratch2);
5769 ARM_ABSD (code, vfp_scratch2, ins->sreg1);
5770 ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0);
5772 *(guint32*)code = 0xffffffff;
5774 *(guint32*)code = 0x7fefffff;
5776 ARM_CMPD (code, vfp_scratch2, vfp_scratch1);
5778 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_GT, "OverflowException");
5779 ARM_CMPD (code, ins->sreg1, ins->sreg1);
5781 EMIT_COND_SYSTEM_EXCEPTION_FLAGS (ARMCOND_VS, "OverflowException");
5782 ARM_CPYD (code, ins->dreg, ins->sreg1);
5784 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch1);
5785 code = mono_arm_emit_vfp_scratch_restore (cfg, code, vfp_scratch2);
5790 case OP_RCONV_TO_I1:
5791 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5793 case OP_RCONV_TO_U1:
5794 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5796 case OP_RCONV_TO_I2:
5797 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5799 case OP_RCONV_TO_U2:
5800 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5802 case OP_RCONV_TO_I4:
5803 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5805 case OP_RCONV_TO_U4:
5806 code = emit_r4_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5808 case OP_RCONV_TO_R4:
5810 if (ins->dreg != ins->sreg1)
5811 ARM_CPYS (code, ins->dreg, ins->sreg1);
5813 case OP_RCONV_TO_R8:
5815 ARM_CVTS (code, ins->dreg, ins->sreg1);
5818 ARM_VFP_ADDS (code, ins->dreg, ins->sreg1, ins->sreg2);
5821 ARM_VFP_SUBS (code, ins->dreg, ins->sreg1, ins->sreg2);
5824 ARM_VFP_MULS (code, ins->dreg, ins->sreg1, ins->sreg2);
5827 ARM_VFP_DIVS (code, ins->dreg, ins->sreg1, ins->sreg2);
5830 ARM_NEGS (code, ins->dreg, ins->sreg1);
5834 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5837 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
5838 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
5842 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5845 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5846 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5850 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5853 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5854 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5855 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5859 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5862 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5863 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5867 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5870 ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
5871 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
5872 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
5876 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5879 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_NE);
5880 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_EQ);
5884 ARM_CMPS (code, ins->sreg1, ins->sreg2);
5887 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5888 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5892 ARM_CMPS (code, ins->sreg2, ins->sreg1);
5895 ARM_MOV_REG_IMM8 (code, ins->dreg, 1);
5896 ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_MI);
5899 case OP_GC_LIVENESS_DEF:
5900 case OP_GC_LIVENESS_USE:
5901 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5902 ins->backend.pc_offset = code - cfg->native_code;
5904 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5905 ins->backend.pc_offset = code - cfg->native_code;
5906 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5908 case OP_GC_SAFE_POINT: {
5911 g_assert (mono_threads_is_coop_enabled ());
5913 ARM_LDR_IMM (code, ARMREG_IP, ins->sreg1, 0);
5914 ARM_CMP_REG_IMM (code, ARMREG_IP, 0, 0);
5916 ARM_B_COND (code, ARMCOND_EQ, 0);
5917 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
5918 code = emit_call_seq (cfg, code);
5919 arm_patch (buf [0], code);
5924 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5925 g_assert_not_reached ();
5928 if ((cfg->opt & MONO_OPT_BRANCH) && ((code - cfg->native_code - offset) > max_len)) {
5929 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5930 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5931 g_assert_not_reached ();
5937 last_offset = offset;
5940 cfg->code_len = code - cfg->native_code;
5943 #endif /* DISABLE_JIT */
5946 mono_arch_register_lowlevel_calls (void)
5948 /* The signature doesn't matter */
5949 mono_register_jit_icall (mono_arm_throw_exception, "mono_arm_throw_exception", mono_create_icall_signature ("void"), TRUE);
5950 mono_register_jit_icall (mono_arm_throw_exception_by_token, "mono_arm_throw_exception_by_token", mono_create_icall_signature ("void"), TRUE);
5951 mono_register_jit_icall (mono_arm_unaligned_stack, "mono_arm_unaligned_stack", mono_create_icall_signature ("void"), TRUE);
5953 #ifndef MONO_CROSS_COMPILE
5954 if (mono_arm_have_tls_get ()) {
5955 MonoTlsImplementation tls_imp = mono_arm_get_tls_implementation ();
5957 mono_register_jit_icall (tls_imp.get_tls_thunk, "mono_get_tls_key", mono_create_icall_signature ("ptr ptr"), TRUE);
5958 mono_register_jit_icall (tls_imp.set_tls_thunk, "mono_set_tls_key", mono_create_icall_signature ("void ptr ptr"), TRUE);
5960 if (tls_imp.get_tls_thunk_end) {
5961 mono_tramp_info_register (
5962 mono_tramp_info_create (
5964 (guint8*)tls_imp.get_tls_thunk,
5965 (guint8*)tls_imp.get_tls_thunk_end - (guint8*)tls_imp.get_tls_thunk,
5967 mono_arch_get_cie_program ()
5971 mono_tramp_info_register (
5972 mono_tramp_info_create (
5974 (guint8*)tls_imp.set_tls_thunk,
5975 (guint8*)tls_imp.set_tls_thunk_end - (guint8*)tls_imp.set_tls_thunk,
5977 mono_arch_get_cie_program ()
5986 #define patch_lis_ori(ip,val) do {\
5987 guint16 *__lis_ori = (guint16*)(ip); \
5988 __lis_ori [1] = (((guint32)(val)) >> 16) & 0xffff; \
5989 __lis_ori [3] = ((guint32)(val)) & 0xffff; \
5993 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5995 unsigned char *ip = ji->ip.i + code;
5997 if (ji->type == MONO_PATCH_INFO_SWITCH) {
6001 case MONO_PATCH_INFO_SWITCH: {
6002 gpointer *jt = (gpointer*)(ip + 8);
6004 /* jt is the inlined jump table, 2 instructions after ip
6005 * In the normal case we store the absolute addresses,
6006 * otherwise the displacements.
6008 for (i = 0; i < ji->data.table->table_size; i++)
6009 jt [i] = code + (int)ji->data.table->table [i];
6012 case MONO_PATCH_INFO_IP:
6013 g_assert_not_reached ();
6014 patch_lis_ori (ip, ip);
6016 case MONO_PATCH_INFO_METHOD_REL:
6017 g_assert_not_reached ();
6018 *((gpointer *)(ip)) = target;
6020 case MONO_PATCH_INFO_METHODCONST:
6021 case MONO_PATCH_INFO_CLASS:
6022 case MONO_PATCH_INFO_IMAGE:
6023 case MONO_PATCH_INFO_FIELD:
6024 case MONO_PATCH_INFO_VTABLE:
6025 case MONO_PATCH_INFO_IID:
6026 case MONO_PATCH_INFO_SFLDA:
6027 case MONO_PATCH_INFO_LDSTR:
6028 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
6029 case MONO_PATCH_INFO_LDTOKEN:
6030 g_assert_not_reached ();
6031 /* from OP_AOTCONST : lis + ori */
6032 patch_lis_ori (ip, target);
6034 case MONO_PATCH_INFO_R4:
6035 case MONO_PATCH_INFO_R8:
6036 g_assert_not_reached ();
6037 *((gconstpointer *)(ip + 2)) = target;
6039 case MONO_PATCH_INFO_EXC_NAME:
6040 g_assert_not_reached ();
6041 *((gconstpointer *)(ip + 1)) = target;
6043 case MONO_PATCH_INFO_NONE:
6044 case MONO_PATCH_INFO_BB_OVF:
6045 case MONO_PATCH_INFO_EXC_OVF:
6046 /* everything is dealt with at epilog output time */
6049 arm_patch_general (cfg, domain, ip, target);
6055 mono_arm_unaligned_stack (MonoMethod *method)
6057 g_assert_not_reached ();
6063 * Stack frame layout:
6065 * ------------------- fp
6066 * MonoLMF structure or saved registers
6067 * -------------------
6069 * -------------------
6071 * -------------------
6072 * optional 8 bytes for tracing
6073 * -------------------
6074 * param area size is cfg->param_area
6075 * ------------------- sp
6078 mono_arch_emit_prolog (MonoCompile *cfg)
6080 MonoMethod *method = cfg->method;
6082 MonoMethodSignature *sig;
6084 int alloc_size, orig_alloc_size, pos, max_offset, i, rot_amount, part;
6089 int prev_sp_offset, reg_offset;
6091 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6094 sig = mono_method_signature (method);
6095 cfg->code_size = 256 + sig->param_count * 64;
6096 code = cfg->native_code = g_malloc (cfg->code_size);
6098 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, 0);
6100 alloc_size = cfg->stack_offset;
6106 * The iphone uses R7 as the frame pointer, and it points at the saved
6111 * We can't use r7 as a frame pointer since it points into the middle of
6112 * the frame, so we keep using our own frame pointer.
6113 * FIXME: Optimize this.
6115 ARM_PUSH (code, (1 << ARMREG_R7) | (1 << ARMREG_LR));
6116 prev_sp_offset += 8; /* r7 and lr */
6117 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6118 mono_emit_unwind_op_offset (cfg, code, ARMREG_R7, (- prev_sp_offset) + 0);
6119 ARM_MOV_REG_REG (code, ARMREG_R7, ARMREG_SP);
6122 if (!method->save_lmf) {
6124 /* No need to push LR again */
6125 if (cfg->used_int_regs)
6126 ARM_PUSH (code, cfg->used_int_regs);
6128 ARM_PUSH (code, cfg->used_int_regs | (1 << ARMREG_LR));
6129 prev_sp_offset += 4;
6131 for (i = 0; i < 16; ++i) {
6132 if (cfg->used_int_regs & (1 << i))
6133 prev_sp_offset += 4;
6135 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6137 for (i = 0; i < 16; ++i) {
6138 if ((cfg->used_int_regs & (1 << i))) {
6139 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6140 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + reg_offset, SLOT_NOREF);
6144 mono_emit_unwind_op_offset (cfg, code, ARMREG_LR, -4);
6145 mini_gc_set_slot_type_from_cfa (cfg, -4, SLOT_NOREF);
6147 ARM_MOV_REG_REG (code, ARMREG_IP, ARMREG_SP);
6148 ARM_PUSH (code, 0x5ff0);
6149 prev_sp_offset += 4 * 10; /* all but r0-r3, sp and pc */
6150 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset);
6152 for (i = 0; i < 16; ++i) {
6153 if ((i > ARMREG_R3) && (i != ARMREG_SP) && (i != ARMREG_PC)) {
6154 /* The original r7 is saved at the start */
6155 if (!(iphone_abi && i == ARMREG_R7))
6156 mono_emit_unwind_op_offset (cfg, code, i, (- prev_sp_offset) + reg_offset);
6160 g_assert (reg_offset == 4 * 10);
6161 pos += sizeof (MonoLMF) - (4 * 10);
6165 orig_alloc_size = alloc_size;
6166 // align to MONO_ARCH_FRAME_ALIGNMENT bytes
6167 if (alloc_size & (MONO_ARCH_FRAME_ALIGNMENT - 1)) {
6168 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - 1;
6169 alloc_size &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
6172 /* the stack used in the pushed regs */
6173 alloc_size += ALIGN_TO (prev_sp_offset, MONO_ARCH_FRAME_ALIGNMENT) - prev_sp_offset;
6174 cfg->stack_usage = alloc_size;
6176 if ((i = mono_arm_is_rotated_imm8 (alloc_size, &rot_amount)) >= 0) {
6177 ARM_SUB_REG_IMM (code, ARMREG_SP, ARMREG_SP, i, rot_amount);
6179 code = mono_arm_emit_load_imm (code, ARMREG_IP, alloc_size);
6180 ARM_SUB_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
6182 mono_emit_unwind_op_def_cfa_offset (cfg, code, prev_sp_offset + alloc_size);
6184 if (cfg->frame_reg != ARMREG_SP) {
6185 ARM_MOV_REG_REG (code, cfg->frame_reg, ARMREG_SP);
6186 mono_emit_unwind_op_def_cfa_reg (cfg, code, cfg->frame_reg);
6188 //g_print ("prev_sp_offset: %d, alloc_size:%d\n", prev_sp_offset, alloc_size);
6189 prev_sp_offset += alloc_size;
6191 for (i = 0; i < alloc_size - orig_alloc_size; i += 4)
6192 mini_gc_set_slot_type_from_cfa (cfg, (- prev_sp_offset) + orig_alloc_size + i, SLOT_NOREF);
6194 /* compute max_offset in order to use short forward jumps
6195 * we could skip do it on arm because the immediate displacement
6196 * for jumps is large enough, it may be useful later for constant pools
6199 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6200 MonoInst *ins = bb->code;
6201 bb->max_offset = max_offset;
6203 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6206 MONO_BB_FOR_EACH_INS (bb, ins)
6207 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6210 /* stack alignment check */
6214 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_SP);
6215 code = mono_arm_emit_load_imm (code, ARMREG_IP, MONO_ARCH_FRAME_ALIGNMENT -1);
6216 ARM_AND_REG_REG (code, ARMREG_LR, ARMREG_LR, ARMREG_IP);
6217 ARM_CMP_REG_IMM (code, ARMREG_LR, 0, 0);
6219 ARM_B_COND (code, ARMCOND_EQ, 0);
6220 if (cfg->compile_aot)
6221 ARM_MOV_REG_IMM8 (code, ARMREG_R0, 0);
6223 code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
6224 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arm_unaligned_stack");
6225 code = emit_call_seq (cfg, code);
6226 arm_patch (buf [0], code);
6230 /* store runtime generic context */
6231 if (cfg->rgctx_var) {
6232 MonoInst *ins = cfg->rgctx_var;
6234 g_assert (ins->opcode == OP_REGOFFSET);
6236 if (arm_is_imm12 (ins->inst_offset)) {
6237 ARM_STR_IMM (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ins->inst_offset);
6239 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6240 ARM_STR_REG_REG (code, MONO_ARCH_RGCTX_REG, ins->inst_basereg, ARMREG_LR);
6244 /* load arguments allocated to register from the stack */
6247 cinfo = get_call_info (NULL, sig);
6249 if (cinfo->ret.storage == RegTypeStructByAddr) {
6250 ArgInfo *ainfo = &cinfo->ret;
6251 inst = cfg->vret_addr;
6252 g_assert (arm_is_imm12 (inst->inst_offset));
6253 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6256 if (sig->call_convention == MONO_CALL_VARARG) {
6257 ArgInfo *cookie = &cinfo->sig_cookie;
6259 /* Save the sig cookie address */
6260 g_assert (cookie->storage == RegTypeBase);
6262 g_assert (arm_is_imm12 (prev_sp_offset + cookie->offset));
6263 g_assert (arm_is_imm12 (cfg->sig_cookie));
6264 ARM_ADD_REG_IMM8 (code, ARMREG_IP, cfg->frame_reg, prev_sp_offset + cookie->offset);
6265 ARM_STR_IMM (code, ARMREG_IP, cfg->frame_reg, cfg->sig_cookie);
6268 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6269 ArgInfo *ainfo = cinfo->args + i;
6270 inst = cfg->args [pos];
6272 if (cfg->verbose_level > 2)
6273 g_print ("Saving argument %d (type: %d)\n", i, ainfo->storage);
6275 if (inst->opcode == OP_REGVAR) {
6276 if (ainfo->storage == RegTypeGeneral)
6277 ARM_MOV_REG_REG (code, inst->dreg, ainfo->reg);
6278 else if (ainfo->storage == RegTypeFP) {
6279 g_assert_not_reached ();
6280 } else if (ainfo->storage == RegTypeBase) {
6281 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6282 ARM_LDR_IMM (code, inst->dreg, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6284 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6285 ARM_LDR_REG_REG (code, inst->dreg, ARMREG_SP, ARMREG_IP);
6288 g_assert_not_reached ();
6290 if (cfg->verbose_level > 2)
6291 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
6293 switch (ainfo->storage) {
6295 for (part = 0; part < ainfo->nregs; part ++) {
6296 if (ainfo->esize == 4)
6297 ARM_FSTS (code, ainfo->reg + part, inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6299 ARM_FSTD (code, ainfo->reg + (part * 2), inst->inst_basereg, inst->inst_offset + (part * ainfo->esize));
6302 case RegTypeGeneral:
6303 case RegTypeIRegPair:
6304 case RegTypeGSharedVtInReg:
6305 case RegTypeStructByAddr:
6306 switch (ainfo->size) {
6308 if (arm_is_imm12 (inst->inst_offset))
6309 ARM_STRB_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6311 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6312 ARM_STRB_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6316 if (arm_is_imm8 (inst->inst_offset)) {
6317 ARM_STRH_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6319 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6320 ARM_STRH_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6324 if (arm_is_imm12 (inst->inst_offset)) {
6325 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6327 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6328 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6330 if (arm_is_imm12 (inst->inst_offset + 4)) {
6331 ARM_STR_IMM (code, ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
6333 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6334 ARM_STR_REG_REG (code, ainfo->reg + 1, inst->inst_basereg, ARMREG_IP);
6338 if (arm_is_imm12 (inst->inst_offset)) {
6339 ARM_STR_IMM (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
6341 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6342 ARM_STR_REG_REG (code, ainfo->reg, inst->inst_basereg, ARMREG_IP);
6347 case RegTypeBaseGen:
6348 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6349 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6351 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6352 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6354 if (arm_is_imm12 (inst->inst_offset + 4)) {
6355 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6356 ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
6358 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6359 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6360 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6361 ARM_STR_REG_REG (code, ARMREG_R3, inst->inst_basereg, ARMREG_IP);
6365 case RegTypeGSharedVtOnStack:
6366 case RegTypeStructByAddrOnStack:
6367 if (arm_is_imm12 (prev_sp_offset + ainfo->offset)) {
6368 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
6370 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset);
6371 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6374 switch (ainfo->size) {
6376 if (arm_is_imm8 (inst->inst_offset)) {
6377 ARM_STRB_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6379 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6380 ARM_STRB_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6384 if (arm_is_imm8 (inst->inst_offset)) {
6385 ARM_STRH_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6387 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6388 ARM_STRH_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6392 if (arm_is_imm12 (inst->inst_offset)) {
6393 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6395 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6396 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6398 if (arm_is_imm12 (prev_sp_offset + ainfo->offset + 4)) {
6399 ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset + 4));
6401 code = mono_arm_emit_load_imm (code, ARMREG_IP, prev_sp_offset + ainfo->offset + 4);
6402 ARM_LDR_REG_REG (code, ARMREG_LR, ARMREG_SP, ARMREG_IP);
6404 if (arm_is_imm12 (inst->inst_offset + 4)) {
6405 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
6407 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset + 4);
6408 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6412 if (arm_is_imm12 (inst->inst_offset)) {
6413 ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset);
6415 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6416 ARM_STR_REG_REG (code, ARMREG_LR, inst->inst_basereg, ARMREG_IP);
6422 int imm8, rot_amount;
6424 if ((imm8 = mono_arm_is_rotated_imm8 (inst->inst_offset, &rot_amount)) == -1) {
6425 code = mono_arm_emit_load_imm (code, ARMREG_IP, inst->inst_offset);
6426 ARM_ADD_REG_REG (code, ARMREG_IP, ARMREG_IP, inst->inst_basereg);
6428 ARM_ADD_REG_IMM (code, ARMREG_IP, inst->inst_basereg, imm8, rot_amount);
6430 if (ainfo->size == 8)
6431 ARM_FSTD (code, ainfo->reg, ARMREG_IP, 0);
6433 ARM_FSTS (code, ainfo->reg, ARMREG_IP, 0);
6436 case RegTypeStructByVal: {
6437 int doffset = inst->inst_offset;
6441 size = mini_type_stack_size_full (inst->inst_vtype, NULL, sig->pinvoke);
6442 for (cur_reg = 0; cur_reg < ainfo->size; ++cur_reg) {
6443 if (arm_is_imm12 (doffset)) {
6444 ARM_STR_IMM (code, ainfo->reg + cur_reg, inst->inst_basereg, doffset);
6446 code = mono_arm_emit_load_imm (code, ARMREG_IP, doffset);
6447 ARM_STR_REG_REG (code, ainfo->reg + cur_reg, inst->inst_basereg, ARMREG_IP);
6449 soffset += sizeof (gpointer);
6450 doffset += sizeof (gpointer);
6452 if (ainfo->vtsize) {
6453 /* FIXME: handle overrun! with struct sizes not multiple of 4 */
6454 //g_print ("emit_memcpy (prev_sp_ofs: %d, ainfo->offset: %d, soffset: %d)\n", prev_sp_offset, ainfo->offset, soffset);
6455 code = emit_memcpy (code, ainfo->vtsize * sizeof (gpointer), inst->inst_basereg, doffset, ARMREG_SP, prev_sp_offset + ainfo->offset);
6460 g_assert_not_reached ();
6467 if (method->save_lmf)
6468 code = emit_save_lmf (cfg, code, alloc_size - lmf_offset);
6471 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6473 if (cfg->arch.seq_point_info_var) {
6474 MonoInst *ins = cfg->arch.seq_point_info_var;
6476 /* Initialize the variable from a GOT slot */
6477 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6478 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6480 *(gpointer*)code = NULL;
6482 ARM_LDR_REG_REG (code, ARMREG_R0, ARMREG_PC, ARMREG_R0);
6484 g_assert (ins->opcode == OP_REGOFFSET);
6486 if (arm_is_imm12 (ins->inst_offset)) {
6487 ARM_STR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6489 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6490 ARM_STR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6494 /* Initialize ss_trigger_page_var */
6495 if (!cfg->soft_breakpoints) {
6496 MonoInst *info_var = cfg->arch.seq_point_info_var;
6497 MonoInst *ss_trigger_page_var = cfg->arch.ss_trigger_page_var;
6498 int dreg = ARMREG_LR;
6501 g_assert (info_var->opcode == OP_REGOFFSET);
6502 g_assert (arm_is_imm12 (info_var->inst_offset));
6504 ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
6505 /* Load the trigger page addr */
6506 ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page));
6507 ARM_STR_IMM (code, dreg, ss_trigger_page_var->inst_basereg, ss_trigger_page_var->inst_offset);
6511 if (cfg->arch.seq_point_ss_method_var) {
6512 MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
6513 MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
6514 g_assert (ss_method_ins->opcode == OP_REGOFFSET);
6515 g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
6516 g_assert (bp_method_ins->opcode == OP_REGOFFSET);
6517 g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
6519 ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
6521 *(gpointer*)code = &single_step_tramp;
6523 *(gpointer*)code = breakpoint_tramp;
6526 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
6527 ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
6528 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
6529 ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
6532 cfg->code_len = code - cfg->native_code;
6533 g_assert (cfg->code_len < cfg->code_size);
6540 mono_arch_emit_epilog (MonoCompile *cfg)
6542 MonoMethod *method = cfg->method;
6543 int pos, i, rot_amount;
6544 int max_epilog_size = 16 + 20*4;
6548 if (cfg->method->save_lmf)
6549 max_epilog_size += 128;
6551 if (mono_jit_trace_calls != NULL)
6552 max_epilog_size += 50;
6554 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6555 max_epilog_size += 50;
6557 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6558 cfg->code_size *= 2;
6559 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6560 cfg->stat_code_reallocs++;
6564 * Keep in sync with OP_JMP
6566 code = cfg->native_code + cfg->code_len;
6568 /* Save the uwind state which is needed by the out-of-line code */
6569 mono_emit_unwind_op_remember_state (cfg, code);
6571 if (mono_jit_trace_calls != NULL && mono_trace_eval (method)) {
6572 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6576 /* Load returned vtypes into registers if needed */
6577 cinfo = cfg->arch.cinfo;
6578 switch (cinfo->ret.storage) {
6579 case RegTypeStructByVal: {
6580 MonoInst *ins = cfg->ret;
6582 if (cinfo->ret.nregs == 1) {
6583 if (arm_is_imm12 (ins->inst_offset)) {
6584 ARM_LDR_IMM (code, ARMREG_R0, ins->inst_basereg, ins->inst_offset);
6586 code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_offset);
6587 ARM_LDR_REG_REG (code, ARMREG_R0, ins->inst_basereg, ARMREG_LR);
6590 for (i = 0; i < cinfo->ret.nregs; ++i) {
6591 int offset = ins->inst_offset + (i * 4);
6592 if (arm_is_imm12 (offset)) {
6593 ARM_LDR_IMM (code, i, ins->inst_basereg, offset);
6595 code = mono_arm_emit_load_imm (code, ARMREG_LR, offset);
6596 ARM_LDR_REG_REG (code, i, ins->inst_basereg, ARMREG_LR);
6603 MonoInst *ins = cfg->ret;
6605 for (i = 0; i < cinfo->ret.nregs; ++i) {
6606 if (cinfo->ret.esize == 4)
6607 ARM_FLDS (code, cinfo->ret.reg + i, ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6609 ARM_FLDD (code, cinfo->ret.reg + (i * 2), ins->inst_basereg, ins->inst_offset + (i * cinfo->ret.esize));
6617 if (method->save_lmf) {
6618 int lmf_offset, reg, sp_adj, regmask, nused_int_regs = 0;
6619 /* all but r0-r3, sp and pc */
6620 pos += sizeof (MonoLMF) - (MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6623 code = emit_restore_lmf (cfg, code, cfg->stack_usage - lmf_offset);
6625 /* This points to r4 inside MonoLMF->iregs */
6626 sp_adj = (sizeof (MonoLMF) - MONO_ARM_NUM_SAVED_REGS * sizeof (mgreg_t));
6628 regmask = 0x9ff0; /* restore lr to pc */
6629 /* Skip caller saved registers not used by the method */
6630 while (!(cfg->used_int_regs & (1 << reg)) && reg < ARMREG_FP) {
6631 regmask &= ~(1 << reg);
6636 /* Restored later */
6637 regmask &= ~(1 << ARMREG_PC);
6638 /* point sp at the registers to restore: 10 is 14 -4, because we skip r0-r3 */
6639 code = emit_big_add (code, ARMREG_SP, cfg->frame_reg, cfg->stack_usage - lmf_offset + sp_adj);
6640 for (i = 0; i < 16; i++) {
6641 if (regmask & (1 << i))
6644 mono_emit_unwind_op_def_cfa (cfg, code, ARMREG_SP, ((iphone_abi ? 3 : 0) + nused_int_regs) * 4);
6646 ARM_POP (code, regmask);
6648 for (i = 0; i < 16; i++) {
6649 if (regmask & (1 << i))
6650 mono_emit_unwind_op_same_value (cfg, code, i);
6652 /* Restore saved r7, restore LR to PC */
6653 /* Skip lr from the lmf */
6654 mono_emit_unwind_op_def_cfa_offset (cfg, code, 3 * 4);
6655 ARM_ADD_REG_IMM (code, ARMREG_SP, ARMREG_SP, sizeof (gpointer), 0);
6656 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6657 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6660 int i, nused_int_regs = 0;
6662 for (i = 0; i < 16; i++) {
6663 if (cfg->used_int_regs & (1 << i))
6667 if ((i = mono_arm_is_rotated_imm8 (cfg->stack_usage, &rot_amount)) >= 0) {
6668 ARM_ADD_REG_IMM (code, ARMREG_SP, cfg->frame_reg, i, rot_amount);
6670 code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
6671 ARM_ADD_REG_REG (code, ARMREG_SP, cfg->frame_reg, ARMREG_IP);
6674 if (cfg->frame_reg != ARMREG_SP) {
6675 mono_emit_unwind_op_def_cfa_reg (cfg, code, ARMREG_SP);
6679 /* Restore saved gregs */
6680 if (cfg->used_int_regs) {
6681 mono_emit_unwind_op_def_cfa_offset (cfg, code, (2 + nused_int_regs) * 4);
6682 ARM_POP (code, cfg->used_int_regs);
6683 for (i = 0; i < 16; i++) {
6684 if (cfg->used_int_regs & (1 << i))
6685 mono_emit_unwind_op_same_value (cfg, code, i);
6688 mono_emit_unwind_op_def_cfa_offset (cfg, code, 2 * 4);
6689 /* Restore saved r7, restore LR to PC */
6690 ARM_POP (code, (1 << ARMREG_R7) | (1 << ARMREG_PC));
6692 mono_emit_unwind_op_def_cfa_offset (cfg, code, (nused_int_regs + 1) * 4);
6693 ARM_POP (code, cfg->used_int_regs | (1 << ARMREG_PC));
6697 /* Restore the unwind state to be the same as before the epilog */
6698 mono_emit_unwind_op_restore_state (cfg, code);
6700 cfg->code_len = code - cfg->native_code;
6702 g_assert (cfg->code_len < cfg->code_size);
6707 mono_arch_emit_exceptions (MonoCompile *cfg)
6709 MonoJumpInfo *patch_info;
6712 guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM];
6713 guint8 exc_throw_found [MONO_EXC_INTRINS_NUM];
6714 int max_epilog_size = 50;
6716 for (i = 0; i < MONO_EXC_INTRINS_NUM; i++) {
6717 exc_throw_pos [i] = NULL;
6718 exc_throw_found [i] = 0;
6721 /* count the number of exception infos */
6724 * make sure we have enough space for exceptions
6726 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6727 if (patch_info->type == MONO_PATCH_INFO_EXC) {
6728 i = mini_exception_id_by_name (patch_info->data.target);
6729 if (!exc_throw_found [i]) {
6730 max_epilog_size += 32;
6731 exc_throw_found [i] = TRUE;
6736 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6737 cfg->code_size *= 2;
6738 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6739 cfg->stat_code_reallocs++;
6742 code = cfg->native_code + cfg->code_len;
6744 /* add code to raise exceptions */
6745 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6746 switch (patch_info->type) {
6747 case MONO_PATCH_INFO_EXC: {
6748 MonoClass *exc_class;
6749 unsigned char *ip = patch_info->ip.i + cfg->native_code;
6751 i = mini_exception_id_by_name (patch_info->data.target);
6752 if (exc_throw_pos [i]) {
6753 arm_patch (ip, exc_throw_pos [i]);
6754 patch_info->type = MONO_PATCH_INFO_NONE;
6757 exc_throw_pos [i] = code;
6759 arm_patch (ip, code);
6761 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6763 ARM_MOV_REG_REG (code, ARMREG_R1, ARMREG_LR);
6764 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_PC, 0);
6765 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
6766 patch_info->data.name = "mono_arch_throw_corlib_exception";
6767 patch_info->ip.i = code - cfg->native_code;
6769 cfg->thunk_area += THUNK_SIZE;
6770 *(guint32*)(gpointer)code = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
6780 cfg->code_len = code - cfg->native_code;
6782 g_assert (cfg->code_len < cfg->code_size);
6786 #endif /* #ifndef DISABLE_JIT */
6789 mono_arch_finish_init (void)
6794 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6799 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6806 mono_arch_print_tree (MonoInst *tree, int arity)
6816 mono_arch_get_patch_offset (guint8 *code)
6823 mono_arch_flush_register_windows (void)
6828 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6830 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6834 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6836 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6840 mono_arch_get_cie_program (void)
6844 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, ARMREG_SP, 0);
6849 /* #define ENABLE_WRONG_METHOD_CHECK 1 */
6850 #define BASE_SIZE (6 * 4)
6851 #define BSEARCH_ENTRY_SIZE (4 * 4)
6852 #define CMP_SIZE (3 * 4)
6853 #define BRANCH_SIZE (1 * 4)
6854 #define CALL_SIZE (2 * 4)
6855 #define WMC_SIZE (8 * 4)
6856 #define DISTANCE(A, B) (((gint32)(B)) - ((gint32)(A)))
6859 arm_emit_value_and_patch_ldr (arminstr_t *code, arminstr_t *target, guint32 value)
6861 guint32 delta = DISTANCE (target, code);
6863 g_assert (delta >= 0 && delta <= 0xFFF);
6864 *target = *target | delta;
6869 #ifdef ENABLE_WRONG_METHOD_CHECK
6871 mini_dump_bad_imt (int input_imt, int compared_imt, int pc)
6873 g_print ("BAD IMT comparing %x with expected %x at ip %x", input_imt, compared_imt, pc);
6879 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6880 gpointer fail_tramp)
6883 arminstr_t *code, *start;
6884 gboolean large_offsets = FALSE;
6885 guint32 **constant_pool_starts;
6886 arminstr_t *vtable_target = NULL;
6887 int extra_space = 0;
6888 #ifdef ENABLE_WRONG_METHOD_CHECK
6894 constant_pool_starts = g_new0 (guint32*, count);
6896 for (i = 0; i < count; ++i) {
6897 MonoIMTCheckItem *item = imt_entries [i];
6898 if (item->is_equals) {
6899 gboolean fail_case = !item->check_target_idx && fail_tramp;
6901 if (item->has_target_code || !arm_is_imm12 (DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]))) {
6902 item->chunk_size += 32;
6903 large_offsets = TRUE;
6906 if (item->check_target_idx || fail_case) {
6907 if (!item->compare_done || fail_case)
6908 item->chunk_size += CMP_SIZE;
6909 item->chunk_size += BRANCH_SIZE;
6911 #ifdef ENABLE_WRONG_METHOD_CHECK
6912 item->chunk_size += WMC_SIZE;
6916 item->chunk_size += 16;
6917 large_offsets = TRUE;
6919 item->chunk_size += CALL_SIZE;
6921 item->chunk_size += BSEARCH_ENTRY_SIZE;
6922 imt_entries [item->check_target_idx]->compare_done = TRUE;
6924 size += item->chunk_size;
6928 size += 4 * count; /* The ARM_ADD_REG_IMM to pop the stack */
6931 code = mono_method_alloc_generic_virtual_thunk (domain, size);
6933 code = mono_domain_code_reserve (domain, size);
6936 unwind_ops = mono_arch_get_cie_program ();
6939 g_print ("Building IMT thunk for class %s %s entries %d code size %d code at %p end %p vtable %p fail_tramp %p\n", vtable->klass->name_space, vtable->klass->name, count, size, start, ((guint8*)start) + size, vtable, fail_tramp);
6940 for (i = 0; i < count; ++i) {
6941 MonoIMTCheckItem *item = imt_entries [i];
6942 g_print ("method %d (%p) %s vtable slot %p is_equals %d chunk size %d\n", i, item->key, ((MonoMethod*)item->key)->name, &vtable->vtable [item->value.vtable_slot], item->is_equals, item->chunk_size);
6946 if (large_offsets) {
6947 ARM_PUSH4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
6948 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 4 * sizeof (mgreg_t));
6950 ARM_PUSH2 (code, ARMREG_R0, ARMREG_R1);
6951 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
6953 ARM_LDR_IMM (code, ARMREG_R0, ARMREG_LR, -4);
6954 vtable_target = code;
6955 ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
6956 ARM_MOV_REG_REG (code, ARMREG_R0, ARMREG_V5);
6958 for (i = 0; i < count; ++i) {
6959 MonoIMTCheckItem *item = imt_entries [i];
6960 arminstr_t *imt_method = NULL, *vtable_offset_ins = NULL, *target_code_ins = NULL;
6961 gint32 vtable_offset;
6963 item->code_target = (guint8*)code;
6965 if (item->is_equals) {
6966 gboolean fail_case = !item->check_target_idx && fail_tramp;
6968 if (item->check_target_idx || fail_case) {
6969 if (!item->compare_done || fail_case) {
6971 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6972 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6974 item->jmp_code = (guint8*)code;
6975 ARM_B_COND (code, ARMCOND_NE, 0);
6977 /*Enable the commented code to assert on wrong method*/
6978 #ifdef ENABLE_WRONG_METHOD_CHECK
6980 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
6981 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
6983 ARM_B_COND (code, ARMCOND_EQ, 0);
6985 /* Define this if your system is so bad that gdb is failing. */
6986 #ifdef BROKEN_DEV_ENV
6987 ARM_MOV_REG_REG (code, ARMREG_R2, ARMREG_PC);
6989 arm_patch (code - 1, mini_dump_bad_imt);
6993 arm_patch (cond, code);
6997 if (item->has_target_code) {
6998 /* Load target address */
6999 target_code_ins = code;
7000 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7001 /* Save it to the fourth slot */
7002 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7003 /* Restore registers and branch */
7004 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7006 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)item->value.target_code);
7008 vtable_offset = DISTANCE (vtable, &vtable->vtable[item->value.vtable_slot]);
7009 if (!arm_is_imm12 (vtable_offset)) {
7011 * We need to branch to a computed address but we don't have
7012 * a free register to store it, since IP must contain the
7013 * vtable address. So we push the two values to the stack, and
7014 * load them both using LDM.
7016 /* Compute target address */
7017 vtable_offset_ins = code;
7018 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7019 ARM_LDR_REG_REG (code, ARMREG_R1, ARMREG_IP, ARMREG_R1);
7020 /* Save it to the fourth slot */
7021 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7022 /* Restore registers and branch */
7023 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7025 code = arm_emit_value_and_patch_ldr (code, vtable_offset_ins, vtable_offset);
7027 ARM_POP2 (code, ARMREG_R0, ARMREG_R1);
7028 if (large_offsets) {
7029 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 2 * sizeof (mgreg_t));
7030 ARM_ADD_REG_IMM8 (code, ARMREG_SP, ARMREG_SP, 2 * sizeof (gpointer));
7032 mono_add_unwind_op_def_cfa_offset (unwind_ops, code, start, 0);
7033 ARM_LDR_IMM (code, ARMREG_PC, ARMREG_IP, vtable_offset);
7038 arm_patch (item->jmp_code, (guchar*)code);
7040 target_code_ins = code;
7041 /* Load target address */
7042 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7043 /* Save it to the fourth slot */
7044 ARM_STR_IMM (code, ARMREG_R1, ARMREG_SP, 3 * sizeof (gpointer));
7045 /* Restore registers and branch */
7046 ARM_POP4 (code, ARMREG_R0, ARMREG_R1, ARMREG_IP, ARMREG_PC);
7048 code = arm_emit_value_and_patch_ldr (code, target_code_ins, (gsize)fail_tramp);
7049 item->jmp_code = NULL;
7053 code = arm_emit_value_and_patch_ldr (code, imt_method, (guint32)item->key);
7055 /*must emit after unconditional branch*/
7056 if (vtable_target) {
7057 code = arm_emit_value_and_patch_ldr (code, vtable_target, (guint32)vtable);
7058 item->chunk_size += 4;
7059 vtable_target = NULL;
7062 /*We reserve the space for bsearch IMT values after the first entry with an absolute jump*/
7063 constant_pool_starts [i] = code;
7065 code += extra_space;
7069 ARM_LDR_IMM (code, ARMREG_R1, ARMREG_PC, 0);
7070 ARM_CMP_REG_REG (code, ARMREG_R0, ARMREG_R1);
7072 item->jmp_code = (guint8*)code;
7073 ARM_B_COND (code, ARMCOND_HS, 0);
7078 for (i = 0; i < count; ++i) {
7079 MonoIMTCheckItem *item = imt_entries [i];
7080 if (item->jmp_code) {
7081 if (item->check_target_idx)
7082 arm_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7084 if (i > 0 && item->is_equals) {
7086 arminstr_t *space_start = constant_pool_starts [i];
7087 for (j = i - 1; j >= 0 && !imt_entries [j]->is_equals; --j) {
7088 space_start = arm_emit_value_and_patch_ldr (space_start, (arminstr_t*)imt_entries [j]->code_target, (guint32)imt_entries [j]->key);
7095 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
7096 mono_disassemble_code (NULL, (guint8*)start, size, buff);
7101 g_free (constant_pool_starts);
7103 mono_arch_flush_icache ((guint8*)start, size);
7104 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7105 mono_stats.imt_thunks_size += code - start;
7107 g_assert (DISTANCE (start, code) <= size);
7109 mono_tramp_info_register (mono_tramp_info_create (NULL, (guint8*)start, DISTANCE (start, code), NULL, unwind_ops), domain);
7115 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7117 return ctx->regs [reg];
7121 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
7123 ctx->regs [reg] = val;
7127 * mono_arch_get_trampolines:
7129 * Return a list of MonoTrampInfo structures describing arch specific trampolines
7133 mono_arch_get_trampolines (gboolean aot)
7135 return mono_arm_get_exception_trampolines (aot);
7139 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7146 bp = MONO_CONTEXT_GET_BP (ctx);
7147 lr_loc = (gpointer*)(bp + clause->exvar_offset);
7149 old_value = *lr_loc;
7150 if ((char*)old_value < (char*)ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7153 *lr_loc = new_value;
7158 #if defined(MONO_ARCH_SOFT_DEBUG_SUPPORTED)
7160 * mono_arch_set_breakpoint:
7162 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7163 * The location should contain code emitted by OP_SEQ_POINT.
7166 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7169 guint32 native_offset = ip - (guint8*)ji->code_start;
7170 MonoDebugOptions *opt = mini_get_debug_options ();
7172 if (opt->soft_breakpoints) {
7173 g_assert (!ji->from_aot);
7175 ARM_BLX_REG (code, ARMREG_LR);
7176 mono_arch_flush_icache (code - 4, 4);
7177 } else if (ji->from_aot) {
7178 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7180 g_assert (native_offset % 4 == 0);
7181 g_assert (info->bp_addrs [native_offset / 4] == 0);
7182 info->bp_addrs [native_offset / 4] = bp_trigger_page;
7184 int dreg = ARMREG_LR;
7186 /* Read from another trigger page */
7187 ARM_LDR_IMM (code, dreg, ARMREG_PC, 0);
7189 *(int*)code = (int)bp_trigger_page;
7191 ARM_LDR_IMM (code, dreg, dreg, 0);
7193 mono_arch_flush_icache (code - 16, 16);
7196 /* This is currently implemented by emitting an SWI instruction, which
7197 * qemu/linux seems to convert to a SIGILL.
7199 *(int*)code = (0xef << 24) | 8;
7201 mono_arch_flush_icache (code - 4, 4);
7207 * mono_arch_clear_breakpoint:
7209 * Clear the breakpoint at IP.
7212 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7214 MonoDebugOptions *opt = mini_get_debug_options ();
7218 if (opt->soft_breakpoints) {
7219 g_assert (!ji->from_aot);
7222 mono_arch_flush_icache (code - 4, 4);
7223 } else if (ji->from_aot) {
7224 guint32 native_offset = ip - (guint8*)ji->code_start;
7225 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
7227 g_assert (native_offset % 4 == 0);
7228 g_assert (info->bp_addrs [native_offset / 4] == bp_trigger_page);
7229 info->bp_addrs [native_offset / 4] = 0;
7231 for (i = 0; i < 4; ++i)
7234 mono_arch_flush_icache (ip, code - ip);
7239 * mono_arch_start_single_stepping:
7241 * Start single stepping.
7244 mono_arch_start_single_stepping (void)
7246 if (ss_trigger_page)
7247 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7249 single_step_tramp = mini_get_single_step_trampoline ();
7253 * mono_arch_stop_single_stepping:
7255 * Stop single stepping.
7258 mono_arch_stop_single_stepping (void)
7260 if (ss_trigger_page)
7261 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7263 single_step_tramp = NULL;
7267 #define DBG_SIGNAL SIGBUS
7269 #define DBG_SIGNAL SIGSEGV
7273 * mono_arch_is_single_step_event:
7275 * Return whenever the machine state in SIGCTX corresponds to a single
7279 mono_arch_is_single_step_event (void *info, void *sigctx)
7281 siginfo_t *sinfo = info;
7283 if (!ss_trigger_page)
7286 /* Sometimes the address is off by 4 */
7287 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7294 * mono_arch_is_breakpoint_event:
7296 * Return whenever the machine state in SIGCTX corresponds to a breakpoint event.
7299 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7301 siginfo_t *sinfo = info;
7303 if (!ss_trigger_page)
7306 if (sinfo->si_signo == DBG_SIGNAL) {
7307 /* Sometimes the address is off by 4 */
7308 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7318 * mono_arch_skip_breakpoint:
7320 * See mini-amd64.c for docs.
7323 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
7325 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7329 * mono_arch_skip_single_step:
7331 * See mini-amd64.c for docs.
7334 mono_arch_skip_single_step (MonoContext *ctx)
7336 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 4);
7339 #endif /* MONO_ARCH_SOFT_DEBUG_SUPPORTED */
7342 * mono_arch_get_seq_point_info:
7344 * See mini-amd64.c for docs.
7347 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7352 // FIXME: Add a free function
7354 mono_domain_lock (domain);
7355 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
7357 mono_domain_unlock (domain);
7360 ji = mono_jit_info_table_find (domain, (char*)code);
7363 info = g_malloc0 (sizeof (SeqPointInfo) + ji->code_size);
7365 info->ss_trigger_page = ss_trigger_page;
7366 info->bp_trigger_page = bp_trigger_page;
7368 mono_domain_lock (domain);
7369 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
7371 mono_domain_unlock (domain);
7378 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
7380 ext->lmf.previous_lmf = prev_lmf;
7381 /* Mark that this is a MonoLMFExt */
7382 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
7383 ext->lmf.sp = (gssize)ext;
7387 * mono_arch_set_target:
7389 * Set the target architecture the JIT backend should generate code for, in the form
7390 * of a GNU target triplet. Only used in AOT mode.
7393 mono_arch_set_target (char *mtriple)
7395 /* The GNU target triple format is not very well documented */
7396 if (strstr (mtriple, "armv7")) {
7397 v5_supported = TRUE;
7398 v6_supported = TRUE;
7399 v7_supported = TRUE;
7401 if (strstr (mtriple, "armv6")) {
7402 v5_supported = TRUE;
7403 v6_supported = TRUE;
7405 if (strstr (mtriple, "armv7s")) {
7406 v7s_supported = TRUE;
7408 if (strstr (mtriple, "armv7k")) {
7409 v7k_supported = TRUE;
7411 if (strstr (mtriple, "thumbv7s")) {
7412 v5_supported = TRUE;
7413 v6_supported = TRUE;
7414 v7_supported = TRUE;
7415 v7s_supported = TRUE;
7416 thumb_supported = TRUE;
7417 thumb2_supported = TRUE;
7419 if (strstr (mtriple, "darwin") || strstr (mtriple, "ios")) {
7420 v5_supported = TRUE;
7421 v6_supported = TRUE;
7422 thumb_supported = TRUE;
7425 if (strstr (mtriple, "gnueabi"))
7426 eabi_supported = TRUE;
7430 mono_arch_opcode_supported (int opcode)
7433 case OP_ATOMIC_ADD_I4:
7434 case OP_ATOMIC_EXCHANGE_I4:
7435 case OP_ATOMIC_CAS_I4:
7436 case OP_ATOMIC_LOAD_I1:
7437 case OP_ATOMIC_LOAD_I2:
7438 case OP_ATOMIC_LOAD_I4:
7439 case OP_ATOMIC_LOAD_U1:
7440 case OP_ATOMIC_LOAD_U2:
7441 case OP_ATOMIC_LOAD_U4:
7442 case OP_ATOMIC_STORE_I1:
7443 case OP_ATOMIC_STORE_I2:
7444 case OP_ATOMIC_STORE_I4:
7445 case OP_ATOMIC_STORE_U1:
7446 case OP_ATOMIC_STORE_U2:
7447 case OP_ATOMIC_STORE_U4:
7448 return v7_supported;
7449 case OP_ATOMIC_LOAD_R4:
7450 case OP_ATOMIC_LOAD_R8:
7451 case OP_ATOMIC_STORE_R4:
7452 case OP_ATOMIC_STORE_R8:
7453 return v7_supported && IS_VFP;
7460 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
7462 return get_call_info (mp, sig);