3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
10 ADDR_WIDTH : integer range 1 to integer'high;
11 DATA_WIDTH : integer range 1 to integer'high
17 wr_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
20 data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
23 data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
25 end component r_w_ram;
27 component r_w_ram_be is
29 ADDR_WIDTH : integer range 1 to integer'high
34 waddr, raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
36 be : in std_logic_vector (3 downto 0);
40 wdata : in std_logic_vector(31 downto 0);
42 q : out std_logic_vector(31 downto 0)
44 end component r_w_ram_be;
46 component ram_xilinx is
48 ADDR_WIDTH : integer range 1 to integer'high
53 waddr, raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
55 be : in std_logic_vector (3 downto 0);
59 wdata : in std_logic_vector(31 downto 0);
61 q : out std_logic_vector(31 downto 0)
63 end component ram_xilinx;
67 ADDR_WIDTH : integer range 1 to integer'high;
68 DATA_WIDTH : integer range 1 to integer'high
74 rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
76 data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
82 ADDR_WIDTH : integer range 1 to integer'high;
83 DATA_WIDTH : integer range 1 to integer'high
89 wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0);
92 data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
95 data_out1, data_out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
97 end component r2_w_ram;
101 ADDR_WIDTH : integer range 1 to integer'high;
102 DATA_WIDTH : integer range 1 to integer'high
108 rw_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
110 wr_en : in std_logic;
111 data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
114 rw_out, rd_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
116 end component rw_r_ram;