2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
7 use work.extension_pkg.all;
13 sys_res : in std_logic;
14 sys_clk : in std_logic;
15 -- result : out gp_register_t;
16 -- reg_wr_data : out gp_register_t
18 bus_tx : out std_logic;
19 bus_rx : in std_logic;
21 sseg0 : out std_logic_vector(0 to 6);
22 sseg1 : out std_logic_vector(0 to 6);
23 sseg2 : out std_logic_vector(0 to 6);
24 sseg3 : out std_logic_vector(0 to 6)
29 architecture behav of core_top is
31 constant SYNC_STAGES : integer := 2;
32 constant RESET_VALUE : std_logic := '0';
34 signal jump_result : instruction_addr_t;
35 signal jump_result_pin : instruction_addr_t;
36 signal prediction_result_pin : instruction_addr_t;
37 signal branch_prediction_bit_pin : std_logic;
38 signal alu_jump_bit_pin : std_logic;
39 signal instruction_pin : instruction_word_t;
40 signal prog_cnt_pin : instruction_addr_t;
42 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
43 signal reg_wr_data_pin : gp_register_t;
44 signal reg_we_pin : std_logic;
45 signal to_next_stage : dec_op;
47 -- signal reg1_rd_data_pin : gp_register_t;
48 -- signal reg2_rd_data_pin : gp_register_t;
50 signal result_pin : gp_register_t;--reg
51 signal result_addr_pin : gp_addr_t;--reg
52 signal addr_pin : word_t; --memaddr
53 signal data_pin : gp_register_t; --mem data --ureg
54 signal alu_jump_pin : std_logic;--reg
55 signal brpr_pin : std_logic; --reg
56 signal wr_en_pin : std_logic;--regop --reg
57 signal dmem_pin : std_logic;--memop
58 signal dmem_wr_en_pin : std_logic;
59 signal hword_pin : std_logic;
60 signal byte_s_pin : std_logic;
62 signal gpm_in_pin : extmod_rec;
63 signal gpm_out_pin : gp_register_t;
64 signal nop_pin : std_logic;
66 signal sync : std_logic_vector(1 to SYNC_STAGES);
67 signal sys_res_n : std_logic;
69 signal int_req : interrupt_t;
71 signal new_im_data : std_logic;
72 signal im_addr, im_data : gp_register_t;
74 signal vers, vers_nxt : exec2wb_rec;
77 fetch_st : fetch_stage
86 clk => sys_clk, --: in std_logic;
87 reset => sys_res_n, --: in std_logic;
90 jump_result => jump_result_pin, --: in instruction_addr_t;
91 prediction_result => prediction_result_pin, --: in instruction_addr_t;
92 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
93 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
95 -- instruction memory program port :D
96 new_im_data_in => new_im_data,
100 instruction => instruction_pin, --: out instruction_word_t
101 prog_cnt => prog_cnt_pin
104 decode_st : decode_stage
106 -- active reset value
108 -- active logic value
114 clk => sys_clk, --: in std_logic;
115 reset => sys_res_n, -- : in std_logic;
118 instruction => instruction_pin, --: in instruction_word_t;
119 prog_cnt => prog_cnt_pin,
120 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
121 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
122 reg_we => reg_we_pin, --: in std_logic;
126 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
127 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
128 to_next_stage => to_next_stage
131 exec_st : execute_stage
133 port map(sys_clk, sys_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
134 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
137 vers_nxt.result <= result_pin;
138 vers_nxt.result_addr <= result_addr_pin;
139 vers_nxt.address <= addr_pin;
140 vers_nxt.ram_data <= data_pin;
141 vers_nxt.alu_jmp <= alu_jump_pin;
142 vers_nxt.br_pred <= brpr_pin;
143 vers_nxt.write_en <= wr_en_pin;
144 vers_nxt.dmem_en <= dmem_pin;
145 vers_nxt.dmem_write_en <= dmem_wr_en_pin;
146 vers_nxt.hword <= hword_pin;
147 vers_nxt.byte_s <= byte_s_pin;
149 -- writeback_st : writeback_stage
150 -- generic map('0', '1')
151 -- port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
152 -- wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
153 -- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
156 writeback_st : writeback_stage
157 generic map('0', '1', "s3e")
158 port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
159 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
160 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
161 -- instruction memory program port :D
162 new_im_data, im_addr, im_data,
163 sseg0, sseg1, sseg2, sseg3, int_req);
166 syn: process(sys_clk, sys_res)
170 if sys_res = '0' then
171 -- vers.result <= (others => '0');
172 -- vers.result_addr <= (others => '0');
173 -- vers.address <= (others => '0');
174 -- vers.ram_data <= (others => '0');
175 -- vers.alu_jmp <= '0';
176 -- vers.br_pred <= '0';
177 -- vers.write_en <= '0';
178 -- vers.dmem_en <= '0';
179 -- vers.dmem_write_en <= '0';
180 -- vers.hword <= '0';
181 -- vers.byte_s <= '0';
183 sync <= (others => '0');
185 elsif rising_edge(sys_clk) then
188 for i in 2 to SYNC_STAGES loop
189 sync(i) <= sync(i - 1);
196 sys_res_n <= sync(SYNC_STAGES);
198 --init : process(all)
201 -- jump_result_pin <= (others => '0');
202 -- alu_jump_bit_pin <= '0';
203 -- reg_w_addr_pin <= (others => '0');
204 -- reg_wr_data_pin <= (others => '0');
205 -- reg_we_pin <= '0';
209 -- result <= result_pin;
210 nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
212 jump_result <= prog_cnt_pin; --jump_result_pin;
215 -- reg_wr_data <= reg_wr_data_pin;