tx-test: transmit erfolgreich getestet :)

[hwmod.git] / src / scanner.vhd

diff --git a/src/scanner.vhd b/src/scanner.vhd
index 1710dc437888bae405c9fe804fcf1827ae4f450d..fde57048fe8c8da0aea576b2be3425ffba88eafb 100644 (file)
--- a/src/scanner.vhd
+++ b/src/scanner.vhd
@@ -18,7 +18,10 @@ entity scanner is
                s_backspace : out std_logic;
                -- Parser
                do_it : out std_logic;
-               finished : in std_logic
+               finished : in std_logic;
+               -- test: uart-tx
+               tx_data : out std_logic_vector(7 downto 0);
+               tx_new : out std_logic
        );
 end entity scanner;
 
@@ -29,11 +32,15 @@ architecture beh of scanner is
        signal s_take_int, s_take_next : std_logic;
        signal s_backspace_int, s_backspace_next : std_logic;
        signal do_it_int, do_it_next : std_logic;
+       signal tx_data_int, tx_data_next : std_logic_vector(7 downto 0);
+       signal tx_new_int, tx_new_next : std_logic;
 begin
        s_char <= s_char_int;
        s_take <= s_take_int;
        s_backspace <= s_backspace_int;
        do_it <= do_it_int;
+       tx_new <= tx_new_int;
+       tx_data <= tx_data_int;
 
        process(sys_clk, sys_res_n)
        begin
@@ -45,6 +52,8 @@ begin
                        s_take_int <= '0';
                        s_backspace_int <= '0';
                        do_it_int <= '0';
+                       tx_new_int <= '0';
+                       tx_data_int <= (others => '0');
                elsif rising_edge(sys_clk) then
                        -- internal
                        state_int <= state_next;
@@ -53,13 +62,17 @@ begin
                        s_take_int <= s_take_next;
                        s_backspace_int <= s_backspace_next;
                        do_it_int <= do_it_next;
+                       tx_new_int <= tx_new_next;
+                       tx_data_int <= tx_data_next;
                end if;
        end process;
 
        -- next state
-       process(state_int, new_data, data, finished, s_done)
+       process(state_int, new_data, data, finished, s_done, tx_data_int)
        begin
                state_next <= state_int;
+               tx_new_next <= '0';
+               tx_data_next <= tx_data_int;
 
                case state_int is
                        when SIDLE =>
@@ -106,6 +119,8 @@ begin
                                end if;
                        when SENTER =>
                                if finished = '1' then
+                                       tx_new_next <= '1';
+                                       tx_data_next <= x"42";
                                        state_next <= SIDLE;
                                end if;
                end case;