--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gen_pkg.all;
+
+entity post_parser_tb is
+end entity post_parser_tb;
+
+architecture sim of post_parser_tb is
+ component parser is
+ port (
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ -- History
+ p_rget : out std_logic;
+ p_rdone : in std_logic;
+ p_read : in hbyte;
+ p_wtake : out std_logic;
+ p_wdone : in std_logic;
+ p_write : out hbyte;
+ p_finished : out std_logic;
+ -- Scanner
+ do_it : in std_logic;
+ finished : out std_logic
+ );
+ end component parser;
+ -- system
+ signal sys_clk, sys_res_n : std_logic;
+ -- history
+ signal p_rget, p_rdone, p_wtake, p_wdone, p_finished : std_logic;
+ signal p_read, p_write : hbyte;
+ --scanner
+ signal do_it : std_logic;
+ signal finished : std_logic;
+
+ signal stop : boolean := false;
+begin
+ inst : parser
+ port map
+ (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n,
+ -- history
+ p_rget => p_rget,
+ p_rdone => p_rdone,
+ p_read => p_read,
+ p_wtake => p_wtake,
+ p_wdone => p_wdone,
+ p_write => p_write,
+ p_finished => p_finished,
+ -- Scanner
+ do_it => do_it,
+ finished => finished
+ );
+
+ process
+ begin
+ sys_clk <= '0';
+ wait for 15 ns;
+ sys_clk <= '1';
+ wait for 15 ns;
+ if stop = true then
+ wait;
+ end if;
+ end process;
+
+ process
+ -- textio stuff
+ use std.textio.all;
+ file f : text open read_mode is "../../src/parser.test";
+ variable l : line;
+
+ variable input : hstring;
+ variable expectedresult : hstring;
+ variable realresult : hstring;
+ variable hstrtmp : hstring;
+
+ variable checkall : boolean := true;
+ variable run_tc : boolean := true;
+ variable i, j, k, y : natural;
+ begin
+ -- init & reset
+ sys_res_n <= '0';
+ p_rdone <= '0';
+ p_wdone <= '0';
+ p_read <= (others => '0');
+ do_it <= '0';
+
+ icwait(sys_clk, 5);
+ sys_res_n <= '1';
+
+ i := 1;
+ f_loop : while not endfile(f) loop
+ realresult := (72 => nul, others => ' ');
+
+ f1_loop : while not endfile(f) loop
+ readline (f, l);
+ input := (others => nul);
+ if (l'length <= 72) then
+ input(1 to l'length) := l.all;
+ if (input(1) = '#') then
+ next f1_loop;
+ else
+ exit f1_loop;
+ end if;
+ else
+ report "fehler in parser.test: eingabe zu lange in testfall " & natural'image(i);
+ next f_loop;
+ end if;
+ end loop f1_loop;
+
+ f2_loop : while not endfile(f) loop
+ readline (f, l);
+ expectedresult := (others => nul);
+ if (l'length <= 72) then
+ expectedresult(1 to l'length) := l.all;
+ if (expectedresult(1) = '#') then
+ next f2_loop;
+ else
+ y := l'length;
+ exit f2_loop;
+ end if;
+ else
+ report "fehler in parser.test: eingabe zu lange in testfall " & natural'image(i);
+ next f_loop;
+ end if;
+ end loop f2_loop;
+
+ -- ergebnis string richtig formatieren
+ hstrtmp := expectedresult;
+ expectedresult := (72 => nul, others => ' ');
+ for x in 1 to 71 loop
+ if hstrtmp(x) /= nul then
+ expectedresult((71-y) + x) := hstrtmp(x);
+ end if;
+ end loop;
+
+
+ report "testcase(" & natural'image(i) & ").input: " & input;
+ report "testcase(" & natural'image(i) & ").expectedresult: " & expectedresult;
+ i := i + 1;
+
+ icwait(sys_clk, 5);
+ do_it <= '1';
+ run_tc := true;
+ j := 1; k := 71;
+
+ while run_tc loop
+ wait on p_rget, p_wtake, p_finished, finished;
+ icwait(sys_clk, 2);
+
+ if p_rget = '1' then
+ p_read <= hbyte( to_unsigned(character'pos(input(j)),8) );
+ p_rdone <= '1';
+ j := j + 1;
+ end if;
+ if p_rget = '0' then
+ p_rdone <= '0';
+ end if;
+
+ if p_wtake = '1' then
+ realresult(k) := character'val(to_integer(unsigned(p_write)));
+ p_wdone <= '1';
+ k := k - 1;
+ end if;
+ if p_wtake = '0' then
+ p_wdone <= '0';
+ end if;
+
+ if p_finished = '1' or finished = '1' then
+ run_tc := false;
+ end if;
+ end loop;
+
+ do_it <= '0';
+ report "realresult : " & realresult;
+ if realresult /= expectedresult then
+ checkall := false;
+ end if;
+ report "==================";
+ end loop f_loop;
+
+ if checkall then
+ report "alle testfaelle des Parser waren erfolgreich!";
+ else
+ report "nicht alle testfaelle des Parsers waren erfolgreich!";
+ end if;
+ stop <= true;
+ wait;
+ end process;
+end architecture sim;
projects / hwmod.git / blobdiff