pc-com: tx_done_* ist unnoetig bzw. verzoegert das ganze sogar

[hwmod.git] / src / pc_communication.vhd

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index 88a5cf88d9ea0d6f351fb476036319daefa1ff8e..976164dff4e6a429b7c8a3e9ff009059e24a065d 100644 (file)
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -30,7 +30,6 @@ architecture beh of pc_communication is
        signal zeile , zeile_next : integer range 0 to HZEILE_MAX + 1;
        signal get, get_next : std_logic;
        signal new_i, new_i_next : std_logic;
-       signal tx_done_i, tx_done_i_next : std_logic;
        signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
 
        type STATE_PC is (IDLE, FETCH, FORWARD, UART_DONE, CR, CR_WAIT,
@@ -43,7 +42,6 @@ begin
        pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
        pc_get <= get;
        tx_new <= new_i;
-       tx_done_i_next <= tx_done;
        tx_data <= tx_data_i;
 
        sync: process (sys_clk, sys_res_n)
@@ -55,19 +53,17 @@ begin
                        get <= '0';
                        new_i <= '0';
                        tx_data_i <= x"00";
-                       tx_done_i <= '0';
                elsif rising_edge(sys_clk) then
                        spalte <= spalte_next;
                        zeile <= zeile_next;
                        state <= state_next;
                        get <= get_next;
                        new_i <= new_i_next;
-                       tx_done_i <= tx_done_i_next;
                        tx_data_i <= tx_data_i_next;
                end if;
        end process sync;
 
-       process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char, rx_new, btn_a,
+       process (state, zeile, spalte, tx_data_i, tx_done, pc_char, rx_new, btn_a,
                        pc_done, rx_data)
                variable tmp : std_logic_vector(6 downto 0);
        begin
@@ -82,70 +78,70 @@ begin
                        when IDLE =>
                                zeile_next <= 0;
                                spalte_next <= 1;
-                               if ((rx_new = '1' and rx_data = x"41") or btn_a = '0') and tx_done_i = '0' then
+                               if ((rx_new = '1' and rx_data = x"41") or btn_a = '0') and tx_done = '0' then
                                        state_next <= PRINT_NO1;
                                end if;
 
                        when PRINT_NO1 =>
                                tx_data_i_next <= x"28"; -- '('
                                new_i_next <= '1';
-                               if tx_done_i = '1' then
+                               if tx_done = '1' then
                                        state_next <= PRINT_NO1_WAIT;
                                end if;
                        when PRINT_NO1_WAIT =>
-                               if tx_done_i = '0' then
+                               if tx_done = '0' then
                                        state_next <= PRINT_NO2;
                                end if;
                        when PRINT_NO2 =>
                                tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 1);
                                new_i_next <= '1';
-                               if tx_done_i = '1' then
+                               if tx_done = '1' then
                                        state_next <= PRINT_NO2_WAIT;
                                end if;
                        when PRINT_NO2_WAIT =>
-                               if tx_done_i = '0' then
+                               if tx_done = '0' then
                                        state_next <= PRINT_NO3;
                                end if;
                        when PRINT_NO3 =>
                                tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 2);
                                new_i_next <= '1';
-                               if tx_done_i = '1' then
+                               if tx_done = '1' then
                                        state_next <= PRINT_NO3_WAIT;
                                end if;
                        when PRINT_NO3_WAIT =>
-                               if tx_done_i = '0' then
+                               if tx_done = '0' then
                                        state_next <= PRINT_NO4;
                                end if;
                        when PRINT_NO4 =>
                                tx_data_i_next <= x"29"; -- ')'
                                new_i_next <= '1';
-                               if tx_done_i = '1' then
+                               if tx_done = '1' then
                                        state_next <= PRINT_NO4_WAIT;
                                end if;
                        when PRINT_NO4_WAIT =>
-                               if tx_done_i = '0' then
+                               if tx_done = '0' then
                                        state_next <= PRINT_NO5;
                                end if;
                        when PRINT_NO5 =>
                                tx_data_i_next <= x"24"; -- '$'
                                new_i_next <= '1';
-                               if tx_done_i = '1' then
+                               if tx_done = '1' then
                                        state_next <= PRINT_NO5_WAIT;
                                end if;
                        when PRINT_NO5_WAIT =>
-                               if tx_done_i = '0' then
+                               if tx_done = '0' then
                                        state_next <= PRINT_NO6;
                                end if;
                        when PRINT_NO6 =>
                                tx_data_i_next <= x"20"; -- ' '
                                new_i_next <= '1';
-                               if tx_done_i = '1' then
+                               if tx_done = '1' then
                                        state_next <= FETCH;
                                end if;
 
                        when FETCH =>
                                get_next <= '1';
-                               if pc_done = '1' and tx_done_i = '0' then
+                               if pc_done = '1' and tx_done = '0' then
                                        state_next <= FORWARD;
                                        if pc_char = x"00" then
                                                state_next <= UART_DONE;
@@ -157,11 +153,11 @@ begin
                                -- halte pc_get weiterhin high sodass pc_char garantiert
                                -- gleicht bleibt (blockiert history!)
                                get_next <= '1';
-                               if tx_done_i = '1' then
+                               if tx_done = '1' then
                                        state_next <= UART_DONE;
                                end if;
                        when UART_DONE =>
-                               if tx_done_i = '0' then
+                               if tx_done = '0' then
                                        state_next <= FETCH;
                                        spalte_next <= spalte + 1;
                                        if spalte = HSPALTE_MAX + 1 then
@@ -173,21 +169,21 @@ begin
                        when NL =>
                                tx_data_i_next <= x"0a";
                                new_i_next <= '1';
-                               if tx_done_i = '1' then
+                               if tx_done = '1' then
                                        state_next <= NL_WAIT;
                                end if;
                        when NL_WAIT =>
-                               if tx_done_i = '0' then
+                               if tx_done = '0' then
                                        state_next <= CR;
                                end if;
                        when CR =>
                                tx_data_i_next <= x"0d";
                                new_i_next <= '1';
-                               if tx_done_i = '1' then
+                               if tx_done = '1' then
                                        state_next <= CR_WAIT;
                                end if;
                        when CR_WAIT =>
-                               if tx_done_i = '0' then
+                               if tx_done = '0' then
                                        tmp := std_logic_vector(to_unsigned(zeile,7));
                                        if tmp(0) = '0' then
                                                -- es handelt sich um eingabe im naechsten schritt